Re: [PATCH v2 5/5] drm/amdgpu:add VCN booting with firmware loaded by PSP

2018-08-20 Thread Michel Dänzer 
On 2018-08-18 01:25 AM, Felix Kuehling wrote:
> ROCm CQE is seeing what looks like hangs during amdgpu initialization on
> Raven and Vega20. Amdgpu basically stops printing messages while trying
> to load VCN firmware. It never completes initialization, but there is no
> obvious error message.

What does "never" mean exactly? :) I.e. how long have you waited?

If it does continue after a few minutes, it sounds like the firmware
isn't available in the same place where the driver is loaded from, i.e.
either the driver is loaded from initrd but the firmware isn't available
there, or the driver is built into the kernel, but the firmware isn't
built into the kernel.


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
___
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Re: [PATCH v2 5/5] drm/amdgpu:add VCN booting with firmware loaded by PSP

2018-08-20 Thread Zhu, James 
Hi Felix,


We did test on both China team and Makham team. Also Embedded team did the test 
also on release 18.20 for Raven.


Please let ROCm CQE team issue a JIRA ticket and the detail reproduce step.


Thanks & Best Regards!


James Zhu


From: amd-gfx  on behalf of Felix 
Kuehling 
Sent: Friday, August 17, 2018 7:25:53 PM
To: James Zhu; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander; Gao, Likun; Zhu, James; Huang, Ray
Subject: Re: [PATCH v2 5/5] drm/amdgpu:add VCN booting with firmware loaded by 
PSP

ROCm CQE is seeing what looks like hangs during amdgpu initialization on
Raven and Vega20. Amdgpu basically stops printing messages while trying
to load VCN firmware. It never completes initialization, but there is no
obvious error message. These are the last messages from amdgpu in the log:

[1.282661] [drm] Found VCN firmware Version: 1.24 Family ID: 18
[1.282664] [drm] PSP loading VCN firmware
[1.303164] [drm] reserve 0x40 from 0xf400e0 for PSP TMR SIZE

Any applications trying to use /dev/dri/* hang with a backtrace like below.

Was this change expected to affect Raven and Vega20? Has it been tested
before submitting? Do we need updated VCN firmware for it to work?

Thanks,
  Felix

[  363.352985] INFO: task gpu-manager:937 blocked for more than 120 seconds.
[  363.352995]   Not tainted 4.18.0-rc1-kfd-compute-roc-master-8912 #1
[  363.352999] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this 
message.
[  363.353004] gpu-manager D0   937  1 0x
[  363.353008] Call Trace:
[  363.353018]  ? __schedule+0x3d9/0x8b0
[  363.353023]  schedule+0x32/0x80
[  363.353026]  schedule_preempt_disabled+0xa/0x10
[  363.353028]  __mutex_lock.isra.4+0x2ae/0x4e0
[  363.353031]  ? _cond_resched+0x16/0x40
[  363.353048]  ? drm_stub_open+0x2e/0x100 [drm]
[  363.353063]  drm_stub_open+0x2e/0x100 [drm]
[  363.353069]  chrdev_open+0xbe/0x1a0
[  363.353072]  ? cdev_put+0x20/0x20
[  363.353075]  do_dentry_open+0x1e2/0x300
[  363.353078]  path_openat+0x2b4/0x14b0
[  363.353082]  ? vsnprintf+0x230/0x4c0
[  363.353086]  ? __alloc_pages_nodemask+0x100/0x290
[  363.353088]  do_filp_open+0x99/0x110
[  363.353092]  ? generic_update_time+0x6a/0xc0
[  363.353094]  ? touch_atime+0xc1/0xd0
[  363.353096]  ? _cond_resched+0x16/0x40
[  363.353100]  ? do_sys_open+0x126/0x210
[  363.353102]  do_sys_open+0x126/0x210
[  363.353106]  do_syscall_64+0x4f/0x100
[  363.353110]  entry_SYSCALL_64_after_hwframe+0x44/0xa9
[  363.353113] RIP: 0033:0x7f988f340040
[  363.353113] Code: Bad RIP value.
[  363.353120] RSP: 002b:7ffecdefe618 EFLAGS: 0246 ORIG_RAX: 
0002
[  363.353123] RAX: ffda RBX: 02337cd0 RCX: 7f988f340040
[  363.353124] RDX: 7ffecdefe67e RSI: 0002 RDI: 7ffecdefe670
[  363.353125] RBP: 7ffecdefe6a0 R08:  R09: 000e
[  363.353126] R10: 069d R11: 0246 R12: 00401b40
[  363.353127] R13: 7ffecdefe910 R14:  R15: 



On 2018-08-09 12:31 PM, James Zhu wrote:
> From: Likun Gao 
>
> Setup psp firmware loading for VCN, and make VCN block
> booting from tmr mac address.
>
> Signed-off-by: James Zhu 
> Reviewed-by: Alex Deucher 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 17 +--
>  drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c   | 38 
> ++---
>  2 files changed, 40 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> index 878f62c..77c192a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> @@ -111,9 +111,10 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
>version_major, version_minor, family_id);
>}
>
> - bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8)
> -   +  AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_HEAP_SIZE
> + bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_HEAP_SIZE
>  +  AMDGPU_VCN_SESSION_SIZE * 40;
> + if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
> + bo_size += 
> AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
>r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
>AMDGPU_GEM_DOMAIN_VRAM, >vcn.vcpu_bo,
>>vcn.gpu_addr, >vcn.cpu_addr);
> @@ -189,11 +190,13 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev)
>unsigned offset;
>
>hdr = (const struct common_firmware_header 
> *)adev->vcn.fw->data;
> - offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
> - memcpy_toio(adev->vcn.cpu_addr, adev->

Re: [PATCH v2 5/5] drm/amdgpu:add VCN booting with firmware loaded by PSP

2018-08-17 Thread Felix Kuehling 
ROCm CQE is seeing what looks like hangs during amdgpu initialization on
Raven and Vega20. Amdgpu basically stops printing messages while trying
to load VCN firmware. It never completes initialization, but there is no
obvious error message. These are the last messages from amdgpu in the log:

[1.282661] [drm] Found VCN firmware Version: 1.24 Family ID: 18
[1.282664] [drm] PSP loading VCN firmware
[1.303164] [drm] reserve 0x40 from 0xf400e0 for PSP TMR SIZE

Any applications trying to use /dev/dri/* hang with a backtrace like below.

Was this change expected to affect Raven and Vega20? Has it been tested
before submitting? Do we need updated VCN firmware for it to work?

Thanks,
  Felix

[  363.352985] INFO: task gpu-manager:937 blocked for more than 120 seconds.
[  363.352995]   Not tainted 4.18.0-rc1-kfd-compute-roc-master-8912 #1
[  363.352999] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this 
message.
[  363.353004] gpu-manager D0   937  1 0x
[  363.353008] Call Trace:
[  363.353018]  ? __schedule+0x3d9/0x8b0
[  363.353023]  schedule+0x32/0x80
[  363.353026]  schedule_preempt_disabled+0xa/0x10
[  363.353028]  __mutex_lock.isra.4+0x2ae/0x4e0
[  363.353031]  ? _cond_resched+0x16/0x40
[  363.353048]  ? drm_stub_open+0x2e/0x100 [drm]
[  363.353063]  drm_stub_open+0x2e/0x100 [drm]
[  363.353069]  chrdev_open+0xbe/0x1a0
[  363.353072]  ? cdev_put+0x20/0x20
[  363.353075]  do_dentry_open+0x1e2/0x300
[  363.353078]  path_openat+0x2b4/0x14b0
[  363.353082]  ? vsnprintf+0x230/0x4c0
[  363.353086]  ? __alloc_pages_nodemask+0x100/0x290
[  363.353088]  do_filp_open+0x99/0x110
[  363.353092]  ? generic_update_time+0x6a/0xc0
[  363.353094]  ? touch_atime+0xc1/0xd0
[  363.353096]  ? _cond_resched+0x16/0x40
[  363.353100]  ? do_sys_open+0x126/0x210
[  363.353102]  do_sys_open+0x126/0x210
[  363.353106]  do_syscall_64+0x4f/0x100
[  363.353110]  entry_SYSCALL_64_after_hwframe+0x44/0xa9
[  363.353113] RIP: 0033:0x7f988f340040
[  363.353113] Code: Bad RIP value.
[  363.353120] RSP: 002b:7ffecdefe618 EFLAGS: 0246 ORIG_RAX: 
0002
[  363.353123] RAX: ffda RBX: 02337cd0 RCX: 7f988f340040
[  363.353124] RDX: 7ffecdefe67e RSI: 0002 RDI: 7ffecdefe670
[  363.353125] RBP: 7ffecdefe6a0 R08:  R09: 000e
[  363.353126] R10: 069d R11: 0246 R12: 00401b40
[  363.353127] R13: 7ffecdefe910 R14:  R15: 



On 2018-08-09 12:31 PM, James Zhu wrote:
> From: Likun Gao 
>
> Setup psp firmware loading for VCN, and make VCN block
> booting from tmr mac address.
>
> Signed-off-by: James Zhu 
> Reviewed-by: Alex Deucher 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 17 +--
>  drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c   | 38 
> ++---
>  2 files changed, 40 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> index 878f62c..77c192a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> @@ -111,9 +111,10 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
>   version_major, version_minor, family_id);
>   }
>  
> - bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8)
> -   +  AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_HEAP_SIZE
> + bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_HEAP_SIZE
> +  AMDGPU_VCN_SESSION_SIZE * 40;
> + if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
> + bo_size += 
> AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
>   r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
>   AMDGPU_GEM_DOMAIN_VRAM, >vcn.vcpu_bo,
>   >vcn.gpu_addr, >vcn.cpu_addr);
> @@ -189,11 +190,13 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev)
>   unsigned offset;
>  
>   hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
> - offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
> - memcpy_toio(adev->vcn.cpu_addr, adev->vcn.fw->data + offset,
> - le32_to_cpu(hdr->ucode_size_bytes));
> - size -= le32_to_cpu(hdr->ucode_size_bytes);
> - ptr += le32_to_cpu(hdr->ucode_size_bytes);
> + if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
> + offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
> + memcpy_toio(adev->vcn.cpu_addr, adev->vcn.fw->data + 
> offset,
> + le32_to_cpu(hdr->ucode_size_bytes));
> + size -= le32_to_cpu(hdr->ucode_size_bytes);
> + ptr += le32_to_cpu(hdr->ucode_size_bytes);
> + }
>   memset_io(ptr, 0, size);
>   }
>  
> diff

Re: [PATCH v2 5/5] drm/amdgpu:add VCN booting with firmware loaded by PSP

2018-08-13 Thread James Zhu 
PSP engine only allocate space for firmware. 
mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW/HIGH is for firmware TMR address.


The other two address are for HEAP/Session.


Regards!

James Zhu


On 2018-08-13 12:16 AM, Quan, Evan wrote:


Why only the mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW/HIGH use the new 
tmr_mc_addr? And the mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW/HIGH and 
mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW/HIGH still use the old 
adev->vcn.gpu_addr?



Regards,

Evan


*From:* amd-gfx  on behalf of 
James Zhu 

*Sent:* Friday, August 10, 2018 12:31:42 AM
*To:* amd-gfx@lists.freedesktop.org
*Cc:* Deucher, Alexander; Gao, Likun; Zhu, James; Huang, Ray
*Subject:* [PATCH v2 5/5] drm/amdgpu:add VCN booting with firmware 
loaded by PSP

From: Likun Gao 

Setup psp firmware loading for VCN, and make VCN block
booting from tmr mac address.

Signed-off-by: James Zhu 
Reviewed-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 17 +--
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c   | 38 
++---

 2 files changed, 40 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c

index 878f62c..77c192a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -111,9 +111,10 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
 version_major, version_minor, family_id);
 }

-   bo_size = 
AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8)

- +  AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_HEAP_SIZE
+   bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_HEAP_SIZE
   +  AMDGPU_VCN_SESSION_SIZE * 40;
+   if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
+   bo_size += 
AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);

 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM, >vcn.vcpu_bo,
>vcn.gpu_addr, >vcn.cpu_addr);
@@ -189,11 +190,13 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev)
 unsigned offset;

 hdr = (const struct common_firmware_header 
*)adev->vcn.fw->data;

-   offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
-   memcpy_toio(adev->vcn.cpu_addr, adev->vcn.fw->data + 
offset,

- le32_to_cpu(hdr->ucode_size_bytes));
-   size -= le32_to_cpu(hdr->ucode_size_bytes);
-   ptr += le32_to_cpu(hdr->ucode_size_bytes);
+   if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
+   offset = 
le32_to_cpu(hdr->ucode_array_offset_bytes);
+   memcpy_toio(adev->vcn.cpu_addr, 
adev->vcn.fw->data + offset,

+ le32_to_cpu(hdr->ucode_size_bytes));
+   size -= le32_to_cpu(hdr->ucode_size_bytes);
+   ptr += le32_to_cpu(hdr->ucode_size_bytes);
+   }
 memset_io(ptr, 0, size);
 }

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

index 2ce91a7..74c4ef4 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -100,6 +100,16 @@ static int vcn_v1_0_sw_init(void *handle)
 if (r)
 return r;

+   if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+   const struct common_firmware_header *hdr;
+   hdr = (const struct common_firmware_header 
*)adev->vcn.fw->data;
+ adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = 
AMDGPU_UCODE_ID_VCN;

+ adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
+   adev->firmware.fw_size +=
+ ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
+   DRM_INFO("PSP loading VCN firmware\n");
+   }
+
 r = amdgpu_vcn_resume(adev);
 if (r)
 return r;
@@ -265,26 +275,38 @@ static int vcn_v1_0_resume(void *handle)
 static void vcn_v1_0_mc_resume(struct amdgpu_device *adev)
 {
 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
-
-   WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
+   uint32_t offset;
+
+   if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+   WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
+ (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
+   WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
+ (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));
+   WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
+   offset = 0;
+   } else {
+   WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
lower_32_bits(adev->vcn.gpu_addr));
-   WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACH

Re: [PATCH v2 5/5] drm/amdgpu:add VCN booting with firmware loaded by PSP

2018-08-12 Thread Quan, Evan 
Why only the mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW/HIGH use the new tmr_mc_addr? 
And the mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW/HIGH and 
mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW/HIGH still use the old adev->vcn.gpu_addr?


Regards,

Evan


From: amd-gfx  on behalf of James Zhu 

Sent: Friday, August 10, 2018 12:31:42 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander; Gao, Likun; Zhu, James; Huang, Ray
Subject: [PATCH v2 5/5] drm/amdgpu:add VCN booting with firmware loaded by PSP

From: Likun Gao 

Setup psp firmware loading for VCN, and make VCN block
booting from tmr mac address.

Signed-off-by: James Zhu 
Reviewed-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 17 +--
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c   | 38 ++---
 2 files changed, 40 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 878f62c..77c192a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -111,9 +111,10 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
 version_major, version_minor, family_id);
 }

-   bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8)
- +  AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_HEAP_SIZE
+   bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_HEAP_SIZE
   +  AMDGPU_VCN_SESSION_SIZE * 40;
+   if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
+   bo_size += 
AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
 AMDGPU_GEM_DOMAIN_VRAM, >vcn.vcpu_bo,
 >vcn.gpu_addr, >vcn.cpu_addr);
@@ -189,11 +190,13 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev)
 unsigned offset;

 hdr = (const struct common_firmware_header 
*)adev->vcn.fw->data;
-   offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
-   memcpy_toio(adev->vcn.cpu_addr, adev->vcn.fw->data + offset,
-   le32_to_cpu(hdr->ucode_size_bytes));
-   size -= le32_to_cpu(hdr->ucode_size_bytes);
-   ptr += le32_to_cpu(hdr->ucode_size_bytes);
+   if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
+   offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
+   memcpy_toio(adev->vcn.cpu_addr, adev->vcn.fw->data + 
offset,
+   le32_to_cpu(hdr->ucode_size_bytes));
+   size -= le32_to_cpu(hdr->ucode_size_bytes);
+   ptr += le32_to_cpu(hdr->ucode_size_bytes);
+   }
 memset_io(ptr, 0, size);
 }

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 2ce91a7..74c4ef4 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -100,6 +100,16 @@ static int vcn_v1_0_sw_init(void *handle)
 if (r)
 return r;

+   if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+   const struct common_firmware_header *hdr;
+   hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
+   adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = 
AMDGPU_UCODE_ID_VCN;
+   adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
+   adev->firmware.fw_size +=
+   ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
+   DRM_INFO("PSP loading VCN firmware\n");
+   }
+
 r = amdgpu_vcn_resume(adev);
 if (r)
 return r;
@@ -265,26 +275,38 @@ static int vcn_v1_0_resume(void *handle)
 static void vcn_v1_0_mc_resume(struct amdgpu_device *adev)
 {
 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
-
-   WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
+   uint32_t offset;
+
+   if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+   WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
+   
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
+   WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
+   
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));
+   WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
+   offset = 0;
+   } else {
+   WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 lower_32_bits(adev->vcn.gpu_addr));
-   WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
+   WREG32_SOC15(UVD, 0, m

[PATCH v2 5/5] drm/amdgpu:add VCN booting with firmware loaded by PSP

2018-08-09 Thread James Zhu 
From: Likun Gao 

Setup psp firmware loading for VCN, and make VCN block
booting from tmr mac address.

Signed-off-by: James Zhu 
Reviewed-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 17 +--
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c   | 38 ++---
 2 files changed, 40 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 878f62c..77c192a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -111,9 +111,10 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
version_major, version_minor, family_id);
}
 
-   bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8)
- +  AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_HEAP_SIZE
+   bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_HEAP_SIZE
  +  AMDGPU_VCN_SESSION_SIZE * 40;
+   if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
+   bo_size += 
AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM, >vcn.vcpu_bo,
>vcn.gpu_addr, >vcn.cpu_addr);
@@ -189,11 +190,13 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev)
unsigned offset;
 
hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
-   offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
-   memcpy_toio(adev->vcn.cpu_addr, adev->vcn.fw->data + offset,
-   le32_to_cpu(hdr->ucode_size_bytes));
-   size -= le32_to_cpu(hdr->ucode_size_bytes);
-   ptr += le32_to_cpu(hdr->ucode_size_bytes);
+   if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
+   offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
+   memcpy_toio(adev->vcn.cpu_addr, adev->vcn.fw->data + 
offset,
+   le32_to_cpu(hdr->ucode_size_bytes));
+   size -= le32_to_cpu(hdr->ucode_size_bytes);
+   ptr += le32_to_cpu(hdr->ucode_size_bytes);
+   }
memset_io(ptr, 0, size);
}
 
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 2ce91a7..74c4ef4 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -100,6 +100,16 @@ static int vcn_v1_0_sw_init(void *handle)
if (r)
return r;
 
+   if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+   const struct common_firmware_header *hdr;
+   hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
+   adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = 
AMDGPU_UCODE_ID_VCN;
+   adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
+   adev->firmware.fw_size +=
+   ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
+   DRM_INFO("PSP loading VCN firmware\n");
+   }
+
r = amdgpu_vcn_resume(adev);
if (r)
return r;
@@ -265,26 +275,38 @@ static int vcn_v1_0_resume(void *handle)
 static void vcn_v1_0_mc_resume(struct amdgpu_device *adev)
 {
uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
-
-   WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
+   uint32_t offset;
+
+   if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+   WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
+   
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
+   WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
+   
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));
+   WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
+   offset = 0;
+   } else {
+   WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
lower_32_bits(adev->vcn.gpu_addr));
-   WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
+   WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
upper_32_bits(adev->vcn.gpu_addr));
-   WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
+   offset = size;
+   WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
+   }
+
WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
 
WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
-   lower_32_bits(adev->vcn.gpu_addr + size));
+   lower_32_bits(adev->vcn.gpu_addr + offset));
WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
-