RE: [PATCH] drm/amd/pm: update driver if file for sienna cichlid

2020-11-16 Thread Zhang, Hawking 
[AMD Public Use]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Gao, Likun  
Sent: Monday, November 16, 2020 15:35
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Feng, Kenneth 
; Gao, Likun 
Subject: [PATCH] drm/amd/pm: update driver if file for sienna cichlid

From: Likun Gao 

Update driver if file for sienna cichlid.

Signed-off-by: Likun Gao 
Change-Id: Ibcffb2a668202f941b1e8e7a22924976c910cf35
---
 .../pm/inc/smu11_driver_if_sienna_cichlid.h   | 16 +-
 drivers/gpu/drm/amd/pm/inc/smu_v11_0.h|  2 +-
 .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c   | 22 ---
 3 files changed, 12 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h 
b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h
index e418a46603c8..fa95147b5a63 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h
@@ -27,9 +27,9 @@
 // *** IMPORTANT ***
 // SMU TEAM: Always increment the interface version if  // any structure is 
changed in this file -#define SMU11_DRIVER_IF_VERSION 0x3A
+#define SMU11_DRIVER_IF_VERSION 0x3B
 
-#define PPTABLE_Sienna_Cichlid_SMU_VERSION 6
+#define PPTABLE_Sienna_Cichlid_SMU_VERSION 7
 
 #define NUM_GFXCLK_DPM_LEVELS  16
 #define NUM_SMNCLK_DPM_LEVELS  2
@@ -437,6 +437,7 @@ typedef enum {
   PIECEWISE_LINEAR_FUSED_MODEL = 0,
   PIECEWISE_LINEAR_PP_MODEL,
   QUADRATIC_PP_MODEL,
+  PERPART_PIECEWISE_LINEAR_PP_MODEL,
 } DfllDroopModelSelect_e;
 
 typedef struct {
@@ -612,7 +613,9 @@ typedef struct {
   uint16_t   SmnclkDpmFreq[NUM_SMNCLK_DPM_LEVELS];   // in MHz
   uint16_t   SmnclkDpmVoltage [NUM_SMNCLK_DPM_LEVELS];   // mV(Q2)
 
-  uint32_t PaddingAPCC[4];
+  uint32_t   PaddingAPCC;
+  uint16_t   
PerPartDroopVsetGfxDfll[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS];  //In 
mV(Q2)
+  uint16_t   PaddingPerPartDroop;
 
   // SECTION: Throttler settings
   uint32_t ThrottlerControlMask;   // See Throtter masks defines
@@ -667,7 +670,9 @@ typedef struct {
   uint16_t   FreqTablePhyclk   [NUM_PHYCLK_DPM_LEVELS  ]; // In MHz
   uint16_t   FreqTableDtbclk   [NUM_DTBCLK_DPM_LEVELS  ]; // In MHz
   uint16_t   FreqTableFclk [NUM_FCLK_DPM_LEVELS]; // In MHz
-  uint32_t   Paddingclks[16];
+  uint32_t   Paddingclks;
+
+  DroopInt_t 
PerPartDroopModelGfxDfll[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //GHz 
->Vstore in IEEE float format
 
   uint32_t   DcModeMaxFreq [PPCLK_COUNT]; // In MHz
   
@@ -1221,7 +1226,8 @@ typedef struct {
 #define WORKLOAD_PPLIB_VR_BIT 4 
 #define WORKLOAD_PPLIB_COMPUTE_BIT5 
 #define WORKLOAD_PPLIB_CUSTOM_BIT 6 
-#define WORKLOAD_PPLIB_COUNT  7 
+#define WORKLOAD_PPLIB_W3D_BIT7 
+#define WORKLOAD_PPLIB_COUNT  8 
 
 
 // These defines are used with the following messages:
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h 
b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
index 41bc919dc9f4..eff396c7a281 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
@@ -30,7 +30,7 @@
 #define SMU11_DRIVER_IF_VERSION_NV10 0x36
 #define SMU11_DRIVER_IF_VERSION_NV12 0x36
 #define SMU11_DRIVER_IF_VERSION_NV14 0x36
-#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x3A
+#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x3B
 #define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x5
 #define SMU11_DRIVER_IF_VERSION_VANGOGH 0x02
 #define SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish 0xD
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 0600befc6e4c..21c5ea3a4a63 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -1805,11 +1805,6 @@ static void sienna_cichlid_dump_pptable(struct 
smu_context *smu)
dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, 
pptable->SmnclkDpmFreq[i]);
dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, 
pptable->SmnclkDpmVoltage[i]);
}
-   dev_info(smu->adev->dev, "PaddingAPCC[0] = 0x%x\n", 
pptable->PaddingAPCC[0]);
-   dev_info(smu->adev->dev, "PaddingAPCC[1] = 0x%x\n", 
pptable->PaddingAPCC[1]);
-   dev_info(smu->adev->dev, "PaddingAPCC[2] = 0x%x\n", 
pptable->PaddingAPCC[2]);
-   dev_info(smu->adev->dev, "PaddingAPCC[3] = 0x%x\n", 
pptable->PaddingAPCC[3]);
-
dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", 
pptable->ThrottlerControlMask);
 
dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", 
pptable->FwDStateMask);
@@ -2036,23 +2031,6 @@ static void sienna_cichlid_dump_pptable(struct 
smu_context *smu)
for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i,

RE: [PATCH] drm/amd/pm: update driver if file for sienna cichlid

2020-11-16 Thread Feng, Kenneth 
[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Kenneth Feng 


Best Regards
Kenneth

-Original Message-
From: Gao, Likun  
Sent: Monday, November 16, 2020 3:35 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Feng, Kenneth 
; Gao, Likun 
Subject: [PATCH] drm/amd/pm: update driver if file for sienna cichlid

From: Likun Gao 

Update driver if file for sienna cichlid.

Signed-off-by: Likun Gao 
Change-Id: Ibcffb2a668202f941b1e8e7a22924976c910cf35
---
 .../pm/inc/smu11_driver_if_sienna_cichlid.h   | 16 +-
 drivers/gpu/drm/amd/pm/inc/smu_v11_0.h|  2 +-
 .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c   | 22 ---
 3 files changed, 12 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h 
b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h
index e418a46603c8..fa95147b5a63 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h
@@ -27,9 +27,9 @@
 // *** IMPORTANT ***
 // SMU TEAM: Always increment the interface version if  // any structure is 
changed in this file -#define SMU11_DRIVER_IF_VERSION 0x3A
+#define SMU11_DRIVER_IF_VERSION 0x3B
 
-#define PPTABLE_Sienna_Cichlid_SMU_VERSION 6
+#define PPTABLE_Sienna_Cichlid_SMU_VERSION 7
 
 #define NUM_GFXCLK_DPM_LEVELS  16
 #define NUM_SMNCLK_DPM_LEVELS  2
@@ -437,6 +437,7 @@ typedef enum {
   PIECEWISE_LINEAR_FUSED_MODEL = 0,
   PIECEWISE_LINEAR_PP_MODEL,
   QUADRATIC_PP_MODEL,
+  PERPART_PIECEWISE_LINEAR_PP_MODEL,
 } DfllDroopModelSelect_e;
 
 typedef struct {
@@ -612,7 +613,9 @@ typedef struct {
   uint16_t   SmnclkDpmFreq[NUM_SMNCLK_DPM_LEVELS];   // in MHz
   uint16_t   SmnclkDpmVoltage [NUM_SMNCLK_DPM_LEVELS];   // mV(Q2)
 
-  uint32_t PaddingAPCC[4];
+  uint32_t   PaddingAPCC;
+  uint16_t   
PerPartDroopVsetGfxDfll[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS];  //In 
mV(Q2)
+  uint16_t   PaddingPerPartDroop;
 
   // SECTION: Throttler settings
   uint32_t ThrottlerControlMask;   // See Throtter masks defines
@@ -667,7 +670,9 @@ typedef struct {
   uint16_t   FreqTablePhyclk   [NUM_PHYCLK_DPM_LEVELS  ]; // In MHz
   uint16_t   FreqTableDtbclk   [NUM_DTBCLK_DPM_LEVELS  ]; // In MHz
   uint16_t   FreqTableFclk [NUM_FCLK_DPM_LEVELS]; // In MHz
-  uint32_t   Paddingclks[16];
+  uint32_t   Paddingclks;
+
+  DroopInt_t 
PerPartDroopModelGfxDfll[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //GHz 
->Vstore in IEEE float format
 
   uint32_t   DcModeMaxFreq [PPCLK_COUNT]; // In MHz
   
@@ -1221,7 +1226,8 @@ typedef struct {
 #define WORKLOAD_PPLIB_VR_BIT 4 
 #define WORKLOAD_PPLIB_COMPUTE_BIT5 
 #define WORKLOAD_PPLIB_CUSTOM_BIT 6 
-#define WORKLOAD_PPLIB_COUNT  7 
+#define WORKLOAD_PPLIB_W3D_BIT7 
+#define WORKLOAD_PPLIB_COUNT  8 
 
 
 // These defines are used with the following messages:
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h 
b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
index 41bc919dc9f4..eff396c7a281 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
@@ -30,7 +30,7 @@
 #define SMU11_DRIVER_IF_VERSION_NV10 0x36
 #define SMU11_DRIVER_IF_VERSION_NV12 0x36
 #define SMU11_DRIVER_IF_VERSION_NV14 0x36
-#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x3A
+#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x3B
 #define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x5
 #define SMU11_DRIVER_IF_VERSION_VANGOGH 0x02
 #define SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish 0xD
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 0600befc6e4c..21c5ea3a4a63 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -1805,11 +1805,6 @@ static void sienna_cichlid_dump_pptable(struct 
smu_context *smu)
dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, 
pptable->SmnclkDpmFreq[i]);
dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, 
pptable->SmnclkDpmVoltage[i]);
}
-   dev_info(smu->adev->dev, "PaddingAPCC[0] = 0x%x\n", 
pptable->PaddingAPCC[0]);
-   dev_info(smu->adev->dev, "PaddingAPCC[1] = 0x%x\n", 
pptable->PaddingAPCC[1]);
-   dev_info(smu->adev->dev, "PaddingAPCC[2] = 0x%x\n", 
pptable->PaddingAPCC[2]);
-   dev_info(smu->adev->dev, "PaddingAPCC[3] = 0x%x\n", 
pptable->PaddingAPCC[3]);
-
dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", 
pptable->ThrottlerControlMask);
 
dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", 
pptable->FwDStateMask);
@@ -2036,23 +2031,6 @@ static void sienna_cichlid_dump_pptable(struct 
smu_context *smu)
for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)

RE: [PATCH] drm/amd/pm: update driver if file for sienna cichlid

2020-10-20 Thread Zhang, Hawking 
[AMD Public Use]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Gao, Likun  
Sent: Tuesday, October 20, 2020 16:57
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Feng, Kenneth 
; Gao, Likun 
Subject: [PATCH] drm/amd/pm: update driver if file for sienna cichlid

From: Likun Gao 

Update driver if file for sienna cichlid.

Signed-off-by: Likun Gao 
Change-Id: Ie386abcd0a00fd904155361c9aa8c0861473552a
---
 .../amd/pm/inc/smu11_driver_if_sienna_cichlid.h| 14 --
 drivers/gpu/drm/amd/pm/inc/smu_v11_0.h |  2 +-
 2 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h 
b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h
index 1275246769d9..e418a46603c8 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h
@@ -27,7 +27,7 @@
 // *** IMPORTANT ***
 // SMU TEAM: Always increment the interface version if  // any structure is 
changed in this file -#define SMU11_DRIVER_IF_VERSION 0x39
+#define SMU11_DRIVER_IF_VERSION 0x3A
 
 #define PPTABLE_Sienna_Cichlid_SMU_VERSION 6
 
@@ -226,6 +226,8 @@ typedef enum {
 #define FW_DSTATE_MEM_PLL_PWRDN_BIT 9   
 #define FW_DSTATE_OPTIMIZE_MALL_REFRESH_BIT 10
 #define FW_DSTATE_MEM_PSI_BIT   11
+#define FW_DSTATE_HSR_NON_STROBE_BIT12
+#define FW_DSTATE_MP0_ENTER_WFI_BIT 13
 
 #define FW_DSTATE_SOC_ULV_MASK(1 << FW_DSTATE_SOC_ULV_BIT  
)
 #define FW_DSTATE_G6_HSR_MASK (1 << FW_DSTATE_G6_HSR_BIT   
)
@@ -239,6 +241,8 @@ typedef enum {
 #define FW_DSTATE_MEM_PLL_PWRDN_MASK  (1 << 
FW_DSTATE_MEM_PLL_PWRDN_BIT)
 #define FW_DSTATE_OPTIMIZE_MALL_REFRESH_MASK  (1 << 
FW_DSTATE_OPTIMIZE_MALL_REFRESH_BIT)
 #define FW_DSTATE_MEM_PSI_MASK(1 << FW_DSTATE_MEM_PSI_BIT  
  )
+#define FW_DSTATE_HSR_NON_STROBE_MASK (1 << 
FW_DSTATE_HSR_NON_STROBE_BIT)
+#define FW_DSTATE_MP0_ENTER_WFI_MASK  (1 << 
FW_DSTATE_MP0_ENTER_WFI_BIT)
 
 // GFX GPO Feature Contains PACE and DEM sub features
 #define GFX_GPO_PACE_BIT   0
@@ -804,7 +808,11 @@ typedef struct {
   uint32_t VcBtcVminA;  // A_VMIN
   uint32_t VcBtcVminB;  // B_VMIN  
   
-  uint32_t SkuReserved[9];
+  //GPIO Board feature
+  uint16_t LedGpio;//GeneriA GPIO flag used to control the 
radeon LEDs
+  uint16_t GfxPowerStagesGpio; //Genlk_vsync GPIO flag used to control 
gfx power stages 
+  
+  uint32_t SkuReserved[8];
 
 
   // MAJOR SECTION: BOARD PARAMETERS
@@ -1026,6 +1034,8 @@ typedef struct {
   uint16_t VcnActivityPercentage  ; //place holder, David N. to provide full 
sequence
   uint8_t  PcieRate   ;
   uint8_t  PcieWidth  ;
+  uint16_t AverageGfxclkFrequencyTarget;  uint16_t Padding16_2;
 
 } SmuMetrics_t;
 
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h 
b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
index 75697b78c13f..820b9d34c997 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
@@ -30,7 +30,7 @@
 #define SMU11_DRIVER_IF_VERSION_NV10 0x36  #define 
SMU11_DRIVER_IF_VERSION_NV12 0x36  #define SMU11_DRIVER_IF_VERSION_NV14 0x36 
-#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x39
+#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x3A
 #define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x4
 
 /* MP Apertures */
--
2.25.1
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RE: [PATCH] drm/amd/pm: update driver if file for sienna cichlid

2020-09-21 Thread Chen, Jiansong (Simon) 
[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Jiansong Chen 

-Original Message-
From: amd-gfx  On Behalf Of Likun Gao
Sent: Tuesday, September 22, 2020 11:17 AM
To: amd-gfx@lists.freedesktop.org
Cc: Gao, Likun ; Feng, Kenneth ; 
Zhang, Hawking 
Subject: [PATCH] drm/amd/pm: update driver if file for sienna cichlid

From: Likun Gao 

Update driver if file for sienna cichlid.

Signed-off-by: Likun Gao 
Change-Id: I295edda90d156c4cea742e62fab696afb6cd1366
---
 drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h | 4 ++--
 drivers/gpu/drm/amd/pm/inc/smu_v11_0.h  | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h 
b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h
index 11a6cf96fe0c..1275246769d9 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h
@@ -27,7 +27,7 @@
 // *** IMPORTANT ***
 // SMU TEAM: Always increment the interface version if  // any structure is 
changed in this file -#define SMU11_DRIVER_IF_VERSION 0x37
+#define SMU11_DRIVER_IF_VERSION 0x39

 #define PPTABLE_Sienna_Cichlid_SMU_VERSION 6

@@ -962,7 +962,7 @@ typedef struct {
   uint8_tFanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS];
   uint8_tFanLinearTempPoints[NUM_OD_FAN_MAX_POINTS];
   uint16_t   MaxOpTemp;// Degree Celcius
-  uint16_t   Padding_16[1];
+  int16_tVddGfxOffset; // in mV
   uint8_tFanZeroRpmEnable;
   uint8_tFanZeroRpmStopTemp;
   uint8_tFanMode;
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h 
b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
index 7ae83df83edb..03198d214bba 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
@@ -30,7 +30,7 @@
 #define SMU11_DRIVER_IF_VERSION_NV10 0x36  #define 
SMU11_DRIVER_IF_VERSION_NV12 0x36  #define SMU11_DRIVER_IF_VERSION_NV14 0x36 
-#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x37
+#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x39
 #define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x5

 /* MP Apertures */
--
2.25.1

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RE: [PATCH] drm/amd/pm: update driver if file for sienna cichlid

2020-09-10 Thread Chen, Jiansong (Simon) 
[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Jiansong Chen 

-Original Message-
From: Gao, Likun 
Sent: Thursday, September 10, 2020 4:27 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Feng, Kenneth 
; Chen, Jiansong (Simon) ; Gao, 
Likun 
Subject: [PATCH] drm/amd/pm: update driver if file for sienna cichlid

From: Likun Gao 

Update drive if file for sienna_cichlid.

Signed-off-by: Likun Gao 
Change-Id: I53e5210acb760901622cd50aaf81193e9699feba
---
 .../pm/inc/smu11_driver_if_sienna_cichlid.h   | 20 ++-
 drivers/gpu/drm/amd/pm/inc/smu_v11_0.h|  2 +-
 .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c   |  5 -
 3 files changed, 16 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h 
b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h
index 5ef9c92f57c4..11a6cf96fe0c 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h
@@ -27,9 +27,9 @@
 // *** IMPORTANT ***
 // SMU TEAM: Always increment the interface version if  // any structure is 
changed in this file -#define SMU11_DRIVER_IF_VERSION 0x35
+#define SMU11_DRIVER_IF_VERSION 0x37

-#define PPTABLE_Sienna_Cichlid_SMU_VERSION 5
+#define PPTABLE_Sienna_Cichlid_SMU_VERSION 6

 #define NUM_GFXCLK_DPM_LEVELS  16
 #define NUM_SMNCLK_DPM_LEVELS  2
@@ -169,7 +169,7 @@ typedef enum {
 #define DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN   0x0200
 #define DPM_OVERRIDE_DISABLE_MEMORY_TEMPERATURE_READ 0x0400
 #define DPM_OVERRIDE_DISABLE_VOLT_LINK_VCN_DCEFCLK   0x0800
-#define DPM_OVERRIDE_ENABLE_FAST_FCLK_TIMER  0x1000
+#define DPM_OVERRIDE_DISABLE_FAST_FCLK_TIMER 0x1000
 #define DPM_OVERRIDE_DISABLE_VCN_PG  0x2000
 #define DPM_OVERRIDE_DISABLE_FMAX_VMAX   0x4000

@@ -793,8 +793,18 @@ typedef struct {

   // SECTION: Sku Reserved
   uint8_t  CustomerVariant;
-  uint8_t  Spare[3];
-  uint32_t SkuReserved[14];
+
+  //VC BTC parameters are only applicable to VDD_GFX domain
+  uint8_t  VcBtcEnabled;
+  uint16_t VcBtcVminT0; // T0_VMIN
+  uint16_t VcBtcFixedVminAgingOffset;   // FIXED_VMIN_AGING_OFFSET
+  uint16_t VcBtcVmin2PsmDegrationGb;// VMIN_TO_PSM_DEGRADATION_GB
+  uint32_t VcBtcPsmA;   // A_PSM
+  uint32_t VcBtcPsmB;   // B_PSM
+  uint32_t VcBtcVminA;  // A_VMIN
+  uint32_t VcBtcVminB;  // B_VMIN
+
+  uint32_t SkuReserved[9];


   // MAJOR SECTION: BOARD PARAMETERS
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h 
b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
index 2a3f1ee4a50b..9dfc1c87b6dd 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
@@ -30,7 +30,7 @@
 #define SMU11_DRIVER_IF_VERSION_NV10 0x36  #define 
SMU11_DRIVER_IF_VERSION_NV12 0x36  #define SMU11_DRIVER_IF_VERSION_NV14 0x36 
-#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x35
+#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x37
 #define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x4

 /* MP Apertures */
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index b67931fd64b4..194abaca6948 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -2295,11 +2295,6 @@ static void sienna_cichlid_dump_pptable(struct 
smu_context *smu)
 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
 dev_info(smu->adev->dev, "SkuReserved[8] = 0x%x\n", pptable->SkuReserved[8]);
-dev_info(smu->adev->dev, "SkuReserved[9] = 0x%x\n", pptable->SkuReserved[9]);
-dev_info(smu->adev->dev, "SkuReserved[10] = 0x%x\n", pptable->SkuReserved[10]);
-dev_info(smu->adev->dev, "SkuReserved[11] = 0x%x\n", pptable->SkuReserved[11]);
-dev_info(smu->adev->dev, "SkuReserved[12] = 0x%x\n", pptable->SkuReserved[12]);
-dev_info(smu->adev->dev, "SkuReserved[13] = 0x%x\n", pptable->SkuReserved[13]);

 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
--
2.25.1

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