RE: [PATCH] drm/amd/swsmu: enable more Pstates profile levels for SMU v14.0.0 and v14.0.1
[AMD Official Use Only - AMD Internal Distribution Only]
Hi Tim,
> -Original Message-
> From: Huang, Tim
> Sent: Monday, July 1, 2024 5:34 PM
> To: Ma, Li ; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Zhang, Yifan
>
> Subject: RE: [PATCH] drm/amd/swsmu: enable more Pstates profile levels for
> SMU v14.0.0 and v14.0.1
>
> [AMD Official Use Only - AMD Internal Distribution Only]
>
> Hi Li,
>
> > -Original Message-
> > From: Ma, Li
> > Sent: Monday, July 1, 2024 4:23 PM
> > To: amd-gfx@lists.freedesktop.org
> > Cc: Deucher, Alexander ; Zhang, Yifan
> > ; Huang, Tim ; Ma, Li
> >
> > Subject: [PATCH] drm/amd/swsmu: enable more Pstates profile levels for
> SMU
> > v14.0.0 and v14.0.1
> >
> > This patch enables following UMD stable Pstates profile levels for
> > power_dpm_force_performance_level interface.
> >
> > - profile_peak
> > - profile_min_mclk
> > - profile_min_sclk
> > - profile_standard
> >
> > Signed-off-by: Li Ma
> > ---
> > .../drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c | 150
> > --
> > 1 file changed, 137 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> > b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> > index 18abfbd6d059..d999e3b23173 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> > @@ -65,6 +65,10 @@
> >
> > #define SMU_MALL_PG_CONFIG_DEFAULT
> > SMU_MALL_PG_CONFIG_DRIVER_CONTROL_ALWAYS_ON
> >
> > +#define SMU_14_0_0_UMD_PSTATE_GFXCLK 700
> > +#define SMU_14_0_0_UMD_PSTATE_SOCCLK 678
> > +#define SMU_14_0_0_UMD_PSTATE_FCLK 1800
> > +
> > #define FEATURE_MASK(feature) (1ULL << feature) #define
> > SMC_DPM_FEATURE ( \
> > FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ @@ -723,10 +727,10
> @@
> > static int smu_v14_0_common_get_dpm_freq_by_index(struct
> smu_context
> > *smu,
> > uint32_t dpm_level,
> > uint32_t *freq)
> > {
> > - if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0,
> > 0))
> > - smu_v14_0_0_get_dpm_freq_by_index(smu, clk_type, dpm_level,
> > freq);
> > - else if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) ==
> IP_VERSION(14,
> > 0, 1))
> > + if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0,
> > 1))
> > smu_v14_0_1_get_dpm_freq_by_index(smu, clk_type, dpm_level,
> > freq);
> > + else
> > + smu_v14_0_0_get_dpm_freq_by_index(smu, clk_type, dpm_level,
> > freq);
> >
> > return 0;
> > }
>
> Does this conflict with the ongoing commit drm/amd/pm: smu v14.0.4 reuse
> smu v14.0.0 dpmtable ?
>
> Tim
Li: Thanks for reminder, the change in smu_v14_0_common_get_dpm_freq_by_index
and smu_v14_0_common_get_dpm_ultimate_freq are same as ongoing commit
"drm/amd/pm: smu v14.0.4 reuse smu v14.0.0 dpmtable". I will remove this change
to avoid the repetition.
>
> > @@ -818,9 +822,11 @@ static int
> > smu_v14_0_1_get_dpm_ultimate_freq(struct smu_context *smu,
> > break;
> > case SMU_MCLK:
> > case SMU_UCLK:
> > - case SMU_FCLK:
> > max_dpm_level = 0;
> > break;
> > + case SMU_FCLK:
> > + max_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
> > + break;
> > case SMU_SOCCLK:
> > max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
> > break;
> > @@ -855,7 +861,7 @@ static int
> > smu_v14_0_1_get_dpm_ultimate_freq(struct smu_context *smu,
> > min_dpm_level = clk_table->NumMemPstatesEnabled - 1;
> > break;
> > case SMU_FCLK:
> > - min_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
> > + min_dpm_level = 0;
> > break;
> > case SMU_SOCCLK:
> > min_dpm_level = 0;
> > @@ -936,9 +942,11 @@ static int
> > smu_v14_0_0_get_dpm_ultimate_freq(struct smu_context *smu,
> > break;
> > case SMU_MCLK:
> > case SMU_
RE: [PATCH] drm/amd/swsmu: enable more Pstates profile levels for SMU v14.0.0 and v14.0.1
[AMD Official Use Only - AMD Internal Distribution Only]
Hi Li,
> -Original Message-
> From: Ma, Li
> Sent: Monday, July 1, 2024 4:23 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Zhang, Yifan
> ; Huang, Tim ; Ma, Li
>
> Subject: [PATCH] drm/amd/swsmu: enable more Pstates profile levels for SMU
> v14.0.0 and v14.0.1
>
> This patch enables following UMD stable Pstates profile levels for
> power_dpm_force_performance_level interface.
>
> - profile_peak
> - profile_min_mclk
> - profile_min_sclk
> - profile_standard
>
> Signed-off-by: Li Ma
> ---
> .../drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c | 150
> --
> 1 file changed, 137 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> index 18abfbd6d059..d999e3b23173 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> @@ -65,6 +65,10 @@
>
> #define SMU_MALL_PG_CONFIG_DEFAULT
> SMU_MALL_PG_CONFIG_DRIVER_CONTROL_ALWAYS_ON
>
> +#define SMU_14_0_0_UMD_PSTATE_GFXCLK 700
> +#define SMU_14_0_0_UMD_PSTATE_SOCCLK 678
> +#define SMU_14_0_0_UMD_PSTATE_FCLK 1800
> +
> #define FEATURE_MASK(feature) (1ULL << feature) #define
> SMC_DPM_FEATURE ( \
> FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ @@ -723,10 +727,10 @@
> static int smu_v14_0_common_get_dpm_freq_by_index(struct smu_context
> *smu,
> uint32_t dpm_level,
> uint32_t *freq)
> {
> - if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0,
> 0))
> - smu_v14_0_0_get_dpm_freq_by_index(smu, clk_type, dpm_level,
> freq);
> - else if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14,
> 0, 1))
> + if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0,
> 1))
> smu_v14_0_1_get_dpm_freq_by_index(smu, clk_type, dpm_level,
> freq);
> + else
> + smu_v14_0_0_get_dpm_freq_by_index(smu, clk_type, dpm_level,
> freq);
>
> return 0;
> }
Does this conflict with the ongoing commit drm/amd/pm: smu v14.0.4 reuse smu
v14.0.0 dpmtable ?
Tim
> @@ -818,9 +822,11 @@ static int
> smu_v14_0_1_get_dpm_ultimate_freq(struct smu_context *smu,
> break;
> case SMU_MCLK:
> case SMU_UCLK:
> - case SMU_FCLK:
> max_dpm_level = 0;
> break;
> + case SMU_FCLK:
> + max_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
> + break;
> case SMU_SOCCLK:
> max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
> break;
> @@ -855,7 +861,7 @@ static int
> smu_v14_0_1_get_dpm_ultimate_freq(struct smu_context *smu,
> min_dpm_level = clk_table->NumMemPstatesEnabled - 1;
> break;
> case SMU_FCLK:
> - min_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
> + min_dpm_level = 0;
> break;
> case SMU_SOCCLK:
> min_dpm_level = 0;
> @@ -936,9 +942,11 @@ static int
> smu_v14_0_0_get_dpm_ultimate_freq(struct smu_context *smu,
> break;
> case SMU_MCLK:
> case SMU_UCLK:
> - case SMU_FCLK:
> max_dpm_level = 0;
> break;
> + case SMU_FCLK:
> + max_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
> + break;
> case SMU_SOCCLK:
> max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
> break;
> @@ -969,7 +977,7 @@ static int
> smu_v14_0_0_get_dpm_ultimate_freq(struct smu_context *smu,
> min_dpm_level = clk_table->NumMemPstatesEnabled - 1;
> break;
> case SMU_FCLK:
> - min_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
> + min_dpm_level = 0;
> break;
> case SMU_SOCCLK:
> min_dpm_level = 0;
> @@ -999,10 +1007,10 @@ static int
> smu_v14_0_common_get_dpm_ultimate_freq(struct smu_context *smu,
> uint32_t *min,
> uint32_t *max)
> {
> - if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0,
> 0))
> - smu_v14_0_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
> - else if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14,
> 0, 1))
> + if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0,
> 1))
>
