Re: [PATCH 2/2] drm/amdgpu/gfx10: update gfx golden settings for navi14
[AMD Official Use Only - Internal Distribution Only] Thanks Alex! From: Alex Deucher Sent: Wednesday, January 15, 2020 1:39 To: Yin, Tianci (Rico) Cc: amd-gfx list ; Xu, Feifei ; Zhang, Hawking Subject: Re: [PATCH 2/2] drm/amdgpu/gfx10: update gfx golden settings for navi14 On Tue, Jan 14, 2020 at 6:42 AM Tianci Yin wrote: > > From: "Tianci.Yin" > > remove registers: mmSPI_CONFIG_CNTL > add registers: mmSPI_CONFIG_CNTL_1 > > Change-Id: I0bbaeca184e7dc85463d6c5740151d6ba1b08c06 > Signed-off-by: Tianci.Yin Series is: Reviewed-by: Alex Deucher > --- > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > index 4f6ffaf3f9be..3c9082b1eea9 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > @@ -169,7 +169,7 @@ static const struct soc15_reg_golden > golden_settings_gc_10_1_1[] = > SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x0800, > 0x0820), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0xff0f, > 0x), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0x, 0x3101), > - SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL, 0x001f, > 0x00070105), > + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f, > 0x00070105), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0x, > 0x), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x0133, > 0x0130), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0x, > 0x), > -- > 2.17.1 > > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Ctianci.yin%40amd.com%7Cced760baf9c0451c0e6708d79918b31c%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637146203676595018&sdata=FJMr7sM3nIICn2hPyZCX851E4%2BCQxvY4U2pD6Rga6X4%3D&reserved=0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 2/2] drm/amdgpu/gfx10: update gfx golden settings for navi14
On Tue, Jan 14, 2020 at 6:42 AM Tianci Yin wrote: > > From: "Tianci.Yin" > > remove registers: mmSPI_CONFIG_CNTL > add registers: mmSPI_CONFIG_CNTL_1 > > Change-Id: I0bbaeca184e7dc85463d6c5740151d6ba1b08c06 > Signed-off-by: Tianci.Yin Series is: Reviewed-by: Alex Deucher > --- > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > index 4f6ffaf3f9be..3c9082b1eea9 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > @@ -169,7 +169,7 @@ static const struct soc15_reg_golden > golden_settings_gc_10_1_1[] = > SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x0800, > 0x0820), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0xff0f, > 0x), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0x, 0x3101), > - SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL, 0x001f, > 0x00070105), > + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f, > 0x00070105), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0x, > 0x), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x0133, > 0x0130), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0x, > 0x), > -- > 2.17.1 > > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH 2/2] drm/amdgpu/gfx10: update gfx golden settings for navi14
Series is Reviewed-by: Feifei Xu -Original Message- From: Tianci Yin Sent: Wednesday, December 11, 2019 8:00 PM To: amd-gfx@lists.freedesktop.org Cc: Zhang, Hawking ; Xu, Feifei ; Yuan, Xiaojie ; Long, Gang ; Li, Pauline ; Yin, Tianci (Rico) Subject: [PATCH 2/2] drm/amdgpu/gfx10: update gfx golden settings for navi14 From: "Tianci.Yin" add registers: mmPA_SC_BINNER_TIMEOUT_COUNTER and mmPA_SC_ENHANCE_2 Change-Id: I1fc3fb481b2d9edc482a32497242a8be6cd6b8d7 Signed-off-by: Tianci.Yin --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index e5637a6efb05..8cdef79de9d4 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -162,8 +162,10 @@ static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x0fff, 0x1100), SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0x, 0x1402002f), SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xbfff, 0x0188), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0x, 0x0800), SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fff, 0x0809), SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x0040, 0x0444), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x0800, 0x0820), SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0xff0f, 0x), SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0x, 0x3101), SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL, 0x001f, 0x00070105), -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 2/2] drm/amdgpu/gfx10: update gfx golden settings for navi14
Series is: Reviewed-by: Alex Deucher From: amd-gfx on behalf of Tianci Yin Sent: Wednesday, September 18, 2019 6:30 AM To: amd-gfx@lists.freedesktop.org Cc: Yin, Tianci (Rico) ; Zhang, Hawking Subject: [PATCH 2/2] drm/amdgpu/gfx10: update gfx golden settings for navi14 From: "Tianci.Yin" update registers: mmUTCL1_CTRL Change-Id: I6df12555b72ba6faa926af8155b3f079e422a500 Signed-off-by: Tianci.Yin --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 7901530d07f0..121824b47d02 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -161,7 +161,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0x, 0x), SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7, 0x0103), SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x6010, 0x479c0010), - SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x0080, 0x0080), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c0, 0x00c0), }; static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
