subject:"RE\: \[PATCH 2\/3\] drm\/amd\/powerplay\: force sclk limit for peak profile"

RE: [PATCH 2/3] drm/amd/powerplay: force sclk limit for peak profile

2019-07-18 Thread Gui, Jack

Hi Evan,
1, The hack hard code was just served for profile_peak mode and (max_count - 1) 
level always used for GFX clock, we just force the limit value with data from 
tool team.
2, The requirement from tool team is to force GFX clock limit value with 
different SKU’s clocks when enter profile peak mode, so the hack code was added 
when  clock adjust rules was applied.

From: Quan, Evan 
Sent: Thursday, July 18, 2019 6:32 PM
To: Gui, Jack ; amd-gfx@lists.freedesktop.org
Cc: Gui, Jack 
Subject: Re: [PATCH 2/3] drm/amd/powerplay: force sclk limit for peak profile

1. In navi10_force_clk_levels, i think you need to compare the max level user 
requested with the peak limit and set the smaller one.
2. can you help me to understand why the change in apply_clock_rules is needed?


发件人: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 代表 Chengming Gui mailto:jack@amd.com>>
发送时间: Thursday, July 18, 2019 6:02:17 PM
收件人: amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org> 
mailto:amd-gfx@lists.freedesktop.org>>
抄送: Gui, Jack mailto:jack@amd.com>>
主题: [PATCH 2/3] drm/amd/powerplay: force sclk limit for peak profile

force different GFX clocks with different SKUs for navi10:
XL  (other rev_id):  1625MHz
XT (F1/C1):  1755MHz
XTX(F0/C0):  1830MHz

Signed-off-by: Chengming Gui mailto:jack@amd.com>>
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c |  2 +
 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h |  2 +
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 66 +-
 3 files changed, 68 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 122985c..693414f 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -664,6 +664,8 @@ static int smu_sw_init(void *handle)
 smu->watermarks_bitmap = 0;
 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
+   smu->smu_dpm.default_sclk_limit = 0;
+   smu->smu_dpm.peak_sclk_limit = 0;

 smu->workload_mask = 1 << 
smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 135a323..acb522b 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -441,6 +441,8 @@ struct smu_dpm_context {
 void *dpm_context;
 void *golden_dpm_context;
 bool enable_umd_pstate;
+   uint32_t default_sclk_limit;
+   uint32_t peak_sclk_limit;
 enum amd_dpm_forced_level dpm_level;
 enum amd_dpm_forced_level saved_dpm_level;
 enum amd_dpm_forced_level requested_dpm_level;
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 895a4e5..b4deb9e 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -37,6 +37,15 @@

 #include "asic_reg/mp/mp_11_0_sh_mask.h"

+#define NV_NV10_F0 0xF0
+#define NV_NV10_C0 0xC0
+#define NV_NV10_F1 0xF1
+#define NV_NV10_C1 0xC1
+
+#define NV_NV10_PEAK_SCLK_XTX 1830
+#define NV_NV10_PEAK_SCLK_XT  1755
+#define NV_NV10_PEAK_SCLK_XL  1625
+
 #define FEATURE_MASK(feature) (1ULL << feature)
 #define SMC_DPM_FEATURE ( \
 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
@@ -675,6 +684,7 @@ static int navi10_force_clk_levels(struct smu_context *smu,

 int ret = 0, size = 0;
 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, 
max_freq = 0;
+   struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);

 soft_min_level = mask ? (ffs(mask) - 1) : 0;
 soft_max_level = mask ? (fls(mask) - 1) : 0;
@@ -682,6 +692,23 @@ static int navi10_force_clk_levels(struct smu_context *smu,
 switch (clk_type) {
 case SMU_GFXCLK:
 case SMU_SCLK:
+   if (smu_dpm_ctx->peak_sclk_limit) {
+   max_freq = smu_dpm_ctx->peak_sclk_limit;
+   ret = smu_get_dpm_freq_by_index(smu, clk_type, 
soft_min_level, _freq);
+   if (ret)
+   return size;
+   } else {
+   ret = smu_get_dpm_freq_by_index(smu, clk_type, 
soft_min_level, _freq);
+   if (ret)
+   return size;
+   ret = smu_get_dpm_freq_by_index(smu, clk_type, 
soft_max_level, _freq);
+   if (ret)
+   return size;
+   }
+   ret = smu_set_soft_freq_range(smu, clk_type, min_freq,

Re: [PATCH 2/3] drm/amd/powerplay: force sclk limit for peak profile

2019-07-18 Thread Quan, Evan

1. In navi10_force_clk_levels, i think you need to compare the max level user 
requested with the peak limit and set the smaller one.
2. can you help me to understand why the change in apply_clock_rules is needed?


发件人: amd-gfx  代表 Chengming Gui 

发送时间: Thursday, July 18, 2019 6:02:17 PM
收件人: amd-gfx@lists.freedesktop.org 
抄送: Gui, Jack 
主题: [PATCH 2/3] drm/amd/powerplay: force sclk limit for peak profile

force different GFX clocks with different SKUs for navi10:
XL  (other rev_id):  1625MHz
XT (F1/C1):  1755MHz
XTX(F0/C0):  1830MHz

Signed-off-by: Chengming Gui 
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c |  2 +
 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h |  2 +
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 66 +-
 3 files changed, 68 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 122985c..693414f 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -664,6 +664,8 @@ static int smu_sw_init(void *handle)
 smu->watermarks_bitmap = 0;
 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
+   smu->smu_dpm.default_sclk_limit = 0;
+   smu->smu_dpm.peak_sclk_limit = 0;

 smu->workload_mask = 1 << 
smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 135a323..acb522b 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -441,6 +441,8 @@ struct smu_dpm_context {
 void *dpm_context;
 void *golden_dpm_context;
 bool enable_umd_pstate;
+   uint32_t default_sclk_limit;
+   uint32_t peak_sclk_limit;
 enum amd_dpm_forced_level dpm_level;
 enum amd_dpm_forced_level saved_dpm_level;
 enum amd_dpm_forced_level requested_dpm_level;
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 895a4e5..b4deb9e 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -37,6 +37,15 @@

 #include "asic_reg/mp/mp_11_0_sh_mask.h"

+#define NV_NV10_F0 0xF0
+#define NV_NV10_C0 0xC0
+#define NV_NV10_F1 0xF1
+#define NV_NV10_C1 0xC1
+
+#define NV_NV10_PEAK_SCLK_XTX 1830
+#define NV_NV10_PEAK_SCLK_XT  1755
+#define NV_NV10_PEAK_SCLK_XL  1625
+
 #define FEATURE_MASK(feature) (1ULL << feature)
 #define SMC_DPM_FEATURE ( \
 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
@@ -675,6 +684,7 @@ static int navi10_force_clk_levels(struct smu_context *smu,

 int ret = 0, size = 0;
 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, 
max_freq = 0;
+   struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);

 soft_min_level = mask ? (ffs(mask) - 1) : 0;
 soft_max_level = mask ? (fls(mask) - 1) : 0;
@@ -682,6 +692,23 @@ static int navi10_force_clk_levels(struct smu_context *smu,
 switch (clk_type) {
 case SMU_GFXCLK:
 case SMU_SCLK:
+   if (smu_dpm_ctx->peak_sclk_limit) {
+   max_freq = smu_dpm_ctx->peak_sclk_limit;
+   ret = smu_get_dpm_freq_by_index(smu, clk_type, 
soft_min_level, _freq);
+   if (ret)
+   return size;
+   } else {
+   ret = smu_get_dpm_freq_by_index(smu, clk_type, 
soft_min_level, _freq);
+   if (ret)
+   return size;
+   ret = smu_get_dpm_freq_by_index(smu, clk_type, 
soft_max_level, _freq);
+   if (ret)
+   return size;
+   }
+   ret = smu_set_soft_freq_range(smu, clk_type, min_freq, 
max_freq);
+   if (ret)
+   return size;
+   break;
 case SMU_SOCCLK:
 case SMU_MCLK:
 case SMU_UCLK:
@@ -690,11 +717,9 @@ static int navi10_force_clk_levels(struct smu_context *smu,
 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, 
_freq);
 if (ret)
 return size;
-
 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_max_level, 
_freq);
 if (ret)
 return size;
-
 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, 
max_freq);
 if (ret)
 return size;
@@ -838,6 +863,7 @@ static int navi10_unforce_dpm_levels(struct smu_context 
*smu)
 int ret = 0, i = 0;
 uint32_t min_freq, max_freq;

RE: [PATCH 2/3] drm/amd/powerplay: force sclk limit for peak profile

Re: [PATCH 2/3] drm/amd/powerplay: force sclk limit for peak profile

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