RE: [PATCH 2/3] drm/amdgpu: Correct the read sclk for navi10
[AMD Official Use Only - Internal Distribution Only] Hello Emily, The average clock value is a little different from the 'current clock' value. May I know what's the purpose of this patch to display the average clock? Any issue or any customer requirement? Thanks. Best Regards Kenneth -Original Message- From: amd-gfx On Behalf Of Emily.Deng Sent: Wednesday, January 6, 2021 9:05 AM To: amd-gfx@lists.freedesktop.org Cc: Deng, Emily Subject: [PATCH 2/3] drm/amdgpu: Correct the read sclk for navi10 [CAUTION: External Email] According to hw, after navi10,it runs in dfll mode, and should read sclk from AverageGfxclkFrequency. Signed-off-by: Emily.Deng --- drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c index 51e83123f72a..7ebf9588983f 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c @@ -1673,7 +1673,7 @@ static int navi10_read_sensor(struct smu_context *smu, *size = 4; break; case AMDGPU_PP_SENSOR_GFX_SCLK: - ret = navi10_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data); + ret = navi10_get_smu_metrics_data(smu, + METRICS_AVERAGE_GFXCLK, (uint32_t *)data); *(uint32_t *)data *= 100; *size = 4; break; -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfxdata=04%7C01%7CKenneth.Feng%40amd.com%7Cf8dd063d81db4666206308d8b1df2912%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637454919344238874%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=mXK3%2F5g4lqMFFN1ovavfXdbuypZK2FUGbAEce9VPTWs%3Dreserved=0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH 2/3] drm/amdgpu: Correct the read sclk for navi10
[AMD Official Use Only - Internal Distribution Only] Reviewed-by: Evan Quan -Original Message- From: amd-gfx On Behalf Of Emily.Deng Sent: Wednesday, January 6, 2021 9:05 AM To: amd-gfx@lists.freedesktop.org Cc: Deng, Emily Subject: [PATCH 2/3] drm/amdgpu: Correct the read sclk for navi10 According to hw, after navi10,it runs in dfll mode, and should read sclk from AverageGfxclkFrequency. Signed-off-by: Emily.Deng --- drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c index 51e83123f72a..7ebf9588983f 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c @@ -1673,7 +1673,7 @@ static int navi10_read_sensor(struct smu_context *smu, *size = 4; break; case AMDGPU_PP_SENSOR_GFX_SCLK: -ret = navi10_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data); +ret = navi10_get_smu_metrics_data(smu, METRICS_AVERAGE_GFXCLK, (uint32_t *)data); *(uint32_t *)data *= 100; *size = 4; break; -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfxdata=04%7C01%7Cevan.quan%40amd.com%7Cf8dd063d81db4666206308d8b1df2912%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637454919343172670%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=gA1B8ytfQj0g5TMPHYYC%2FKNUli2qY7iY%2Fc1vn4M7vWA%3Dreserved=0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 2/3] drm/amdgpu: Correct the read sclk for navi10
On Tue, Jan 5, 2021 at 8:05 PM Emily.Deng wrote: > > According to hw, after navi10,it runs in dfll mode, and should > read sclk from AverageGfxclkFrequency. > > Signed-off-by: Emily.Deng Acked-by: Alex Deucher > --- > drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c > b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c > index 51e83123f72a..7ebf9588983f 100644 > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c > @@ -1673,7 +1673,7 @@ static int navi10_read_sensor(struct smu_context *smu, > *size = 4; > break; > case AMDGPU_PP_SENSOR_GFX_SCLK: > - ret = navi10_get_current_clk_freq_by_table(smu, SMU_GFXCLK, > (uint32_t *)data); > + ret = navi10_get_smu_metrics_data(smu, > METRICS_AVERAGE_GFXCLK, (uint32_t *)data); > *(uint32_t *)data *= 100; > *size = 4; > break; > -- > 2.25.1 > > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH 2/3] drm/amdgpu: Correct the read sclk for navi10
[AMD Official Use Only - Internal Distribution Only] >-Original Message- >From: Quan, Evan >Sent: Tuesday, January 5, 2021 5:07 PM >To: Deng, Emily ; amd-gfx@lists.freedesktop.org >Cc: Deng, Emily >Subject: RE: [PATCH 2/3] drm/amdgpu: Correct the read sclk for navi10 > >[AMD Official Use Only - Internal Distribution Only] > >What's the issue with original implementation? > And does other clock domains(e.g uclk) need this fix also? According to smu team, after navi10, it will use dfll mode, for sclk read from CurrClock is not correct, need to read from AverageGfxclkFrequency in SmuMetrics_t. Will add this in comment. > >-Original Message- >From: amd-gfx On Behalf Of >Emily.Deng >Sent: Tuesday, January 5, 2021 4:37 PM >To: amd-gfx@lists.freedesktop.org >Cc: Deng, Emily >Subject: [PATCH 2/3] drm/amdgpu: Correct the read sclk for navi10 > >Signed-off-by: Emily.Deng >--- > drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > >diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c >b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c >index 51e83123f72a..7ebf9588983f 100644 >--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c >+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c >@@ -1673,7 +1673,7 @@ static int navi10_read_sensor(struct smu_context >*smu, *size = 4; break; case AMDGPU_PP_SENSOR_GFX_SCLK: >-ret = navi10_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t >*)data); >+ret = navi10_get_smu_metrics_data(smu, METRICS_AVERAGE_GFXCLK, >+(uint32_t *)data); > *(uint32_t *)data *= 100; > *size = 4; > break; >-- >2.25.1 > >___ >amd-gfx mailing list >amd-gfx@lists.freedesktop.org >https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.f >reedesktop.org%2Fmailman%2Flistinfo%2Famd- >gfxdata=04%7C01%7Cevan.quan%40amd.com%7C8f2af901fd044c097 >8a408d8b155289f%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C >637454326608630462%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwM >DAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata >=mzE040qzS6j1%2Fy85pZgUE1q3Pl6LLYOIe6Z7S3zsxJw%3Dreserved=0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH 2/3] drm/amdgpu: Correct the read sclk for navi10
[AMD Official Use Only - Internal Distribution Only] What's the issue with original implementation? And does other clock domains(e.g uclk) need this fix also? -Original Message- From: amd-gfx On Behalf Of Emily.Deng Sent: Tuesday, January 5, 2021 4:37 PM To: amd-gfx@lists.freedesktop.org Cc: Deng, Emily Subject: [PATCH 2/3] drm/amdgpu: Correct the read sclk for navi10 Signed-off-by: Emily.Deng --- drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c index 51e83123f72a..7ebf9588983f 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c @@ -1673,7 +1673,7 @@ static int navi10_read_sensor(struct smu_context *smu, *size = 4; break; case AMDGPU_PP_SENSOR_GFX_SCLK: -ret = navi10_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data); +ret = navi10_get_smu_metrics_data(smu, METRICS_AVERAGE_GFXCLK, (uint32_t *)data); *(uint32_t *)data *= 100; *size = 4; break; -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfxdata=04%7C01%7Cevan.quan%40amd.com%7C8f2af901fd044c0978a408d8b155289f%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637454326608630462%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=mzE040qzS6j1%2Fy85pZgUE1q3Pl6LLYOIe6Z7S3zsxJw%3Dreserved=0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
