RE: [PATCH V2] drm/amdgpu: fix incorrect GCR_GENERAL_CNTL address
Reviewed-by: Aaron Liu -- Best Regards Aaron Liu > -Original Message- > From: amd-gfx On Behalf Of Ji, Ruili > Sent: Monday, March 28, 2022 12:59 PM > To: amd-gfx@lists.freedesktop.org > Cc: Zhang, Yifan ; Liu, Aaron > ; Liang, Prike ; Huang, Ray > ; Deucher, Alexander > ; Ji, Ruili > Subject: [PATCH V2] drm/amdgpu: fix incorrect GCR_GENERAL_CNTL address > > From: Ruili Ji > > gfx10.3.3/gfx10.3.6/gfx10.3.7 shall use 0x1580 address for > GCR_GENERAL_CNTL > > Signed-off-by: Ruili Ji > --- > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > index 99df18ae7316..e4c9d92ac381 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > @@ -3300,7 +3300,7 @@ static const struct soc15_reg_golden > golden_settings_gc_10_3_3[] = > SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x, > 0x0280), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x, > 0x0080), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, > 0x0c1807ff, 0x0242), > - SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, > 0x1ff1, 0x0500), > + SOC15_REG_GOLDEN_VALUE(GC, 0, > mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1, > +0x0500), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x00ff, > 0x00e4), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, > 0x, 0x32103210), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, > 0x, 0x32103210), @@ -3436,7 +3436,7 @@ static const struct > soc15_reg_golden golden_settings_gc_10_3_6[] = > SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x, > 0x0280), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x, > 0x0080), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, > 0x0c1807ff, 0x0042), > - SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, > 0x1ff1, 0x0500), > + SOC15_REG_GOLDEN_VALUE(GC, 0, > mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1, > +0x0500), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x00ff, > 0x0044), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, > 0x, 0x32103210), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, > 0x, 0x32103210), @@ -3461,7 +3461,7 @@ static const struct > soc15_reg_golden golden_settings_gc_10_3_7[] = { > SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x, > 0x0280), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x, > 0x0080), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, > 0x0c1807ff, 0x0041), > - SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, > 0x1ff1, 0x0500), > + SOC15_REG_GOLDEN_VALUE(GC, 0, > mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1, > +0x0500), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x00ff, > 0x00e4), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, > 0x, 0x32103210), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, > 0x, 0x32103210), > -- > 2.25.1
RE: [PATCH V2] drm/amdgpu: fix incorrect GCR_GENERAL_CNTL address
[AMD Official Use Only] Reviewed-by: Yifan Zhang -Original Message- From: amd-gfx On Behalf Of Ji, Ruili Sent: Monday, March 28, 2022 12:59 PM To: amd-gfx@lists.freedesktop.org Cc: Zhang, Yifan ; Liu, Aaron ; Liang, Prike ; Huang, Ray ; Deucher, Alexander ; Ji, Ruili Subject: [PATCH V2] drm/amdgpu: fix incorrect GCR_GENERAL_CNTL address From: Ruili Ji gfx10.3.3/gfx10.3.6/gfx10.3.7 shall use 0x1580 address for GCR_GENERAL_CNTL Signed-off-by: Ruili Ji --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 99df18ae7316..e4c9d92ac381 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -3300,7 +3300,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_3[] = SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x, 0x0280), SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x, 0x0080), SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x0242), - SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1, 0x0500), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1, +0x0500), SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x00ff, 0x00e4), SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x, 0x32103210), SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x, 0x32103210), @@ -3436,7 +3436,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_6[] = SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x, 0x0280), SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x, 0x0080), SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x0042), - SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1, 0x0500), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1, +0x0500), SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x00ff, 0x0044), SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x, 0x32103210), SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x, 0x32103210), @@ -3461,7 +3461,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = { SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x, 0x0280), SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x, 0x0080), SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x0041), - SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1, 0x0500), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1, +0x0500), SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x00ff, 0x00e4), SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x, 0x32103210), SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x, 0x32103210), -- 2.25.1
Re: [PATCH V2] drm/amdgpu: fix incorrect GCR_GENERAL_CNTL address
Dear Ruili, Thank you for your patch. Am 28.03.22 um 06:58 schrieb Ji, Ruili: From: Ruili Ji gfx10.3.3/gfx10.3.6/gfx10.3.7 shall use 0x1580 address for GCR_GENERAL_CNTL Is any “user-visible“ problem fixed by this? Please add a Fixes tag. Kind regards, Paul Signed-off-by: Ruili Ji --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 99df18ae7316..e4c9d92ac381 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -3300,7 +3300,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_3[] = SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x, 0x0280), SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x, 0x0080), SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x0242), - SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1, 0x0500), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1, 0x0500), SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x00ff, 0x00e4), SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x, 0x32103210), SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x, 0x32103210), @@ -3436,7 +3436,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_6[] = SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x, 0x0280), SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x, 0x0080), SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x0042), - SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1, 0x0500), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1, 0x0500), SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x00ff, 0x0044), SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x, 0x32103210), SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x, 0x32103210), @@ -3461,7 +3461,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = { SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x, 0x0280), SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x, 0x0080), SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x0041), - SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1, 0x0500), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1, 0x0500), SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x00ff, 0x00e4), SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x, 0x32103210), SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x, 0x32103210),
RE: [PATCH V2] drm/amdgpu: fix incorrect GCR_GENERAL_CNTL address
[AMD Official Use Only] Hi Paul, This is not related to any issue. Kind regards, Ruili -Original Message- From: Paul Menzel Sent: 2022年3月29日 16:16 To: Ji, Ruili Cc: amd-gfx@lists.freedesktop.org; Zhang, Yifan ; Liu, Aaron ; Liang, Prike ; Huang, Ray ; Deucher, Alexander ; Ji, Ruili Subject: Re: [PATCH V2] drm/amdgpu: fix incorrect GCR_GENERAL_CNTL address [CAUTION: External Email] Dear Ruili, Thank you for your patch. Am 28.03.22 um 06:58 schrieb Ji, Ruili: > From: Ruili Ji > > gfx10.3.3/gfx10.3.6/gfx10.3.7 shall use 0x1580 address for > GCR_GENERAL_CNTL Is any “user-visible“ problem fixed by this? Please add a Fixes tag. Kind regards, Paul > Signed-off-by: Ruili Ji > --- > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > index 99df18ae7316..e4c9d92ac381 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > @@ -3300,7 +3300,7 @@ static const struct soc15_reg_golden > golden_settings_gc_10_3_3[] = > SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x, 0x0280), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x, 0x0080), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x0242), > - SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1, > 0x0500), > + SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, > + 0x1ff1, 0x0500), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x00ff, 0x00e4), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x, > 0x32103210), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x, > 0x32103210), @@ -3436,7 +3436,7 @@ static const struct soc15_reg_golden > golden_settings_gc_10_3_6[] = > SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x, 0x0280), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x, 0x0080), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x0042), > - SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1, > 0x0500), > + SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, > + 0x1ff1, 0x0500), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x00ff, 0x0044), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x, > 0x32103210), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x, > 0x32103210), @@ -3461,7 +3461,7 @@ static const struct soc15_reg_golden > golden_settings_gc_10_3_7[] = { > SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x, 0x0280), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x, 0x0080), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x0041), > - SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1, > 0x0500), > + SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, > + 0x1ff1, 0x0500), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x00ff, 0x00e4), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x, > 0x32103210), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x, > 0x32103210),
Re: [PATCH V2] drm/amdgpu: fix incorrect GCR_GENERAL_CNTL address
Dear Ruili, Am 29.03.22 um 11:17 schrieb Ji, Ruili: This is not related to any issue. I didn’t mean an issue (where I’d use Resolves to differentiate the two cases), but the commit introducing the incorrect address. Kind regards, Paul PS: Please use interleaved style when replying instead of top-posting.