RE: [PATCH v2 1/6] drm/amdgpu: add mode2 reset for sienna_cichlid
[AMD Official Use Only - General] Thanks for catching. Thanks, Victor -Original Message- From: Quan, Evan Sent: Friday, July 29, 2022 2:06 PM To: Zhao, Victor ; amd-gfx@lists.freedesktop.org Cc: Deng, Emily ; Zhao, Victor ; Grodzovsky, Andrey Subject: RE: [PATCH v2 1/6] drm/amdgpu: add mode2 reset for sienna_cichlid [AMD Official Use Only - General] > -Original Message- > From: amd-gfx On Behalf Of > Victor Zhao > Sent: Thursday, July 28, 2022 6:30 PM > To: amd-gfx@lists.freedesktop.org > Cc: Deng, Emily ; Zhao, Victor > ; Grodzovsky, Andrey > Subject: [PATCH v2 1/6] drm/amdgpu: add mode2 reset for sienna_cichlid > > To meet the requirement for multi container usecase which needs a > quicker reset and not causing VRAM lost, adding the Mode2 reset > handler for sienna_cichlid. > > v2: move skip mode2 flag part separately > > Signed-off-by: Victor Zhao > --- > drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- > drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c | 7 + > drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c | 297 > ++ > drivers/gpu/drm/amd/amdgpu/sienna_cichlid.h | 32 ++ > .../pm/swsmu/inc/pmfw_if/smu_v11_0_7_ppsmc.h | 4 +- > drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 3 +- > .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 54 > 7 files changed, 395 insertions(+), 4 deletions(-) create mode > 100644 drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c > create mode 100644 drivers/gpu/drm/amd/amdgpu/sienna_cichlid.h > > diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile > b/drivers/gpu/drm/amd/amdgpu/Makefile > index c7d0cd15b5ef..7030ac2d7d2c 100644 > --- a/drivers/gpu/drm/amd/amdgpu/Makefile > +++ b/drivers/gpu/drm/amd/amdgpu/Makefile > @@ -75,7 +75,7 @@ amdgpu-y += \ > vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o > vega10_reg_init.o \ > vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o arct_reg_init.o > mxgpu_nv.o \ > nbio_v7_2.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o aldebaran.o > soc21.o \ > - nbio_v4_3.o hdp_v6_0.o nbio_v7_7.o hdp_v5_2.o lsdma_v6_0.o > + sienna_cichlid.o nbio_v4_3.o hdp_v6_0.o nbio_v7_7.o hdp_v5_2.o > lsdma_v6_0.o > > # add DF block > amdgpu-y += \ > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c > index 32c86a0b145c..f778466bb9db 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c > @@ -23,6 +23,7 @@ > > #include "amdgpu_reset.h" > #include "aldebaran.h" > +#include "sienna_cichlid.h" > > int amdgpu_reset_add_handler(struct amdgpu_reset_control *reset_ctl, >struct amdgpu_reset_handler *handler) @@ -40,6 > +41,9 @@ int > amdgpu_reset_init(struct amdgpu_device *adev) > case IP_VERSION(13, 0, 2): > ret = aldebaran_reset_init(adev); > break; > + case IP_VERSION(11, 0, 7): > + ret = sienna_cichlid_reset_init(adev); > + break; > default: > break; > } > @@ -55,6 +59,9 @@ int amdgpu_reset_fini(struct amdgpu_device *adev) > case IP_VERSION(13, 0, 2): > ret = aldebaran_reset_fini(adev); > break; > + case IP_VERSION(11, 0, 7): > + ret = sienna_cichlid_reset_fini(adev); > + break; > default: > break; > } > diff --git a/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c > b/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c > new file mode 100644 > index ..0512960bed23 > --- /dev/null > +++ b/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c > @@ -0,0 +1,297 @@ > +/* > + * Copyright 2021 Advanced Micro Devices, Inc. > + * > + * Permission is hereby granted, free of charge, to any person > +obtaining a > + * copy of this software and associated documentation files (the > "Software"), > + * to deal in the Software without restriction, including without > + limitation > + * the rights to use, copy, modify, merge, publish, distribute, > + sublicense, > + * and/or sell copies of the Software, and to permit persons to whom > + the > + * Software is furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be > + included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF > MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT
RE: [PATCH v2 1/6] drm/amdgpu: add mode2 reset for sienna_cichlid
[AMD Official Use Only - General] > -Original Message- > From: amd-gfx On Behalf Of > Victor Zhao > Sent: Thursday, July 28, 2022 6:30 PM > To: amd-gfx@lists.freedesktop.org > Cc: Deng, Emily ; Zhao, Victor > ; Grodzovsky, Andrey > > Subject: [PATCH v2 1/6] drm/amdgpu: add mode2 reset for sienna_cichlid > > To meet the requirement for multi container usecase which needs > a quicker reset and not causing VRAM lost, adding the Mode2 > reset handler for sienna_cichlid. > > v2: move skip mode2 flag part separately > > Signed-off-by: Victor Zhao > --- > drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- > drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c | 7 + > drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c | 297 > ++ > drivers/gpu/drm/amd/amdgpu/sienna_cichlid.h | 32 ++ > .../pm/swsmu/inc/pmfw_if/smu_v11_0_7_ppsmc.h | 4 +- > drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 3 +- > .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 54 > 7 files changed, 395 insertions(+), 4 deletions(-) > create mode 100644 drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c > create mode 100644 drivers/gpu/drm/amd/amdgpu/sienna_cichlid.h > > diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile > b/drivers/gpu/drm/amd/amdgpu/Makefile > index c7d0cd15b5ef..7030ac2d7d2c 100644 > --- a/drivers/gpu/drm/amd/amdgpu/Makefile > +++ b/drivers/gpu/drm/amd/amdgpu/Makefile > @@ -75,7 +75,7 @@ amdgpu-y += \ > vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o > nbio_v7_0.o vega10_reg_init.o \ > vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o arct_reg_init.o > mxgpu_nv.o \ > nbio_v7_2.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o > aldebaran.o soc21.o \ > - nbio_v4_3.o hdp_v6_0.o nbio_v7_7.o hdp_v5_2.o lsdma_v6_0.o > + sienna_cichlid.o nbio_v4_3.o hdp_v6_0.o nbio_v7_7.o hdp_v5_2.o > lsdma_v6_0.o > > # add DF block > amdgpu-y += \ > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c > index 32c86a0b145c..f778466bb9db 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c > @@ -23,6 +23,7 @@ > > #include "amdgpu_reset.h" > #include "aldebaran.h" > +#include "sienna_cichlid.h" > > int amdgpu_reset_add_handler(struct amdgpu_reset_control *reset_ctl, >struct amdgpu_reset_handler *handler) > @@ -40,6 +41,9 @@ int amdgpu_reset_init(struct amdgpu_device *adev) > case IP_VERSION(13, 0, 2): > ret = aldebaran_reset_init(adev); > break; > + case IP_VERSION(11, 0, 7): > + ret = sienna_cichlid_reset_init(adev); > + break; > default: > break; > } > @@ -55,6 +59,9 @@ int amdgpu_reset_fini(struct amdgpu_device *adev) > case IP_VERSION(13, 0, 2): > ret = aldebaran_reset_fini(adev); > break; > + case IP_VERSION(11, 0, 7): > + ret = sienna_cichlid_reset_fini(adev); > + break; > default: > break; > } > diff --git a/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c > b/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c > new file mode 100644 > index ..0512960bed23 > --- /dev/null > +++ b/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c > @@ -0,0 +1,297 @@ > +/* > + * Copyright 2021 Advanced Micro Devices, Inc. > + * > + * Permission is hereby granted, free of charge, to any person obtaining a > + * copy of this software and associated documentation files (the > "Software"), > + * to deal in the Software without restriction, including without limitation > + * the rights to use, copy, modify, merge, publish, distribute, sublicense, > + * and/or sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF > MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO > EVENT SHALL > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, > DAMAGES OR > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR > OTHERWISE, > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR > THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + * > + */ > + > +#include "sienna_cichlid.h" > +#include "amdgpu_reset.h" > +#include "amdgpu_amdkfd.h" > +#include "amdgpu_dpm.h" > +#include "amdgpu_job.h" > +#include "amdgpu_ring.h" > +#include "amdgpu_ras.h" > +#include "amdgpu_psp.h" > +#include "amdgpu_xgmi.h" > + > +static struct amdgpu_reset_handler * > +sienna_cichlid_get_reset_handler(struct amdgpu_reset_control *reset_ctl, > + struct amdgpu_reset_context
Re: [PATCH v2 1/6] drm/amdgpu: add mode2 reset for sienna_cichlid
On 2022-07-28 06:30, Victor Zhao wrote:
To meet the requirement for multi container usecase which needs
a quicker reset and not causing VRAM lost, adding the Mode2
reset handler for sienna_cichlid.
v2: move skip mode2 flag part separately
Signed-off-by: Victor Zhao
---
drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c | 7 +
drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c | 297 ++
drivers/gpu/drm/amd/amdgpu/sienna_cichlid.h | 32 ++
.../pm/swsmu/inc/pmfw_if/smu_v11_0_7_ppsmc.h | 4 +-
drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 3 +-
.../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 54
7 files changed, 395 insertions(+), 4 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/sienna_cichlid.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index c7d0cd15b5ef..7030ac2d7d2c 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -75,7 +75,7 @@ amdgpu-y += \
vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o
vega10_reg_init.o \
vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o arct_reg_init.o
mxgpu_nv.o \
nbio_v7_2.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o aldebaran.o
soc21.o \
- nbio_v4_3.o hdp_v6_0.o nbio_v7_7.o hdp_v5_2.o lsdma_v6_0.o
+ sienna_cichlid.o nbio_v4_3.o hdp_v6_0.o nbio_v7_7.o hdp_v5_2.o
lsdma_v6_0.o
# add DF block
amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
index 32c86a0b145c..f778466bb9db 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
@@ -23,6 +23,7 @@
#include "amdgpu_reset.h"
#include "aldebaran.h"
+#include "sienna_cichlid.h"
int amdgpu_reset_add_handler(struct amdgpu_reset_control *reset_ctl,
struct amdgpu_reset_handler *handler)
@@ -40,6 +41,9 @@ int amdgpu_reset_init(struct amdgpu_device *adev)
case IP_VERSION(13, 0, 2):
ret = aldebaran_reset_init(adev);
break;
+ case IP_VERSION(11, 0, 7):
+ ret = sienna_cichlid_reset_init(adev);
+ break;
default:
break;
}
@@ -55,6 +59,9 @@ int amdgpu_reset_fini(struct amdgpu_device *adev)
case IP_VERSION(13, 0, 2):
ret = aldebaran_reset_fini(adev);
break;
+ case IP_VERSION(11, 0, 7):
+ ret = sienna_cichlid_reset_fini(adev);
+ break;
default:
break;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c
b/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c
new file mode 100644
index ..0512960bed23
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c
@@ -0,0 +1,297 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "sienna_cichlid.h"
+#include "amdgpu_reset.h"
+#include "amdgpu_amdkfd.h"
+#include "amdgpu_dpm.h"
+#include "amdgpu_job.h"
+#include "amdgpu_ring.h"
+#include "amdgpu_ras.h"
+#include "amdgpu_psp.h"
+#include "amdgpu_xgmi.h"
+
+static struct amdgpu_reset_handler *
+sienna_cichlid_get_reset_handler(struct amdgpu_reset_control *reset_ctl,
+ struct amdgpu_reset_context *reset_context)
+{
+ struct amdgpu_reset_handler *handler;
+ struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
+
+ if (reset_context->method != AMD_RESET_METHOD_NONE) {
+ list_for_each_entry(handler, _ctl->reset_handlers,
+handler_list) {
+ if (handler->reset_method == reset_context->method)
+ return handler;
