Re: [ARTIQ] DDR3 status on KC705
On 09/03/2014 01:56 AM, Sébastien Bourdeauducq wrote: > Florent and I got the full DDR3 SODIMM to work on the KC705 board. The > peak bandwidth is 64Gbps, which I think sets the record of the fastest > open source SDRAM controller :) Congratulations! Impressive tour de force. > Please test on yours and report your results - all the code is committed > in MiSoC, so you should be able to build and flash everything with: I guess so far I have been the only one here at NIST regularly reading the code, building, and testing it. It would be great if someone could spend the time and get familiar with migen/misoc/artiq. Anyone interested? I have a KC705 around if needed. > The write delay on the data lines is set to the write leveling DQS delay > minus half a bit time to meet the DQS/DQ setup/hold requirements. At > this point, we have functional writes to the SDRAM. Why don't you place them in the middle of the working window as you do with the reads? Regards, Robert. ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
Re: [ARTIQ] DDR3 status on KC705
On 09/04/2014 08:46 AM, Robert Jordens wrote: >> The write delay on the data lines is set to the write leveling DQS delay >> minus half a bit time to meet the DQS/DQ setup/hold requirements. At >> this point, we have functional writes to the SDRAM. > > Why don't you place them in the middle of the working window as you do > with the reads? Initially, we have no way of measuring where the working window is, as reading does not work yet and the current code needs to write the PRNG sequence to be able to calibrate the reads. So the timings are placed in the middle of the theoretical working window, assuming zero skew between DQ and DQS (they are length-matched and have the same load, so this is not an unreasonable assumption). One perk of the monster-FPGA is calibrated output delays, which makes that easier to achieve. If that turns out not to be enough, we can place the DQ write timings in the middle of the actual working window after the read calibration is done, in order to give the system more resistance against post-calibration timing variations due to e.g. temperature or voltage fluctuations. We can also use the MR test pattern (a special mode that makes the SDRAM output predefined data in response to all reads) to calibrate the reads independently of the writes. By the way, the calibrated delays are a neat feature - we could even use them to get 39ps output resolution on RTIO... Sébastien ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
Re: [ARTIQ] DDR3 status on KC705
> > Please test on yours and report your results - all the code is > > committed in MiSoC, so you should be able to build and flash everything > > with: > I guess so far I have been the only one here at NIST regularly reading the > code, building, and testing it. > It would be great if someone could spend the time and get familiar with > migen/misoc/artiq. Anyone > interested? I have a KC705 around if needed. I have another KC705 that I plan to set up to do regular build/test work now, and I will get familiar with the tools needed to do so. Robert, perhaps I can lean on you if I hit any roadblocks. I will also put together a breakout from the LPC HMC on the board to our existing ribbon cables for DDS and TTL, so that the KC705 can be used to drive our experimental hardware for tests. ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
Re: [ARTIQ] DDR3 status on KC705
On 09/03/2014 01:56 AM, Sébastien Bourdeauducq wrote: > Please test on yours and report your results - all the code is committed > in MiSoC, so you should be able to build and flash everything with: Works fine here. The windows look good with vivado as well as ise. Temperature and/or vivado-ise differences change it by at most one bit time. Write leveling: 14* 15* 13 13 9 9 5 5 completed Read bitslip: 7 6 5 4 3 2 Read delays: 7:02-12 6:01-11 5:03-14 4:05-15 3:11-21 2:11-20 1:00-09 0:00-10 completed Memtest OK Robert. ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
Re: [ARTIQ] DDR3 status on KC705
On 09/05/2014 01:39 PM, Robert Jordens wrote: > Works fine here. The windows look good with vivado as well as ise. Great! > Temperature and/or vivado-ise differences change it by at most one bit > time. I guess you meant a IODELAY tap? Sébastien ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
Re: [ARTIQ] DDR3 status on KC705
On 09/05/2014 04:07 AM, Sébastien Bourdeauducq wrote: >> Temperature and/or vivado-ise differences change it by at most one bit >> time. > > I guess you meant a IODELAY tap? Yes. Robert. ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
