Re: Last notice of Trainer's Friend training kits sale
Do you have any CICS kits ? Best Regards, Larry Larry Lawler -Original Message- From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of Steve Comstock Sent: Wednesday, November 27, 2013 9:23 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Last notice of Trainer's Friend training kits sale This is for organizations who need 30 days to get through a requisition / paperwork cycle, and it will be the last notice of our sale, so in the future we will not take up any bandwidth on it. The Trainer's Friend, Inc. is closing its [virtual] doors as of December 31, 2013. Prior to that, we are holding a Going Out Of Business (GOOB) sale of our training kits and a collection of my technical papers. Tons of detail are available at: http://www.trainersfriend.com/SpecialSale/ but here's a quick overview... A training kit is a collection of files that enables an instructor to teach a course (or allows a course to be taken as self-study[-with-mentor]). Typically a training kit from us contains: * Presentation version of content (PDF) * Print master for student handout version of content (PDF) * Instructor notes (PDF) * Lab files (XMIT) * Instructions for installing lab files on mainframe (PDF) Historically, we have priced training kits at USD 2000 per course day. For this sale, we are pricing them at USD 200 per course day - a 90% discount. Our courses are focused on z/OS application programmers, although some courses might be useful for beginning systems programmers, operators, end users, and so on. The topic areas for which we have training kits include: * Introduction to application programming (z/OS) * ISPF, CLIST, REXX, Dialog Manager * JCL and Utilities, DFSORT * Assembler Language * COBOL * PL/I * C * VSAM * DB2 * Language Environment * Cross program communications * DLLs * Debug Tool * z/OS UNIX (including building web pages and coding CGIs) 64 courses in all, totalling 192 training days. In addition we have these special offers: * Total package - all courses plus technical papers USD 3 * Steve package - all my courses plus technical papers USD 17000 * Hunter packate - all Hunter's courses USD 16000 * Bulk discount - if purchasing individual courses, if total is 10 or more training days, additional 15% discount for training kits (so: USD 170 per course day) This is spelled out here: http://www.trainersfriend.com/SpecialSale/SpecialDeal.html The sale is going well so far, but we just wanted to put in a gentle reminder before it is no longer available. Sale ends December 30, 2013. Kind regards, -Steve Comstock, founder The Trainer's Friend, Inc. 303-355-2752
Re: Making an old macro baseless
I thought LAY required a more recent processor? Sent from my iPhone On Aug 15, 2013, at 14:47, Robert Ngan rn...@csc.com wrote: If the label could be in the module or in a dsect, I'd use LAY instead of LARL. Of course, this assumes you currently have addressability to the dsect, and the label is within +/- 512K of the dsect base register (or your module static data base register) which in 99.9% of cases is a good assumption. And you don't have to worry about halfword alignment. Robert Ngan CSC Financial Services Group IBM Mainframe Assembler List ASSEMBLER-LIST@listserv.uga.edu wrote on 2013/08/15 06:19:06: From: John P. Hrtmann jphartm...@gmail.com To: ASSEMBLER-LIST@listserv.uga.edu Date: 2013/08/15 06:21 Subject: Making an old macro baseless Sent by: IBM Mainframe Assembler List ASSEMBLER-LIST@listserv.uga.edu CMS Pipelines ships the macro #LAL. One would write: #LAL 2,'a message' This expands to a LA 2,=c'...' and LA 3,length. As the constant goes into a literal pool I can substitute LARL for even length literals without adding failures (unless the literal pool is more than 4G away). The general case of #LAL 2,label expands also to a LA. I can change that to a LARL only when the reference is to a control section. If the label is declared in a dummy section, there is no way around the USING and LA. (If the label is undefined at the time the #LAL macro is issued, all bets are off and I must clearly be conservative and go LA). So my question is: How to determine whether a label is in a DSECT or CSECT/RSECT? I think I can determine whether the symbol is absolute from the type attribute, so we don't need to worry about that. Or is there a way to determine the name of the section a symbol is in? If not, would a SETC function SECTION(x) returning the appropriate name be useful in generl? All it has to do is look in the symbol table and return a null string for undefined or absolute. A SETA function returning the ESD number of the containing section would also solve my problem (DSECTS have negative ESD IDs internally; absolute symbols are in ESD 0). SETA also gets round the problem of the symbol being in private code, so it is really the best. I guess there is the additional wrinkle that the target must be on a halfword boundary, but I can add a trailing blank to a literal that is an odd number of characters (as long as I don't mess up the length). Any suggestions?
Re: YREGS MACRO doc?
Or use the WORD keyword, in your search and replace C R1 R2 WORD -Original Message- From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of Robert A. Rosenberg Sent: Thursday, August 01, 2013 9:54 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: YREGS MACRO doc? At 10:48 -0400 on 08/01/2013, Tom Marchant wrote about Re: YREGS MACRO doc?: On Wed, 31 Jul 2013 20:07:52 -0500, John McKown wrote: I tend to use Rn_32 and Rn_64 An advantage of this over Rn, GRn and RWn is that a search for R1_32 doesn't find, e.g. R11_32. -- Tom Marchant You can always use R00-R15 which also does not confuse a search for register 1 with registers 10-15.
Re: YREGS MACRO doc?
This is what we use, and we did use RA before, but are trying to get away from that convention, due to 64-bit registers, such as GRA, GRE, GRF which looks too much like a field names now: *-* *DEFINE GENERAL PURPOSE 32-BIT REGISTER SYMBOLS *-* R0 EQU 0GR32 EQUATE FOR REGISTER 0 R1 EQU 1GR32 EQUATE FOR REGISTER 1 R2 EQU 2GR32 EQUATE FOR REGISTER 2 R3 EQU 3GR32 EQUATE FOR REGISTER 3 R4 EQU 4GR32 EQUATE FOR REGISTER 4 R5 EQU 5GR32 EQUATE FOR REGISTER 5 R6 EQU 6GR32 EQUATE FOR REGISTER 6 R7 EQU 7GR32 EQUATE FOR REGISTER 7 R8 EQU 8GR32 EQUATE FOR REGISTER 8 R9 EQU 9GR32 EQUATE FOR REGISTER 9 RA EQU 10GR32 EQUATE FOR REGISTER 10 R10 EQU 10GR32 EQUATE FOR REGISTER 10 RB EQU 11GR32 EQUATE FOR REGISTER 11 R11 EQU 11GR32 EQUATE FOR REGISTER 11 RC EQU 12GR32 EQUATE FOR REGISTER 12 R12 EQU 12GR32 EQUATE FOR REGISTER 12 RD EQU 13GR32 EQUATE FOR REGISTER 13 R13 EQU 13GR32 EQUATE FOR REGISTER 13 RE EQU 14GR32 EQUATE FOR REGISTER 14 R14 EQU 14GR32 EQUATE FOR REGISTER 14 RF EQU 15GR32 EQUATE FOR REGISTER 15 R15 EQU 15GR32 EQUATE FOR REGISTER 15 - - - - - - - - - - - - - - - - 1 Line(s) not Displayed *-* *DEFINE GENERAL PURPOSE 64-BIT REGISTER PAIR SYMBOLS *-* R0_R1EQU 0GR EQUATE FOR REGISTER PAIR 0/1 R2_R3EQU 2GR EQUATE FOR REGISTER PAIR 2/3 R4_R5EQU 4GR EQUATE FOR REGISTER PAIR 4/5 R6_R7EQU 6GR EQUATE FOR REGISTER PAIR 6/7 R8_R9EQU 8GR EQUATE FOR REGISTER PAIR 8/9 R10_R11 EQU 10GR EQUATE FOR REGISTER PAIR 10/11 R12_R13 EQU 12GR EQUATE FOR REGISTER PAIR 12/13 R14_R15 EQU 14GR EQUATE FOR REGISTER PAIR 14/15 - - - - - - - - - - - - - - - - 21 Line(s) not Displayed *-* *DEFINE GENERAL PURPOSE 64-BIT REGISTER SYMBOLS *-* GR0 EQU 0GR64 EQUATE FOR REGISTER 0 GR1 EQU 1GR64 EQUATE FOR REGISTER 1 GR2 EQU 2GR64 EQUATE FOR REGISTER 2 GR3 EQU 3GR64 EQUATE FOR REGISTER 3 GR4 EQU 4GR64 EQUATE FOR REGISTER 4 GR5 EQU 5GR64 EQUATE FOR REGISTER 5 GR6 EQU 6GR64 EQUATE FOR REGISTER 6 GR7 EQU 7GR64 EQUATE FOR REGISTER 7 GR8 EQU 8GR64 EQUATE FOR REGISTER 8 GR9 EQU 9GR64 EQUATE FOR REGISTER 9 GRA EQU 10GR64 EQUATE FOR REGISTER 10 GR10 EQU 10GR64 EQUATE FOR REGISTER 10 GRB EQU 11GR64 EQUATE FOR REGISTER 11 GR11 EQU 11GR64 EQUATE FOR REGISTER 11 GRC EQU 12GR64 EQUATE FOR REGISTER 12 GR12 EQU 12GR64 EQUATE FOR REGISTER 12 GRD EQU 13GR64 EQUATE FOR REGISTER 13 GR13 EQU 13GR64 EQUATE FOR REGISTER 13 GRE EQU 14GR64 EQUATE FOR REGISTER 14 GR14 EQU 14GR64 EQUATE FOR REGISTER 14 GRF EQU 15GR64 EQUATE FOR REGISTER 15 GR15 EQU 15GR64 EQUATE FOR REGISTER 15 - - - - - - - - - - - - - - - - 1 Line(s) not Displayed *-* *DEFINE GENERAL PURPOSE 128-BIT REGISTER PAIR SYMBOLS *-* GR0_R1 EQU 0GR EQUATE FOR REGISTER PAIR 0/1 GR2_R3 EQU 2GR EQUATE FOR REGISTER PAIR 2/3 GR4_R5 EQU 4GR EQUATE FOR REGISTER PAIR 4/5 GR6_R7 EQU 6GR EQUATE FOR REGISTER PAIR 6/7 GR8_R9 EQU 8GR EQUATE FOR REGISTER PAIR 8/9 GR10_R11 EQU 10GR EQUATE FOR REGISTER PAIR 10/11 GR12_R13 EQU 12GR EQUATE FOR REGISTER PAIR 12/13 GR14_R15 EQU 14GR
Re: 64 bit question
CVTV64 EQU X'10' 64-bit virtual services are present. *You should ensure FLCARCH (in IHAPSA) is *non-zero before using -Original Message- From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of Scott Ford Sent: Thursday, June 13, 2013 9:46 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: 64 bit question All, After reading through the Extended Addressability Guide/ref I have a question.. How do I tell if a machine will support 64 bit storage above the bar ? I mean like a Assembler macro query ..I want to use 64bit storage but I don't know to tell programmatically what the allocation is for the system. Regards, Scott ford www.identityforge.com from my IPAD 'Infinite wisdom through infinite means'
Re: Model 2827 New Instructions
yes, it was built for the java JVMs that use blocking techniques on non-z platforms but there is no reason we can't use it Best Regards, Larry Larry Lawler C.T.O. larry.law...@unicomglobal.com Unicom Systems Intl, Inc. 15535 San Fernando Mission Blvd. Suite 310, Unicom Plaza Mission Hills, CA 91345 Office: (949)-873-2225 VoIP x3883 This message (including any attachments) contains confidential information that is PRIVILEGED, CONFIDENTIAL and/or ATTORNEY WORK PRODUCT and is intended only for the individual(s) named herein. If you are not the intended recipient, you are hereby notified that any dissemination, distribution or copying of this email is strictly prohibited. If you have received this message in error, please notify the UNICOM Systems, Inc. Postmaster (postmas...@unicomsi.com) of the error immediately, do not read or use the email and any attachments in any manner, destroy all copies, and delete it from your system if the communication was sent via email. UNICOM Systems, Inc. (818) 838-0606 Fax: (818) 838-0776 * -Original Message- From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of Chuck Arney Sent: Tuesday, September 18, 2012 8:02 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Model 2827 New Instructions It seems to be an extended PLO instruction. Chuck Arney Arney Computer Systems -Original Message- From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of McKown, John Sent: Tuesday, September 18, 2012 1:21 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Model 2827 New Instructions I just read up on the Transaction Execution. I now need two things: 1. Aspirin; 2. a nap. I get the general concept, but the restrictions are immense. I guess it is good for a *very* short routine which does not update very much storage. The conditions under which it can abort are a multitude. I wonder exactly what it was that made IBM decide to implement it, as opposed to doing a CPU spin loop. I guess it is the only way to guarantee that another CPU simply cannot observe an in flight set of updates by *any* other code on *any* other CPU.
