Re: [PATCH] macb: rename platform data

2013-03-19 Thread Josh Cartwright 
On Fri, Mar 15, 2013 at 06:26:00PM -0500, Josh Cartwright wrote:
[..]
> >From 0d51dc731ff3934e22e78405a992658a8d3bf1de Mon Sep 17 00:00:00 2001
> From: Josh Cartwright 
> Date: Tue, 19 Mar 2013 10:22:48 -0500
> Subject: [PATCH] parameter: fix build warning when !CONFIG_PARAMETER
> To: barebox@lists.infradead.org

Ugh, sorry that I butchered patch submission and this mail ended up with
two patches together; should I resend?

> Commit 51f2ded17c35c146488f6f3b697764bb2953a156 ("param: make return
> value of param getter function const") made the parameter getter const,
> but neglected to change the dev_add_param() function prototype in the
> !CONFIG_PARAMETER case.
> 
> Fixes the following warning with CONFIG_NAND and !CONFIG_PARAMETER:
> 
> drivers/mtd/nand/nand_base.c: In function 'add_mtd_nand_device':
> drivers/mtd/nand/nand_base.c:1720:2: warning: passing argument 4 of 
> 'dev_add_param' from incompatible pointer type [enabled by default]
> include/param.h:59:19: note: expected 'char * (*)(struct device_d *, struct 
> param_d *)' but argument is of type 'const char * (*)(struct device_d *, 
> struct param_d *)'
> 
> Signed-off-by: Josh Cartwright 
> ---
>  include/param.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/include/param.h b/include/param.h
> index 21f4f7d..3a585cd 100644
> --- a/include/param.h
> +++ b/include/param.h
> @@ -58,7 +58,7 @@ static inline struct param_d *get_param_by_name(struct 
> device_d *dev,
>  
>  static inline int dev_add_param(struct device_d *dev, char *name,
>   int (*set)(struct device_d *dev, struct param_d *p, const char 
> *val),
> - char *(*get)(struct device_d *, struct param_d *p),
> + const char *(*get)(struct device_d *, struct param_d *p),
>   unsigned long flags)
>  {
>   return 0;
> -- 
> 1.8.1.5
> 
> 
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[PATCH] macb: rename platform data

2013-03-19 Thread Josh Cartwright 
The macb/gem core is used by the Zynq SoC.  In preparation of sharing
the macb driver between at91 and Zynq, rename the platform data to
'struct macb_platform_data', and move the definition to a common
location.

Signed-off-by: Josh Cartwright 
---
 arch/arm/boards/animeo_ip/init.c |  2 +-
 arch/arm/boards/at91rm9200ek/init.c  |  2 +-
 arch/arm/boards/at91sam9260ek/init.c |  2 +-
 arch/arm/boards/at91sam9263ek/init.c |  2 +-
 arch/arm/boards/at91sam9m10g45ek/init.c  |  2 +-
 arch/arm/boards/at91sam9m10ihd/init.c|  2 +-
 arch/arm/boards/at91sam9x5ek/init.c  |  2 +-
 arch/arm/boards/dss11/init.c |  2 +-
 arch/arm/boards/mmccpu/init.c|  2 +-
 arch/arm/boards/pm9263/init.c|  2 +-
 arch/arm/boards/pm9g45/init.c|  2 +-
 arch/arm/boards/qil-a9260/init.c |  2 +-
 arch/arm/boards/sama5d3xek/init.c|  4 ++--
 arch/arm/boards/telit-evk-pro3/init.c|  2 +-
 arch/arm/boards/tny-a926x/init.c |  2 +-
 arch/arm/boards/usb-a926x/init.c |  2 +-
 arch/arm/mach-at91/at91rm9200_devices.c  |  4 ++--
 arch/arm/mach-at91/at91sam9260_devices.c |  4 ++--
 arch/arm/mach-at91/at91sam9263_devices.c |  4 ++--
 arch/arm/mach-at91/at91sam9g45_devices.c |  4 ++--
 arch/arm/mach-at91/at91sam9x5_devices.c  |  4 ++--
 arch/arm/mach-at91/include/mach/board.h  | 11 ++-
 arch/arm/mach-at91/sama5d3_devices.c |  4 ++--
 drivers/net/at91_ether.c |  2 +-
 drivers/net/macb.c   |  4 ++--
 include/platform_data/macb.h | 30 ++
 26 files changed, 64 insertions(+), 41 deletions(-)
 create mode 100644 include/platform_data/macb.h

diff --git a/arch/arm/boards/animeo_ip/init.c b/arch/arm/boards/animeo_ip/init.c
index ada3bb0..07525b7 100644
--- a/arch/arm/boards/animeo_ip/init.c
+++ b/arch/arm/boards/animeo_ip/init.c
@@ -120,7 +120,7 @@ static void animeo_ip_add_device_nand(void)
at91_add_device_nand(&nand_pdata);
 }
 
-static struct at91_ether_platform_data macb_pdata = {
+static struct macb_platform_data macb_pdata = {
.phy_addr = 0,
 };
 
diff --git a/arch/arm/boards/at91rm9200ek/init.c 
b/arch/arm/boards/at91rm9200ek/init.c
index eec71bb..30aaae2 100644
--- a/arch/arm/boards/at91rm9200ek/init.c
+++ b/arch/arm/boards/at91rm9200ek/init.c
@@ -32,7 +32,7 @@
 #include 
 #include 
 
-static struct at91_ether_platform_data ether_pdata = {
+static struct macb_platform_data ether_pdata = {
.phy_interface = PHY_INTERFACE_MODE_RMII,
.phy_addr = 0,
 };
diff --git a/arch/arm/boards/at91sam9260ek/init.c 
b/arch/arm/boards/at91sam9260ek/init.c
index dc2976a..4e4a69d 100644
--- a/arch/arm/boards/at91sam9260ek/init.c
+++ b/arch/arm/boards/at91sam9260ek/init.c
@@ -114,7 +114,7 @@ static void ek_add_device_nand(void)
at91_add_device_nand(&nand_pdata);
 }
 
-static struct at91_ether_platform_data macb_pdata = {
+static struct macb_platform_data macb_pdata = {
.phy_interface = PHY_INTERFACE_MODE_RMII,
.phy_addr = 0,
 };
diff --git a/arch/arm/boards/at91sam9263ek/init.c 
b/arch/arm/boards/at91sam9263ek/init.c
index 90fdbec..a731d58 100644
--- a/arch/arm/boards/at91sam9263ek/init.c
+++ b/arch/arm/boards/at91sam9263ek/init.c
@@ -82,7 +82,7 @@ static void ek_add_device_nand(void)
at91_add_device_nand(&nand_pdata);
 }
 
-static struct at91_ether_platform_data macb_pdata = {
+static struct macb_platform_data macb_pdata = {
.phy_interface = PHY_INTERFACE_MODE_RMII,
.phy_addr = 0,
 };
diff --git a/arch/arm/boards/at91sam9m10g45ek/init.c 
b/arch/arm/boards/at91sam9m10g45ek/init.c
index 0ae7171..f32215d 100644
--- a/arch/arm/boards/at91sam9m10g45ek/init.c
+++ b/arch/arm/boards/at91sam9m10g45ek/init.c
@@ -105,7 +105,7 @@ static void ek_add_device_nand(void)
at91_add_device_nand(&nand_pdata);
 }
 
-static struct at91_ether_platform_data macb_pdata = {
+static struct macb_platform_data macb_pdata = {
.phy_interface = PHY_INTERFACE_MODE_RMII,
.phy_addr = 0,
 };
diff --git a/arch/arm/boards/at91sam9m10ihd/init.c 
b/arch/arm/boards/at91sam9m10ihd/init.c
index df63a91..fe77b3a 100644
--- a/arch/arm/boards/at91sam9m10ihd/init.c
+++ b/arch/arm/boards/at91sam9m10ihd/init.c
@@ -79,7 +79,7 @@ static void ek_add_device_nand(void)
at91_add_device_nand(&nand_pdata);
 }
 
-static struct at91_ether_platform_data macb_pdata = {
+static struct macb_platform_data macb_pdata = {
.phy_interface = PHY_INTERFACE_MODE_RMII,
.phy_addr = 0,
 };
diff --git a/arch/arm/boards/at91sam9x5ek/init.c 
b/arch/arm/boards/at91sam9x5ek/init.c
index 4e1e069..74cc7ab 100644
--- a/arch/arm/boards/at91sam9x5ek/init.c
+++ b/arch/arm/boards/at91sam9x5ek/init.c
@@ -105,7 +105,7 @@ static void ek_add_device_nand(void)
at91_add_device_nand(&nand_pdata);
 }
 
-static struct at91_ether_platform_data macb_pdata = {
+static struct macb_platform_data macb_pdata = {
.phy_interface = PHY_INTERFACE_MOD

Re: [PATCH v2 1/5] serial: Add driver for Cadence UART

2013-03-19 Thread Jean-Christophe PLAGNIOL-VILLARD 
On 10:21 Tue 19 Mar , Steffen Trumtrar wrote:
> Support for Cadence UART core.
> 
> Signed-off-by: Steffen Trumtrar 
> ---
>  drivers/serial/Kconfig  |   4 +
>  drivers/serial/Makefile |   1 +
>  drivers/serial/serial_cadence.c | 307 
> 
>  3 files changed, 312 insertions(+)
>  create mode 100644 drivers/serial/serial_cadence.c
> 
> diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
> index f61d670..a51510e 100644
> --- a/drivers/serial/Kconfig
> +++ b/drivers/serial/Kconfig
> @@ -113,4 +113,8 @@ config DRIVER_SERIAL_OMAP4_USBBOOT
>   help
> Enable this to get console support over the usb bus used to boot an 
> OMAP4
>  
> +config DRIVER_SERIAL_CADENCE
> + default n
no need it's already n
> + bool "Cadence UART driver"
> +
>  endmenu
> diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
> index 893e282..963a7df 100644
> --- a/drivers/serial/Makefile
> +++ b/drivers/serial/Makefile
> @@ -21,3 +21,4 @@ obj-$(CONFIG_DRIVER_SERIAL_ALTERA)  += 
> serial_altera.o
>  obj-$(CONFIG_DRIVER_SERIAL_ALTERA_JTAG)  += serial_altera_jtag.o
>  obj-$(CONFIG_DRIVER_SERIAL_PXA)  += serial_pxa.o
>  obj-$(CONFIG_DRIVER_SERIAL_OMAP4_USBBOOT)+= serial_omap4_usbboot.o
> +obj-$(CONFIG_DRIVER_SERIAL_CADENCE)  += serial_cadence.o
> diff --git a/drivers/serial/serial_cadence.c b/drivers/serial/serial_cadence.c
> new file mode 100644
> index 000..c29c391
> --- /dev/null
> +++ b/drivers/serial/serial_cadence.c
> @@ -0,0 +1,307 @@
> +/*
> + * (c) 2012 Steffen Trumtrar 
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + */
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#define CADENCE_UART_CONTROL 0x00
> +#define CADENCE_UART_MODE0x04
> +#define CADENCE_UART_BAUD_GEN0x18
> +#define CADENCE_UART_CHANNEL_STS 0x2C
> +#define CADENCE_UART_RXTXFIFO0x30
> +#define CADENCE_UART_BAUD_DIV0x34
> +
> +#define CADENCE_CTRL_RXRES   (1 << 0)
> +#define CADENCE_CTRL_TXRES   (1 << 1)
> +#define CADENCE_CTRL_RXEN(1 << 2)
> +#define CADENCE_CTRL_RXDIS   (1 << 3)
> +#define CADENCE_CTRL_TXEN(1 << 4)
> +#define CADENCE_CTRL_TXDIS   (1 << 5)
> +#define CADENCE_CTRL_RSTTO   (1 << 6)
> +#define CADENCE_CTRL_STTBRK  (1 << 7)
> +#define CADENCE_CTRL_STPBRK  (1 << 8)
> +
> +#define CADENCE_MODE_CLK_REF (0 << 0)
> +#define CADENCE_MODE_CLK_REF_DIV (1 << 0)
> +#define CADENCE_MODE_CHRL_6  (3 << 1)
> +#define CADENCE_MODE_CHRL_7  (2 << 1)
> +#define CADENCE_MODE_CHRL_8  (0 << 1)
> +#define CADENCE_MODE_PAR_EVEN(0 << 3)
> +#define CADENCE_MODE_PAR_ODD (1 << 3)
> +#define CADENCE_MODE_PAR_SPACE   (2 << 3)
> +#define CADENCE_MODE_PAR_MARK(3 << 3)
> +#define CADENCE_MODE_PAR_NONE(4 << 3)
> +
> +#define CADENCE_STS_REMPTY   (1 << 1)
> +#define CADENCE_STS_RFUL (1 << 2)
> +#define CADENCE_STS_TEMPTY   (1 << 3)
> +#define CADENCE_STS_TFUL (1 << 4)
move this to an include as we will use them for debug_ll
> +
> +/*
> + * create default values for different platforms
> + */
> +struct cadence_serial_devtype_data {
> + u32 ctrl;
> + u32 mode;
> +};
> +
> +static struct cadence_serial_devtype_data cadence_r1p08_data = {
> + .ctrl = CADENCE_CTRL_RXEN | CADENCE_CTRL_TXEN,
> + .mode = CADENCE_MODE_CLK_REF | CADENCE_MODE_CHRL_8 | 
> CADENCE_MODE_PAR_NONE,
> +};
> +
> +struct cadence_serial_priv {
> + struct console_device cdev;
> + int baudrate;
> + struct notifier_block notify;
> + void __iomem *regs;
> + struct clk *clk;
> + struct cadence_serial_devtype_data *devtype;
> +};
> +
> +static int cadence_serial_reset(struct console_device *cdev)
> +{
> + struct cadence_serial_priv *priv = container_of(cdev,
> + struct cadence_serial_priv, cdev);
> +
> + /* Soft-Reset Tx/Rx paths */
> + writel(CADENCE_CTRL_RXRES | CADENCE_CTRL_TXRES, priv->regs +
> + CADENCE_UART_CONTROL);
> +
> + while (readl(priv->regs + CADENCE_UART_CONTROL) &
> + (CADENCE_CTRL_RXRES | CADENCE_CTRL_TXRES))
> + ;
> +
> + return 0;
> +}
> +
> +static int cadence_serial_setbaudrate(struct console_dev

Re: [PATCH v2 5/5] ARM: zynq: Add support for the Avnet Zedboard

2013-03-19 Thread Jean-Christophe PLAGNIOL-VILLARD 
On 10:22 Tue 19 Mar , Steffen Trumtrar wrote:
> The Avnet ZedBoard is an evalboard with a Zynq-7020 based MPSoC.
> There is also a Digilent ZedBoard, that is the same but only for
> academic customers.
> 
> Signed-off-by: Steffen Trumtrar 
> ---
>  arch/arm/boards/avnet-zedboard/Makefile|   1 +
>  arch/arm/boards/avnet-zedboard/board.c |  38 
>  arch/arm/boards/avnet-zedboard/config.h|   4 +
>  .../boards/avnet-zedboard/env/init/config-board|   7 +
>  arch/arm/boards/avnet-zedboard/flash_header.c  |  76 +++
>  arch/arm/boards/avnet-zedboard/lowlevel.c  | 252 
> +
>  arch/arm/configs/zedboard_defconfig|  45 
>  7 files changed, 423 insertions(+)
>  create mode 100644 arch/arm/boards/avnet-zedboard/Makefile
>  create mode 100644 arch/arm/boards/avnet-zedboard/board.c
>  create mode 100644 arch/arm/boards/avnet-zedboard/config.h
>  create mode 100644 arch/arm/boards/avnet-zedboard/env/init/config-board
>  create mode 100644 arch/arm/boards/avnet-zedboard/flash_header.c
>  create mode 100644 arch/arm/boards/avnet-zedboard/lowlevel.c
>  create mode 100644 arch/arm/configs/zedboard_defconfig
> 
> diff --git a/arch/arm/boards/avnet-zedboard/Makefile 
> b/arch/arm/boards/avnet-zedboard/Makefile
> new file mode 100644
> index 000..5c05544
> --- /dev/null
> +++ b/arch/arm/boards/avnet-zedboard/Makefile
> @@ -0,0 +1 @@
> +obj-y += board.o lowlevel.o flash_header.o
> diff --git a/arch/arm/boards/avnet-zedboard/board.c 
> b/arch/arm/boards/avnet-zedboard/board.c
> new file mode 100644
> index 000..4e3d5a5
> --- /dev/null
> +++ b/arch/arm/boards/avnet-zedboard/board.c
> @@ -0,0 +1,38 @@
> +/*
> + * Copyright (C) 2013 Steffen Trumtrar 
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +static int zedboard_mem_init(void)
> +{
> + arm_add_mem_device("ram0", 0, SZ_512M);
> +
> + return 0;
> +}
> +mem_initcall(zedboard_mem_init);
> +
> +static int zedboard_console_init(void)
> +{
> + zynq_add_uart1();
> +
> + return 0;
> +}
> +console_initcall(zedboard_console_init);
> diff --git a/arch/arm/boards/avnet-zedboard/config.h 
> b/arch/arm/boards/avnet-zedboard/config.h
> new file mode 100644
> index 000..ca15136
> --- /dev/null
> +++ b/arch/arm/boards/avnet-zedboard/config.h
> @@ -0,0 +1,4 @@
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +#endif   /* __CONFIG_H */
> diff --git a/arch/arm/boards/avnet-zedboard/env/init/config-board 
> b/arch/arm/boards/avnet-zedboard/env/init/config-board
> new file mode 100644
> index 000..9957653
> --- /dev/null
> +++ b/arch/arm/boards/avnet-zedboard/env/init/config-board
> @@ -0,0 +1,7 @@
> +#!/bin/sh
> +
> +# board defaults, do not change in running system. Change /env/config
> +# instead
> +
> +global.hostname=ZedBoard
> +global.linux.bootargs.base="console=ttyPS1,115200"
> diff --git a/arch/arm/boards/avnet-zedboard/flash_header.c 
> b/arch/arm/boards/avnet-zedboard/flash_header.c
> new file mode 100644
> index 000..e7e2f8d
> --- /dev/null
> +++ b/arch/arm/boards/avnet-zedboard/flash_header.c
> @@ -0,0 +1,76 @@
> +/*
> + * Copyright (C) 2012 Steffen Trumtrar 
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +void __naked __flash_header_start go(void)
> +{
> + __asm__ __volatile__ (
> + "b barebox_arm_reset_vector\n"
> + "1: b 1b\n"
> + "1: b 1b\n"
> + "1: b 1b\n"
> + "1: b 1b\n"
> + "1: b 1b\n"
> + "1: b 1b\n"
> + "1: b 1b\n"
> + );
> +}
> +
> +#define REG(a, v) { .addr = cpu_to_le32(a), .val = cpu_to_le32(v), }
> +
> +struct zynq_reg_entry __ps7reg_entry_section reg_entry[] = {
> + REG(ZYNQ_SLCR_UNLOCK, 0xDF0D),
> + REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_CLK_621_TRUE, 0x0001),
>

Re: [PATCH v2 2/5] ARM: zynq: Add new architecture zynq

2013-03-19 Thread Jean-Christophe PLAGNIOL-VILLARD 
On 10:21 Tue 19 Mar , Steffen Trumtrar wrote:
> Add basic support for the Xilinx Zynq-7000 EPP architecture.
> The Zynq-7000 is an embedded processing platform that combines a Cortex A9
> dualcore MPSoC with an Artix-7 FPGA.
> 
> Signed-off-by: Steffen Trumtrar 
> ---
>  arch/arm/Kconfig   |   5 +
>  arch/arm/Makefile  |   2 +
>  arch/arm/mach-zynq/Kconfig |  39 ++
>  arch/arm/mach-zynq/Makefile|   1 +
>  arch/arm/mach-zynq/devices.c   |  14 +++
>  arch/arm/mach-zynq/include/mach/barebox.lds.h  |   9 ++
>  arch/arm/mach-zynq/include/mach/debug_ll.h |  37 ++
>  arch/arm/mach-zynq/include/mach/devices.h  |  13 ++
>  .../arm/mach-zynq/include/mach/zynq-flash-header.h |  40 +++
>  arch/arm/mach-zynq/include/mach/zynq7000-regs.h| 132 
> +
>  arch/arm/mach-zynq/zynq.c  |  56 +
>  include/asm-generic/barebox.lds.h  |   3 +-
>  12 files changed, 350 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/mach-zynq/Kconfig
>  create mode 100644 arch/arm/mach-zynq/Makefile
>  create mode 100644 arch/arm/mach-zynq/devices.c
>  create mode 100644 arch/arm/mach-zynq/include/mach/barebox.lds.h
>  create mode 100644 arch/arm/mach-zynq/include/mach/debug_ll.h
>  create mode 100644 arch/arm/mach-zynq/include/mach/devices.h
>  create mode 100644 arch/arm/mach-zynq/include/mach/zynq-flash-header.h
>  create mode 100644 arch/arm/mach-zynq/include/mach/zynq7000-regs.h
>  create mode 100644 arch/arm/mach-zynq/zynq.c
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 28332ec..8431fa8 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -110,6 +110,10 @@ config ARCH_TEGRA
>   select CPU_ARM926T
>   select HAS_DEBUG_LL
>  
> +config ARCH_ZYNQ
> + bool "Xilinx Zynq-based boards"
> + select HAS_DEBUG_LL
> +
>  endchoice
>  
>  source arch/arm/cpu/Kconfig
> @@ -126,6 +130,7 @@ source arch/arm/mach-pxa/Kconfig
>  source arch/arm/mach-samsung/Kconfig
>  source arch/arm/mach-versatile/Kconfig
>  source arch/arm/mach-tegra/Kconfig
> +source arch/arm/mach-zynq/Kconfig
>  
>  config ARM_ASM_UNIFIED
>   bool
> diff --git a/arch/arm/Makefile b/arch/arm/Makefile
> index fcb2969..ceb45dc 100644
> --- a/arch/arm/Makefile
> +++ b/arch/arm/Makefile
> @@ -64,6 +64,7 @@ machine-$(CONFIG_ARCH_PXA)  := pxa
>  machine-$(CONFIG_ARCH_SAMSUNG)   := samsung
>  machine-$(CONFIG_ARCH_VERSATILE) := versatile
>  machine-$(CONFIG_ARCH_TEGRA) := tegra
> +machine-$(CONFIG_ARCH_ZYNQ)  := zynq
>  
>  # Board directory name.  This list is sorted alphanumerically
>  # by CONFIG_* macro name.
> @@ -157,6 +158,7 @@ board-$(CONFIG_MACH_SABRELITE):= 
> freescale-mx6-sabrelite
>  board-$(CONFIG_MACH_TX53):= karo-tx53
>  board-$(CONFIG_MACH_GUF_VINCELL) := guf-vincell
>  board-$(CONFIG_MACH_EFIKA_MX_SMARTBOOK)  := efika-mx-smartbook
> +board-$(CONFIG_MACH_ZEDBOARD):= avnet-zedboard
>  
>  machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
>  
> diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
> new file mode 100644
> index 000..3965ad4
> --- /dev/null
> +++ b/arch/arm/mach-zynq/Kconfig
> @@ -0,0 +1,39 @@
> +if ARCH_ZYNQ
> +
> +config ARCH_TEXT_BASE
> + hex
> + default 0x1ff0 if MACH_ZEDBOARD
> +
> +config ZYNQ_DEBUG_LL_UART_BASE
> + hex
> + default 0xe0001000 if MACH_ZEDBOARD
> +
> +config BOARDINFO
> + default "ZedBoard" if MACH_ZEDBOARD
> +
> +choice
> + prompt "Xilinx Zynq type board"
> +
> +config ARCH_ZYNQ7000
> + bool "Zynq-7000"
> + select CPU_V7
> + select DRIVER_SERIAL_CADENCE
don't force it we may want NO serial support
> + select CLKDEV_LOOKUP
> + select COMMON_CLK
> + select ARM_SMP_TWD
> +
> +endchoice
> +
> +if ARCH_ZYNQ7000
> +
> +choice
> + prompt "Zynq-7000 Board Type"
> +
> +config MACH_ZEDBOARD
> + bool "Avnet Zynq-7000 ZedBoard"
> + select MACH_HAS_LOWLEVEL_INIT
???
> +
> +endchoice
> +endif
> +
> +endif
> diff --git a/arch/arm/mach-zynq/Makefile b/arch/arm/mach-zynq/Makefile
> new file mode 100644
> index 000..459c957
> --- /dev/null
> +++ b/arch/arm/mach-zynq/Makefile
> @@ -0,0 +1 @@
> +obj-y += zynq.o devices.o clk-zynq7000.o
> diff --git a/arch/arm/mach-zynq/devices.c b/arch/arm/mach-zynq/devices.c
> new file mode 100644
> index 000..2bb3c92
> --- /dev/null
> +++ b/arch/arm/mach-zynq/devices.c
> @@ -0,0 +1,14 @@
> +#include 
> +#include 
> +#include 
> +
> +static inline struct device_d *zynq_add_device(char *name, int id, void 
> *base, int size, void *pdata)
> +{
> + return add_generic_device(name, id, NULL, (resource_size_t)base, size,
> +   IORESOURCE_MEM, pdata);
> +}
drop it useless
> +
> +struct device_d *z

Re: [PATCH v2 0/5] ARM: add support for Zynq

2013-03-19 Thread Josh Cartwright 
On Tue, Mar 19, 2013 at 02:57:58PM +0100, Steffen Trumtrar wrote:
> On Tue, Mar 19, 2013 at 07:59:27AM -0500, Josh Cartwright wrote:
> > On Tue, Mar 19, 2013 at 10:21:55AM +0100, Steffen Trumtrar wrote:
> > > Hi!
> > > 
> > > Still nothing fancy. Boots a little faster from SD and has a console.
> > > For ethernet the macb-driver works fine,
> > 
> > I've also found the macb driver works, but it does require a change to
> > prevent byteswapping during DMA, have you run into this on the ZedBoard?
> > (patch below).
> 
> I already sent the same patch :-)
> Xilinx decided to use a different reset default than Cadence uses.

So you did!  Nearly identical, too :).

> > Also, have you thought about how you'll handle the OCM mapping?  For my
> > testing, I'm using a PBL image (which contains the lowlevel init), but I
> > still need some hook into the decompressed image to remove the OCM
> > mapping from the lower address space.  This can't be done during the
> > execution of the PBL image, since it's running from OCM.
> > 
> > As far as I could tell, there was no good way to hook in early to the
> > decompressed image.
> > 
> > I ran into this trying to boot the 14.4 release uImage, since it has a
> > load address of 0x8000, and spans the 'hole' at 0x3 configured out
> > of BootROM to be 'Reserved' (writes to here trigger a Data Abort).
> > 
> 
> You also need that for the mainline kernel. Or it won't even uncompress.

I haven't yet got to the point that I can boot a kernel, but I just got
to the point where it will at least decompress last night.

> > > but needs to be "freed" from its at91 heritage (meaning: the struct
> > > at91_ether_platform_data should be renamed first and defined someplace
> > > else than a board.h)
> > 
> > I'm assuming you've done this, but if not, I've made this change in my
> > tree.  For what it's worth, I went with 'struct macb_platform_data' and
> > moved it into include/platform_data/macb.h.
> > 
> 
> Actually, I haven't. If you have a series that renames tree-wide please
> post that.

Okay, will do.

   Josh

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Re: [PATCH v2 0/5] ARM: add support for Zynq

2013-03-19 Thread Steffen Trumtrar 
On Tue, Mar 19, 2013 at 07:59:27AM -0500, Josh Cartwright wrote:
> On Tue, Mar 19, 2013 at 10:21:55AM +0100, Steffen Trumtrar wrote:
> > Hi!
> > 
> > Still nothing fancy. Boots a little faster from SD and has a console.
> > For ethernet the macb-driver works fine,
> 
> I've also found the macb driver works, but it does require a change to
> prevent byteswapping during DMA, have you run into this on the ZedBoard?
> (patch below).

I already sent the same patch :-)
Xilinx decided to use a different reset default than Cadence uses.

> 
> Also, have you thought about how you'll handle the OCM mapping?  For my
> testing, I'm using a PBL image (which contains the lowlevel init), but I
> still need some hook into the decompressed image to remove the OCM
> mapping from the lower address space.  This can't be done during the
> execution of the PBL image, since it's running from OCM.
> 
> As far as I could tell, there was no good way to hook in early to the
> decompressed image.
> 
> I ran into this trying to boot the 14.4 release uImage, since it has a
> load address of 0x8000, and spans the 'hole' at 0x3 configured out
> of BootROM to be 'Reserved' (writes to here trigger a Data Abort).
> 

You also need that for the mainline kernel. Or it won't even uncompress.


> > but needs to be "freed" from its at91 heritage (meaning: the struct
> > at91_ether_platform_data should be renamed first and defined someplace
> > else than a board.h)
> 
> I'm assuming you've done this, but if not, I've made this change in my
> tree.  For what it's worth, I went with 'struct macb_platform_data' and
> moved it into include/platform_data/macb.h.
> 

Actually, I haven't. If you have a series that renames tree-wide please
post that.

> >
> > Changelog:
> > - addressed all comments by Sascha and Josh
> >   (some uart stuff, defines, endianess, ...)
> > - squashed a little
> > 
> > Regards,
> > Steffen
> 
> -- 8< --
> Subject: [PATCH] macb: disable byte-order translation through DMA
> 
> Packet data already exists in memory in network byte-order.  Prevent the
> GEM from performing endianness translation through DMA.
> 
> Signed-off-by: Josh Cartwright 
> ---
>  drivers/net/macb.c | 1 +
>  drivers/net/macb.h | 2 ++
>  2 files changed, 3 insertions(+)
> 
> diff --git a/drivers/net/macb.c b/drivers/net/macb.c
> index 14a0689..25d1b9f 100644
> --- a/drivers/net/macb.c
> +++ b/drivers/net/macb.c
> @@ -307,6 +307,7 @@ static void macb_configure_dma(struct macb_device *bp)
>   dmacfg |= GEM_BF(FBLDO, 16);
>   dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
>   dmacfg |= GEM_BIT(DDRP);
> + dmacfg &= ~GEM_BIT(ENDIAN);
>   gem_writel(bp, DMACFG, dmacfg);
>   }
>  }
> diff --git a/drivers/net/macb.h b/drivers/net/macb.h
> index cadd561..fc4d1a9 100644
> --- a/drivers/net/macb.h
> +++ b/drivers/net/macb.h
> @@ -168,6 +168,8 @@
>  /* Bitfields in DMACFG. */
>  #define GEM_FBLDO_OFFSET 0
>  #define GEM_FBLDO_SIZE   5
> +#define GEM_ENDIAN_OFFSET7
> +#define GEM_ENDIAN_SIZE  1
>  #define GEM_RXBMS_OFFSET 8
>  #define GEM_RXBMS_SIZE   2
>  #define GEM_TXPBMS_OFFSET10
> -- 
> 1.8.1.5
> 
> 

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Re: [PATCH v2 5/5] ARM: zynq: Add support for the Avnet Zedboard

2013-03-19 Thread Steffen Trumtrar 
On Tue, Mar 19, 2013 at 08:40:42AM -0500, Josh Cartwright wrote:
> On Tue, Mar 19, 2013 at 10:22:00AM +0100, Steffen Trumtrar wrote:
> > The Avnet ZedBoard is an evalboard with a Zynq-7020 based MPSoC.
> > There is also a Digilent ZedBoard, that is the same but only for
> > academic customers.
> > 
> > Signed-off-by: Steffen Trumtrar 
> > ---
> >  arch/arm/boards/avnet-zedboard/Makefile|   1 +
> >  arch/arm/boards/avnet-zedboard/board.c |  38 
> >  arch/arm/boards/avnet-zedboard/config.h|   4 +
> >  .../boards/avnet-zedboard/env/init/config-board|   7 +
> >  arch/arm/boards/avnet-zedboard/flash_header.c  |  76 +++
> >  arch/arm/boards/avnet-zedboard/lowlevel.c  | 252 
> > +
> >  arch/arm/configs/zedboard_defconfig|  45 
> >  7 files changed, 423 insertions(+)
> >  create mode 100644 arch/arm/boards/avnet-zedboard/Makefile
> >  create mode 100644 arch/arm/boards/avnet-zedboard/board.c
> >  create mode 100644 arch/arm/boards/avnet-zedboard/config.h
> >  create mode 100644 arch/arm/boards/avnet-zedboard/env/init/config-board
> >  create mode 100644 arch/arm/boards/avnet-zedboard/flash_header.c
> >  create mode 100644 arch/arm/boards/avnet-zedboard/lowlevel.c
> >  create mode 100644 arch/arm/configs/zedboard_defconfig
> > 
> > diff --git a/arch/arm/boards/avnet-zedboard/Makefile 
> > b/arch/arm/boards/avnet-zedboard/Makefile
> > new file mode 100644
> > index 000..5c05544
> > --- /dev/null
> > +++ b/arch/arm/boards/avnet-zedboard/Makefile
> > @@ -0,0 +1 @@
> > +obj-y += board.o lowlevel.o flash_header.o
> 
> Should lowlevel.o and flash_header.o only be built into the PBL image?
> 

I didn't get around to using PBL. But, yes.

> [..]
> > diff --git a/arch/arm/boards/avnet-zedboard/flash_header.c 
> > b/arch/arm/boards/avnet-zedboard/flash_header.c
> > new file mode 100644
> > index 000..e7e2f8d
> > --- /dev/null
> > +++ b/arch/arm/boards/avnet-zedboard/flash_header.c
> > @@ -0,0 +1,76 @@
> [..]
> > +#define REG(a, v) { .addr = cpu_to_le32(a), .val = cpu_to_le32(v), }
> > +
> > +struct zynq_reg_entry __ps7reg_entry_section reg_entry[] = {
> > +   REG(ZYNQ_SLCR_UNLOCK, 0xDF0D),
> > +   REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_CLK_621_TRUE, 0x0001),
> > +   REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_APER_CLK_CTRL, 0x01FC044D),
> > +
> > +   REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CTRL, 0x00028008),
> > +   REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CFG, 0x000FA220),
> > +   REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CTRL, 0x00028010),
> > +   REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CTRL, 0x00028011),
> > +   REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CTRL, 0x00028010),
> > +   REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CTRL, 0x00028000),
> > +
> > +   REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_IO_PLL_CTRL, 0x0001E008),
> > +   REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_IO_PLL_CFG, 0x001452C0),
> > +   REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_IO_PLL_CTRL, 0x0001E010),
> > +   REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_IO_PLL_CTRL, 0x0001E011),
> > +   REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_IO_PLL_CTRL, 0x0001E010),
> > +   REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_IO_PLL_CTRL, 0x0001E000),
> > +
> > +   REG(0xf8000150, 0x0a03),
> > +
> > +   /* stop */
> > +   REG(0x, 0x),
> > +};
> > +
> [..]
> > diff --git a/arch/arm/boards/avnet-zedboard/lowlevel.c 
> > b/arch/arm/boards/avnet-zedboard/lowlevel.c
> > new file mode 100644
> > index 000..b50886e
> > --- /dev/null
> > +++ b/arch/arm/boards/avnet-zedboard/lowlevel.c
> [..]
> > +void __naked barebox_arm_reset_vector(void)
> > +{
> > +   /* open sesame */
> > +   writel(0xDF0D, ZYNQ_SLCR_UNLOCK);
> > +
> > +   /* turn on LD9 */
> > +   writel(0x0200, 0xF800071C);
> > +   writel(0x0080, 0xE000A204);
> > +   writel(0x0080, 0xE000A000);
> > +
> > +   /* ps7_clock_init_data */
> > +   writel(0x1F000200, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_CLK_CTRL);
> > +   writel(0x00F00701, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_DCI_CLK_CTRL);
> > +   writel(0x2803, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_UART_CLK_CTRL);
> > +   writel(0x0A03, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_DBG_CLK_CTRL);
> > +   writel(0x0501, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_PCAP_CLK_CTRL);
> > +   writel(0x, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_TOPSW_CLK_CTRL);
> > +   writel(0x00100A00, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_FPGA0_CLK_CTRL);
> > +   writel(0x00100700, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_FPGA1_CLK_CTRL);
> > +   writel(0x00101400, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_FPGA2_CLK_CTRL);
> > +   writel(0x00101400, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_FPGA3_CLK_CTRL);
> > +   /* 6:2:1 mode */
> > +   writel(0x0001, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_CLK_621_TRUE);
> > +   writel(0x01FC044D, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_APER_CLK_CTRL);
> > +
> > +   /* configure the PLLs */
> > +   /* ARM PLL */
> > +   writel(0x00028008, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CTRL);
> > +   writel(0x000FA220, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CFG);
> > +   writel(0x00028010, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CTRL);
> > +

Re: [PATCH v2 3/5] ARM: zynq: add clk support for zynq7000

2013-03-19 Thread Josh Cartwright 
On Tue, Mar 19, 2013 at 02:35:33PM +0100, Steffen Trumtrar wrote:
> On Tue, Mar 19, 2013 at 08:29:54AM -0500, Josh Cartwright wrote:
> > On Tue, Mar 19, 2013 at 10:21:58AM +0100, Steffen Trumtrar wrote:
> > > This adds support for the clocktree on zynq7000 SoCs.
> > > The patch is based on clocks.c from the larger patch
> > >   ARM: zynq: add suppport for Zynq 7000 SoC
> > > by Josh Cartwright.
> > > 
> > > The driver in that patch is converted to a platform_driver and code to
> > > enable plls was added.
> > > 
> > > Signed-off-by: Steffen Trumtrar 
> > > ---
> > [..]
> > > +
> > > +static int zynq_clock_probe(struct device_d *dev)
> > > +{
> > > + void __iomem *slcr_base;
> > > + unsigned long ps_clk_rate = 3330;
> > 
> > My version of the patchset had this ^ configurable, since it's possible
> > a different osc could be used on the board.  Any reason why you've
> > hardcoded this instead?
> > 
> 
> Hm, not really any good reason. But the plan is to get this from the
> devicetree instead. I didn't get around to actually doing that.
> Do your boards have another osc or would a hardcoded value suffice for
> the moment?

I agree that we should be leveraging the device tree here, so maybe it's
worth dropping until we get sorted out.  I'm fine with a hardcoded value
for now.

   Josh

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Re: [PATCH v2 3/5] ARM: zynq: add clk support for zynq7000

2013-03-19 Thread Steffen Trumtrar 
On Tue, Mar 19, 2013 at 08:29:54AM -0500, Josh Cartwright wrote:
> On Tue, Mar 19, 2013 at 10:21:58AM +0100, Steffen Trumtrar wrote:
> > This adds support for the clocktree on zynq7000 SoCs.
> > The patch is based on clocks.c from the larger patch
> > ARM: zynq: add suppport for Zynq 7000 SoC
> > by Josh Cartwright.
> > 
> > The driver in that patch is converted to a platform_driver and code to
> > enable plls was added.
> > 
> > Signed-off-by: Steffen Trumtrar 
> > ---
> [..]
> > +
> > +static int zynq_clock_probe(struct device_d *dev)
> > +{
> > +   void __iomem *slcr_base;
> > +   unsigned long ps_clk_rate = 3330;
> 
> My version of the patchset had this ^ configurable, since it's possible
> a different osc could be used on the board.  Any reason why you've
> hardcoded this instead?
> 

Hm, not really any good reason. But the plan is to get this from the
devicetree instead. I didn't get around to actually doing that.
Do your boards have another osc or would a hardcoded value suffice for
the moment?

str

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Re: [PATCH v2 5/5] ARM: zynq: Add support for the Avnet Zedboard

2013-03-19 Thread Josh Cartwright 
On Tue, Mar 19, 2013 at 10:22:00AM +0100, Steffen Trumtrar wrote:
> The Avnet ZedBoard is an evalboard with a Zynq-7020 based MPSoC.
> There is also a Digilent ZedBoard, that is the same but only for
> academic customers.
> 
> Signed-off-by: Steffen Trumtrar 
> ---
>  arch/arm/boards/avnet-zedboard/Makefile|   1 +
>  arch/arm/boards/avnet-zedboard/board.c |  38 
>  arch/arm/boards/avnet-zedboard/config.h|   4 +
>  .../boards/avnet-zedboard/env/init/config-board|   7 +
>  arch/arm/boards/avnet-zedboard/flash_header.c  |  76 +++
>  arch/arm/boards/avnet-zedboard/lowlevel.c  | 252 
> +
>  arch/arm/configs/zedboard_defconfig|  45 
>  7 files changed, 423 insertions(+)
>  create mode 100644 arch/arm/boards/avnet-zedboard/Makefile
>  create mode 100644 arch/arm/boards/avnet-zedboard/board.c
>  create mode 100644 arch/arm/boards/avnet-zedboard/config.h
>  create mode 100644 arch/arm/boards/avnet-zedboard/env/init/config-board
>  create mode 100644 arch/arm/boards/avnet-zedboard/flash_header.c
>  create mode 100644 arch/arm/boards/avnet-zedboard/lowlevel.c
>  create mode 100644 arch/arm/configs/zedboard_defconfig
> 
> diff --git a/arch/arm/boards/avnet-zedboard/Makefile 
> b/arch/arm/boards/avnet-zedboard/Makefile
> new file mode 100644
> index 000..5c05544
> --- /dev/null
> +++ b/arch/arm/boards/avnet-zedboard/Makefile
> @@ -0,0 +1 @@
> +obj-y += board.o lowlevel.o flash_header.o

Should lowlevel.o and flash_header.o only be built into the PBL image?

[..]
> diff --git a/arch/arm/boards/avnet-zedboard/flash_header.c 
> b/arch/arm/boards/avnet-zedboard/flash_header.c
> new file mode 100644
> index 000..e7e2f8d
> --- /dev/null
> +++ b/arch/arm/boards/avnet-zedboard/flash_header.c
> @@ -0,0 +1,76 @@
[..]
> +#define REG(a, v) { .addr = cpu_to_le32(a), .val = cpu_to_le32(v), }
> +
> +struct zynq_reg_entry __ps7reg_entry_section reg_entry[] = {
> + REG(ZYNQ_SLCR_UNLOCK, 0xDF0D),
> + REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_CLK_621_TRUE, 0x0001),
> + REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_APER_CLK_CTRL, 0x01FC044D),
> +
> + REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CTRL, 0x00028008),
> + REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CFG, 0x000FA220),
> + REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CTRL, 0x00028010),
> + REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CTRL, 0x00028011),
> + REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CTRL, 0x00028010),
> + REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CTRL, 0x00028000),
> +
> + REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_IO_PLL_CTRL, 0x0001E008),
> + REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_IO_PLL_CFG, 0x001452C0),
> + REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_IO_PLL_CTRL, 0x0001E010),
> + REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_IO_PLL_CTRL, 0x0001E011),
> + REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_IO_PLL_CTRL, 0x0001E010),
> + REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_IO_PLL_CTRL, 0x0001E000),
> +
> + REG(0xf8000150, 0x0a03),
> +
> + /* stop */
> + REG(0x, 0x),
> +};
> +
[..]
> diff --git a/arch/arm/boards/avnet-zedboard/lowlevel.c 
> b/arch/arm/boards/avnet-zedboard/lowlevel.c
> new file mode 100644
> index 000..b50886e
> --- /dev/null
> +++ b/arch/arm/boards/avnet-zedboard/lowlevel.c
[..]
> +void __naked barebox_arm_reset_vector(void)
> +{
> + /* open sesame */
> + writel(0xDF0D, ZYNQ_SLCR_UNLOCK);
> +
> + /* turn on LD9 */
> + writel(0x0200, 0xF800071C);
> + writel(0x0080, 0xE000A204);
> + writel(0x0080, 0xE000A000);
> +
> + /* ps7_clock_init_data */
> + writel(0x1F000200, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_CLK_CTRL);
> + writel(0x00F00701, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_DCI_CLK_CTRL);
> + writel(0x2803, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_UART_CLK_CTRL);
> + writel(0x0A03, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_DBG_CLK_CTRL);
> + writel(0x0501, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_PCAP_CLK_CTRL);
> + writel(0x, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_TOPSW_CLK_CTRL);
> + writel(0x00100A00, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_FPGA0_CLK_CTRL);
> + writel(0x00100700, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_FPGA1_CLK_CTRL);
> + writel(0x00101400, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_FPGA2_CLK_CTRL);
> + writel(0x00101400, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_FPGA3_CLK_CTRL);
> + /* 6:2:1 mode */
> + writel(0x0001, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_CLK_621_TRUE);
> + writel(0x01FC044D, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_APER_CLK_CTRL);
> +
> + /* configure the PLLs */
> + /* ARM PLL */
> + writel(0x00028008, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CTRL);
> + writel(0x000FA220, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CFG);
> + writel(0x00028010, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CTRL);
> + writel(0x00028011, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CTRL);
> + writel(0x00028010, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CTRL);

Any particular reason why you are configuring the ARM and IO PLLs twice?
(once in the ps7_reg section in th

Re: [PATCH v2 2/5] ARM: zynq: Add new architecture zynq

2013-03-19 Thread Steffen Trumtrar 
On Tue, Mar 19, 2013 at 08:18:02AM -0500, Josh Cartwright wrote:
> On Tue, Mar 19, 2013 at 10:21:57AM +0100, Steffen Trumtrar wrote:
> > Add basic support for the Xilinx Zynq-7000 EPP architecture.
> > The Zynq-7000 is an embedded processing platform that combines a Cortex A9
> > dualcore MPSoC with an Artix-7 FPGA.
> > 
> > Signed-off-by: Steffen Trumtrar 
> > ---
> [..]
> > diff --git a/arch/arm/mach-zynq/include/mach/zynq-flash-header.h 
> > b/arch/arm/mach-zynq/include/mach/zynq-flash-header.h
> > new file mode 100644
> > index 000..a0251cb
> > --- /dev/null
> > +++ b/arch/arm/mach-zynq/include/mach/zynq-flash-header.h
> > @@ -0,0 +1,40 @@
> > +#ifndef __MACH_FLASH_HEADER_H
> > +#define __MACH_FLASH_HEADER_H
> > +
> > +#include 
> > +
> > +#define __flash_header_start   __section(.flash_header_start)
> > +
> > +#define __flash_header_section __section(.flash_header_0x0)
> > +#define __ps7reg_entry_section __section(.ps7reg_entry_0x0A0)
> > +#define __image_len_section__section(.image_len_0x08c0)
> > +#define FLASH_HEADER_OFFSET0x0
> > +#define IMAGE_OFFSET   0x8c0
> > +
> > +#define DEST_BASE  0x8c0
> > +#define FLASH_HEADER_BASE  (DEST_BASE + FLASH_HEADER_OFFSET)
> > +
> > +struct zynq_reg_entry {
> > +   __le32 addr;
> > +   __le32 val;
> > +};
> > +
> > +#define WIDTH_DETECTION_MAGIC  0xAA995566
> > +#define IMAGE_IDENTIFICATION   0x584C4E58  /* "XLNX" */
> > +
> > +struct zynq_flash_header {
> > +   uint32_t width_det;
> > +   uint32_t image_id;
> > +   uint32_t enc_stat;
> > +   uint32_t user;
> > +   uint32_t flash_offset;
> > +   uint32_t length;
> > +   uint32_t res0;
> > +   uint32_t start_of_exec;
> > +   uint32_t total_len;
> > +   uint32_t res1;
> > +   uint32_t checksum;
> > +   uint32_t res2;
> > +};
> 
> Did you disagree with my suggestion last time around of merging the
> flash_header and ps7reg_entry sections?  At the very least, it seems
> inconsistent that the zynq_reg_entrys have type __le32, and the members
> of zynq_flash_header are uint32_t (even though they have the same
> endianness requirement).

Actually, I seem to have missed that comment.
The types should be the same. Yes. I have to fix that.

> 
> I still maintain you should move the REG macro currently in the board
> flash_header.c here.
> 

Hm, ok. I will do that.

Regards,
Steffen

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Re: [PATCH v2 3/5] ARM: zynq: add clk support for zynq7000

2013-03-19 Thread Josh Cartwright 
On Tue, Mar 19, 2013 at 10:21:58AM +0100, Steffen Trumtrar wrote:
> This adds support for the clocktree on zynq7000 SoCs.
> The patch is based on clocks.c from the larger patch
>   ARM: zynq: add suppport for Zynq 7000 SoC
> by Josh Cartwright.
> 
> The driver in that patch is converted to a platform_driver and code to
> enable plls was added.
> 
> Signed-off-by: Steffen Trumtrar 
> ---
[..]
> +
> +static int zynq_clock_probe(struct device_d *dev)
> +{
> + void __iomem *slcr_base;
> + unsigned long ps_clk_rate = 3330;

My version of the patchset had this ^ configurable, since it's possible
a different osc could be used on the board.  Any reason why you've
hardcoded this instead?

   Josh

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Re: [PATCH v2 2/5] ARM: zynq: Add new architecture zynq

2013-03-19 Thread Josh Cartwright 
On Tue, Mar 19, 2013 at 10:21:57AM +0100, Steffen Trumtrar wrote:
> Add basic support for the Xilinx Zynq-7000 EPP architecture.
> The Zynq-7000 is an embedded processing platform that combines a Cortex A9
> dualcore MPSoC with an Artix-7 FPGA.
> 
> Signed-off-by: Steffen Trumtrar 
> ---
[..]
> diff --git a/arch/arm/mach-zynq/include/mach/zynq-flash-header.h 
> b/arch/arm/mach-zynq/include/mach/zynq-flash-header.h
> new file mode 100644
> index 000..a0251cb
> --- /dev/null
> +++ b/arch/arm/mach-zynq/include/mach/zynq-flash-header.h
> @@ -0,0 +1,40 @@
> +#ifndef __MACH_FLASH_HEADER_H
> +#define __MACH_FLASH_HEADER_H
> +
> +#include 
> +
> +#define __flash_header_start __section(.flash_header_start)
> +
> +#define __flash_header_section   __section(.flash_header_0x0)
> +#define __ps7reg_entry_section   __section(.ps7reg_entry_0x0A0)
> +#define __image_len_section  __section(.image_len_0x08c0)
> +#define FLASH_HEADER_OFFSET  0x0
> +#define IMAGE_OFFSET 0x8c0
> +
> +#define DEST_BASE0x8c0
> +#define FLASH_HEADER_BASE(DEST_BASE + FLASH_HEADER_OFFSET)
> +
> +struct zynq_reg_entry {
> + __le32 addr;
> + __le32 val;
> +};
> +
> +#define WIDTH_DETECTION_MAGIC0xAA995566
> +#define IMAGE_IDENTIFICATION 0x584C4E58  /* "XLNX" */
> +
> +struct zynq_flash_header {
> + uint32_t width_det;
> + uint32_t image_id;
> + uint32_t enc_stat;
> + uint32_t user;
> + uint32_t flash_offset;
> + uint32_t length;
> + uint32_t res0;
> + uint32_t start_of_exec;
> + uint32_t total_len;
> + uint32_t res1;
> + uint32_t checksum;
> + uint32_t res2;
> +};

Did you disagree with my suggestion last time around of merging the
flash_header and ps7reg_entry sections?  At the very least, it seems
inconsistent that the zynq_reg_entrys have type __le32, and the members
of zynq_flash_header are uint32_t (even though they have the same
endianness requirement).

I still maintain you should move the REG macro currently in the board
flash_header.c here.

   Josh

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Re: [PATCH v2 2/5] ARM: zynq: Add new architecture zynq

2013-03-19 Thread Josh Cartwright 
On Tue, Mar 19, 2013 at 10:21:57AM +0100, Steffen Trumtrar wrote:
> Add basic support for the Xilinx Zynq-7000 EPP architecture.
> The Zynq-7000 is an embedded processing platform that combines a Cortex A9
> dualcore MPSoC with an Artix-7 FPGA.
> 
> Signed-off-by: Steffen Trumtrar 
[..]
> +static int zynq_init(void)
> +{
> + u32 val;
> +
> + dsb();
> + isb();
> + writel(0xDF0D, ZYNQ_SLCR_UNLOCK);
> + /* remap ocm high */
> + writel(0x000F, 0xf8000910);
> + /* mpcore.filtering_start_address */
> + writel(0x, 0xf8f00040);
> + /* mpcore.filtering_end_address */
> + writel(0xffe0, 0xf8f00044);
> + val = readl(0xf8f0);
> + val |= 0x2;
> + writel(val, 0xf8f0);
> + dmb();

Doh!  I should have read this before replying!  This is what I was
looking for!

I think this will work nicely.

Josh

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Re: [PATCH v2 0/5] ARM: add support for Zynq

2013-03-19 Thread Josh Cartwright 
On Tue, Mar 19, 2013 at 10:21:55AM +0100, Steffen Trumtrar wrote:
> Hi!
> 
> Still nothing fancy. Boots a little faster from SD and has a console.
> For ethernet the macb-driver works fine,

I've also found the macb driver works, but it does require a change to
prevent byteswapping during DMA, have you run into this on the ZedBoard?
(patch below).

Also, have you thought about how you'll handle the OCM mapping?  For my
testing, I'm using a PBL image (which contains the lowlevel init), but I
still need some hook into the decompressed image to remove the OCM
mapping from the lower address space.  This can't be done during the
execution of the PBL image, since it's running from OCM.

As far as I could tell, there was no good way to hook in early to the
decompressed image.

I ran into this trying to boot the 14.4 release uImage, since it has a
load address of 0x8000, and spans the 'hole' at 0x3 configured out
of BootROM to be 'Reserved' (writes to here trigger a Data Abort).

> but needs to be "freed" from its at91 heritage (meaning: the struct
> at91_ether_platform_data should be renamed first and defined someplace
> else than a board.h)

I'm assuming you've done this, but if not, I've made this change in my
tree.  For what it's worth, I went with 'struct macb_platform_data' and
moved it into include/platform_data/macb.h.

>
> Changelog:
>   - addressed all comments by Sascha and Josh
> (some uart stuff, defines, endianess, ...)
>   - squashed a little
> 
> Regards,
> Steffen

-- 8< --
Subject: [PATCH] macb: disable byte-order translation through DMA

Packet data already exists in memory in network byte-order.  Prevent the
GEM from performing endianness translation through DMA.

Signed-off-by: Josh Cartwright 
---
 drivers/net/macb.c | 1 +
 drivers/net/macb.h | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 14a0689..25d1b9f 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -307,6 +307,7 @@ static void macb_configure_dma(struct macb_device *bp)
dmacfg |= GEM_BF(FBLDO, 16);
dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
dmacfg |= GEM_BIT(DDRP);
+   dmacfg &= ~GEM_BIT(ENDIAN);
gem_writel(bp, DMACFG, dmacfg);
}
 }
diff --git a/drivers/net/macb.h b/drivers/net/macb.h
index cadd561..fc4d1a9 100644
--- a/drivers/net/macb.h
+++ b/drivers/net/macb.h
@@ -168,6 +168,8 @@
 /* Bitfields in DMACFG. */
 #define GEM_FBLDO_OFFSET   0
 #define GEM_FBLDO_SIZE 5
+#define GEM_ENDIAN_OFFSET  7
+#define GEM_ENDIAN_SIZE1
 #define GEM_RXBMS_OFFSET   8
 #define GEM_RXBMS_SIZE 2
 #define GEM_TXPBMS_OFFSET  10
-- 
1.8.1.5


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Re: [PATCH] clk: Add is_enabled callback

2013-03-19 Thread Sascha Hauer 
On Sat, Mar 16, 2013 at 10:58:54AM +0400, Alexander Shiyan wrote:
> > This allows us to better detect whether a clk is enabled or not.
> > 
> > - If we can ask a clk, ask it. If it's enabled, go on and ask parents
> > - If we can't ask it, but it can be enabled, depend on the enable_count.
> >   if it's positive, go on and ask parents
> > - If we can't ask it and it cannot be enabled, assume it is enabled
> >   and ask parents.
> > 
> > This makes the CLK_ALWAYS_ENABLED unnecessary, since the fixed clk now
> > always returns 1 in its is_enabled callback.
> > 
> > Signed-off-by: Sascha Hauer 
> > ---
> >  drivers/clk/clk-fixed.c |  2 +-
> >  drivers/clk/clk-gate.c  | 14 
> >  drivers/clk/clk.c   | 61 
> > +
> >  include/linux/clk.h |  4 ++--
> >  4 files changed, 63 insertions(+), 18 deletions(-)
> > 
> > diff --git a/drivers/clk/clk-fixed.c b/drivers/clk/clk-fixed.c
> > +
> > +   if (val & (1 << g->shift))
> > +   return 1;
> > +   else
> > +   return 0;
> > +}
> 
> Make it simper, like:
> return !!(readl(g->reg) & (1 << g->shift));
> 

Hm, do you find this simpler to read? The compiler will most likely
produce the same result.

> > unsigned intdiv;
> > @@ -202,6 +200,8 @@ struct clk *clk_mux(const char *name, void __iomem *reg,
> >  struct clk *clk_gate(const char *name, const char *parent, void __iomem 
> > *reg,
> > u8 shift);
> >  
> > +int clk_is_enabled_always(struct clk *clk);
> 
> Used only in clk-fixed.c, is it really need to be declared global?

No, you're right. Will make this a local function in clk-fixed.c

Sascha

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[PATCH v2 0/5] ARM: add support for Zynq

2013-03-19 Thread Steffen Trumtrar 
Hi!

Still nothing fancy. Boots a little faster from SD and has a console.
For ethernet the macb-driver works fine, but needs to be "freed" from its
at91 heritage (meaning: the struct at91_ether_platform_data should be
renamed first and defined someplace else than a board.h)

Changelog:
- addressed all comments by Sascha and Josh
  (some uart stuff, defines, endianess, ...)
- squashed a little

Regards,
Steffen


Steffen Trumtrar (5):
  serial: Add driver for Cadence UART
  ARM: zynq: Add new architecture zynq
  ARM: zynq: add clk support for zynq7000
  ARM: zynq: add zynq fsbl checksum script
  ARM: zynq: Add support for the Avnet Zedboard

 arch/arm/Kconfig   |   5 +
 arch/arm/Makefile  |   2 +
 arch/arm/boards/avnet-zedboard/Makefile|   1 +
 arch/arm/boards/avnet-zedboard/board.c |  38 ++
 arch/arm/boards/avnet-zedboard/config.h|   4 +
 .../boards/avnet-zedboard/env/init/config-board|   7 +
 arch/arm/boards/avnet-zedboard/flash_header.c  |  76 
 arch/arm/boards/avnet-zedboard/lowlevel.c  | 252 +
 arch/arm/configs/zedboard_defconfig|  45 +++
 arch/arm/mach-zynq/Kconfig |  39 ++
 arch/arm/mach-zynq/Makefile|   1 +
 arch/arm/mach-zynq/clk-zynq7000.c  | 417 +
 arch/arm/mach-zynq/devices.c   |  14 +
 arch/arm/mach-zynq/include/mach/barebox.lds.h  |   9 +
 arch/arm/mach-zynq/include/mach/clkdev.h   |   6 +
 arch/arm/mach-zynq/include/mach/debug_ll.h |  37 ++
 arch/arm/mach-zynq/include/mach/devices.h  |  13 +
 .../arm/mach-zynq/include/mach/zynq-flash-header.h |  40 ++
 arch/arm/mach-zynq/include/mach/zynq7000-regs.h| 132 +++
 arch/arm/mach-zynq/zynq.c  |  56 +++
 drivers/serial/Kconfig |   4 +
 drivers/serial/Makefile|   1 +
 drivers/serial/serial_cadence.c| 307 +++
 include/asm-generic/barebox.lds.h  |   3 +-
 scripts/Makefile   |   1 +
 scripts/zynq_checksum.c|  72 
 26 files changed, 1581 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boards/avnet-zedboard/Makefile
 create mode 100644 arch/arm/boards/avnet-zedboard/board.c
 create mode 100644 arch/arm/boards/avnet-zedboard/config.h
 create mode 100644 arch/arm/boards/avnet-zedboard/env/init/config-board
 create mode 100644 arch/arm/boards/avnet-zedboard/flash_header.c
 create mode 100644 arch/arm/boards/avnet-zedboard/lowlevel.c
 create mode 100644 arch/arm/configs/zedboard_defconfig
 create mode 100644 arch/arm/mach-zynq/Kconfig
 create mode 100644 arch/arm/mach-zynq/Makefile
 create mode 100644 arch/arm/mach-zynq/clk-zynq7000.c
 create mode 100644 arch/arm/mach-zynq/devices.c
 create mode 100644 arch/arm/mach-zynq/include/mach/barebox.lds.h
 create mode 100644 arch/arm/mach-zynq/include/mach/clkdev.h
 create mode 100644 arch/arm/mach-zynq/include/mach/debug_ll.h
 create mode 100644 arch/arm/mach-zynq/include/mach/devices.h
 create mode 100644 arch/arm/mach-zynq/include/mach/zynq-flash-header.h
 create mode 100644 arch/arm/mach-zynq/include/mach/zynq7000-regs.h
 create mode 100644 arch/arm/mach-zynq/zynq.c
 create mode 100644 drivers/serial/serial_cadence.c
 create mode 100644 scripts/zynq_checksum.c

-- 
1.8.2.rc2


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[PATCH v2 1/5] serial: Add driver for Cadence UART

2013-03-19 Thread Steffen Trumtrar 
Support for Cadence UART core.

Signed-off-by: Steffen Trumtrar 
---
 drivers/serial/Kconfig  |   4 +
 drivers/serial/Makefile |   1 +
 drivers/serial/serial_cadence.c | 307 
 3 files changed, 312 insertions(+)
 create mode 100644 drivers/serial/serial_cadence.c

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index f61d670..a51510e 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -113,4 +113,8 @@ config DRIVER_SERIAL_OMAP4_USBBOOT
help
  Enable this to get console support over the usb bus used to boot an 
OMAP4
 
+config DRIVER_SERIAL_CADENCE
+   default n
+   bool "Cadence UART driver"
+
 endmenu
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 893e282..963a7df 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -21,3 +21,4 @@ obj-$(CONFIG_DRIVER_SERIAL_ALTERA)+= 
serial_altera.o
 obj-$(CONFIG_DRIVER_SERIAL_ALTERA_JTAG)+= serial_altera_jtag.o
 obj-$(CONFIG_DRIVER_SERIAL_PXA)+= serial_pxa.o
 obj-$(CONFIG_DRIVER_SERIAL_OMAP4_USBBOOT)  += serial_omap4_usbboot.o
+obj-$(CONFIG_DRIVER_SERIAL_CADENCE)+= serial_cadence.o
diff --git a/drivers/serial/serial_cadence.c b/drivers/serial/serial_cadence.c
new file mode 100644
index 000..c29c391
--- /dev/null
+++ b/drivers/serial/serial_cadence.c
@@ -0,0 +1,307 @@
+/*
+ * (c) 2012 Steffen Trumtrar 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define CADENCE_UART_CONTROL   0x00
+#define CADENCE_UART_MODE  0x04
+#define CADENCE_UART_BAUD_GEN  0x18
+#define CADENCE_UART_CHANNEL_STS   0x2C
+#define CADENCE_UART_RXTXFIFO  0x30
+#define CADENCE_UART_BAUD_DIV  0x34
+
+#define CADENCE_CTRL_RXRES (1 << 0)
+#define CADENCE_CTRL_TXRES (1 << 1)
+#define CADENCE_CTRL_RXEN  (1 << 2)
+#define CADENCE_CTRL_RXDIS (1 << 3)
+#define CADENCE_CTRL_TXEN  (1 << 4)
+#define CADENCE_CTRL_TXDIS (1 << 5)
+#define CADENCE_CTRL_RSTTO (1 << 6)
+#define CADENCE_CTRL_STTBRK(1 << 7)
+#define CADENCE_CTRL_STPBRK(1 << 8)
+
+#define CADENCE_MODE_CLK_REF   (0 << 0)
+#define CADENCE_MODE_CLK_REF_DIV   (1 << 0)
+#define CADENCE_MODE_CHRL_6(3 << 1)
+#define CADENCE_MODE_CHRL_7(2 << 1)
+#define CADENCE_MODE_CHRL_8(0 << 1)
+#define CADENCE_MODE_PAR_EVEN  (0 << 3)
+#define CADENCE_MODE_PAR_ODD   (1 << 3)
+#define CADENCE_MODE_PAR_SPACE (2 << 3)
+#define CADENCE_MODE_PAR_MARK  (3 << 3)
+#define CADENCE_MODE_PAR_NONE  (4 << 3)
+
+#define CADENCE_STS_REMPTY (1 << 1)
+#define CADENCE_STS_RFUL   (1 << 2)
+#define CADENCE_STS_TEMPTY (1 << 3)
+#define CADENCE_STS_TFUL   (1 << 4)
+
+/*
+ * create default values for different platforms
+ */
+struct cadence_serial_devtype_data {
+   u32 ctrl;
+   u32 mode;
+};
+
+static struct cadence_serial_devtype_data cadence_r1p08_data = {
+   .ctrl = CADENCE_CTRL_RXEN | CADENCE_CTRL_TXEN,
+   .mode = CADENCE_MODE_CLK_REF | CADENCE_MODE_CHRL_8 | 
CADENCE_MODE_PAR_NONE,
+};
+
+struct cadence_serial_priv {
+   struct console_device cdev;
+   int baudrate;
+   struct notifier_block notify;
+   void __iomem *regs;
+   struct clk *clk;
+   struct cadence_serial_devtype_data *devtype;
+};
+
+static int cadence_serial_reset(struct console_device *cdev)
+{
+   struct cadence_serial_priv *priv = container_of(cdev,
+   struct cadence_serial_priv, cdev);
+
+   /* Soft-Reset Tx/Rx paths */
+   writel(CADENCE_CTRL_RXRES | CADENCE_CTRL_TXRES, priv->regs +
+   CADENCE_UART_CONTROL);
+
+   while (readl(priv->regs + CADENCE_UART_CONTROL) &
+   (CADENCE_CTRL_RXRES | CADENCE_CTRL_TXRES))
+   ;
+
+   return 0;
+}
+
+static int cadence_serial_setbaudrate(struct console_device *cdev, int 
baudrate)
+{
+   struct cadence_serial_priv *priv = container_of(cdev,
+   struct cadence_serial_priv, cdev);
+   unsigned int gen, div;
+   int calc_rate;
+   unsigned long clk;
+   int error;
+   int val;
+
+   clk = clk_get_rate(priv->clk);
+   priv->baudrate

[PATCH v2 3/5] ARM: zynq: add clk support for zynq7000

2013-03-19 Thread Steffen Trumtrar 
This adds support for the clocktree on zynq7000 SoCs.
The patch is based on clocks.c from the larger patch
ARM: zynq: add suppport for Zynq 7000 SoC
by Josh Cartwright.

The driver in that patch is converted to a platform_driver and code to
enable plls was added.

Signed-off-by: Steffen Trumtrar 
---
 arch/arm/mach-zynq/clk-zynq7000.c| 417 +++
 arch/arm/mach-zynq/include/mach/clkdev.h |   6 +
 2 files changed, 423 insertions(+)
 create mode 100644 arch/arm/mach-zynq/clk-zynq7000.c
 create mode 100644 arch/arm/mach-zynq/include/mach/clkdev.h

diff --git a/arch/arm/mach-zynq/clk-zynq7000.c 
b/arch/arm/mach-zynq/clk-zynq7000.c
new file mode 100644
index 000..1e03514
--- /dev/null
+++ b/arch/arm/mach-zynq/clk-zynq7000.c
@@ -0,0 +1,417 @@
+/*
+ * Copyright (c) 2013 Josh Cartwright 
+ * Copyright (c) 2013 Steffen Trumtrar 
+ *
+ * Based on drivers/clk-zynq.c from Linux.
+ *
+ * Copyright (c) 2012 National Instruments
+ *
+ * Josh Cartwright 
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+enum zynq_clks {
+   dummy, ps_clk, arm_pll, ddr_pll, io_pll, uart_clk, uart0, uart1,
+   cpu_clk, cpu_6x4x, cpu_3x2x, cpu_2x, cpu_1x, clks_max
+};
+
+enum zynq_pll_type {
+   ZYNQ_PLL_ARM,
+   ZYNQ_PLL_DDR,
+   ZYNQ_PLL_IO,
+};
+
+#define PLL_STATUS_ARM_PLL_LOCK(1 << 0)
+#define PLL_STATUS_DDR_PLL_LOCK(1 << 1)
+#define PLL_STATUS_IO_PLL_LOCK (1 << 2)
+#define PLL_STATUS_ARM_PLL_STABLE  (1 << 0)
+#define PLL_STATUS_DDR_PLL_STABLE  (1 << 1)
+#define PLL_STATUS_IO_PLL_STABLE   (1 << 2)
+#define PLL_CTRL_BYPASS_FORCE  (1 << 4)
+
+static struct clk *clks[clks_max];
+
+struct zynq_pll_clk {
+   struct clk  clk;
+   u32 pll_lock;
+   void __iomem*pll_ctrl;
+};
+
+#define to_zynq_pll_clk(c) container_of(c, struct zynq_pll_clk, clk)
+
+#define PLL_CTRL_FDIV(x)   (((x) >> 12) & 0x7F)
+
+static unsigned long zynq_pll_recalc_rate(struct clk *clk,
+ unsigned long parent_rate)
+{
+   struct zynq_pll_clk *pll = to_zynq_pll_clk(clk);
+   return parent_rate * PLL_CTRL_FDIV(readl(pll->pll_ctrl));
+}
+
+static int zynq_pll_enable(struct clk *clk)
+{
+   struct zynq_pll_clk *pll = to_zynq_pll_clk(clk);
+   u32 val;
+   int timeout = 1;
+
+   val = readl(pll->pll_ctrl);
+   val &= ~PLL_CTRL_BYPASS_FORCE;
+   writel(val, pll->pll_ctrl);
+
+   while (timeout--) {
+   if (readl(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_PLL_STATUS) & 
pll->pll_lock)
+   break;
+   }
+
+   if (!timeout)
+   return -ETIMEDOUT;
+
+   return 0;
+}
+
+static struct clk_ops zynq_pll_clk_ops = {
+   .recalc_rate = zynq_pll_recalc_rate,
+   .enable = zynq_pll_enable,
+};
+
+static inline struct clk *zynq_pll_clk(enum zynq_pll_type type,
+  const char *name,
+  void __iomem *pll_ctrl)
+{
+   static const char *pll_parent = "ps_clk";
+   struct zynq_pll_clk *pll;
+   int ret;
+
+   pll = xzalloc(sizeof(*pll));
+   pll->pll_ctrl   = pll_ctrl;
+   pll->clk.ops= &zynq_pll_clk_ops;
+   pll->clk.name   = name;
+   pll->clk.parent_names   = &pll_parent;
+   pll->clk.num_parents= 1;
+
+   switch(type) {
+   case ZYNQ_PLL_ARM:
+   pll->pll_lock = PLL_STATUS_ARM_PLL_LOCK;
+   break;
+   case ZYNQ_PLL_DDR:
+   pll->pll_lock = PLL_STATUS_DDR_PLL_LOCK;
+   break;
+   case ZYNQ_PLL_IO:
+   pll->pll_lock = PLL_STATUS_IO_PLL_LOCK;
+   break;
+   }
+
+   ret = clk_register(&pll->clk);
+   if (ret) {
+   free(pll);
+   return ERR_PTR(ret);
+   }
+
+   return &pll->clk;
+}
+
+struct zynq_periph_clk {
+   struct clk  clk;
+   void __iomem*clk_ctrl;
+};
+
+#define to_zynq_periph_clk(c)  container_of(c, struct zynq_periph_clk, c)
+
+static const u8 periph_clk_parent_map[] = {
+   0, 0, 1, 2
+};
+#define PERIPH_CLK_CTRL_SRC(x) (periph_clk_parent_map[((x) & 0x30) >> 4])
+#define PERIPH_CLK_CTRL_DIV(x) (((x) & 0x3F00) >> 8)
+
+static unsigned long zynq_periph_recalc_rate(struct c

[PATCH v2 5/5] ARM: zynq: Add support for the Avnet Zedboard

2013-03-19 Thread Steffen Trumtrar 
The Avnet ZedBoard is an evalboard with a Zynq-7020 based MPSoC.
There is also a Digilent ZedBoard, that is the same but only for
academic customers.

Signed-off-by: Steffen Trumtrar 
---
 arch/arm/boards/avnet-zedboard/Makefile|   1 +
 arch/arm/boards/avnet-zedboard/board.c |  38 
 arch/arm/boards/avnet-zedboard/config.h|   4 +
 .../boards/avnet-zedboard/env/init/config-board|   7 +
 arch/arm/boards/avnet-zedboard/flash_header.c  |  76 +++
 arch/arm/boards/avnet-zedboard/lowlevel.c  | 252 +
 arch/arm/configs/zedboard_defconfig|  45 
 7 files changed, 423 insertions(+)
 create mode 100644 arch/arm/boards/avnet-zedboard/Makefile
 create mode 100644 arch/arm/boards/avnet-zedboard/board.c
 create mode 100644 arch/arm/boards/avnet-zedboard/config.h
 create mode 100644 arch/arm/boards/avnet-zedboard/env/init/config-board
 create mode 100644 arch/arm/boards/avnet-zedboard/flash_header.c
 create mode 100644 arch/arm/boards/avnet-zedboard/lowlevel.c
 create mode 100644 arch/arm/configs/zedboard_defconfig

diff --git a/arch/arm/boards/avnet-zedboard/Makefile 
b/arch/arm/boards/avnet-zedboard/Makefile
new file mode 100644
index 000..5c05544
--- /dev/null
+++ b/arch/arm/boards/avnet-zedboard/Makefile
@@ -0,0 +1 @@
+obj-y += board.o lowlevel.o flash_header.o
diff --git a/arch/arm/boards/avnet-zedboard/board.c 
b/arch/arm/boards/avnet-zedboard/board.c
new file mode 100644
index 000..4e3d5a5
--- /dev/null
+++ b/arch/arm/boards/avnet-zedboard/board.c
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2013 Steffen Trumtrar 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static int zedboard_mem_init(void)
+{
+   arm_add_mem_device("ram0", 0, SZ_512M);
+
+   return 0;
+}
+mem_initcall(zedboard_mem_init);
+
+static int zedboard_console_init(void)
+{
+   zynq_add_uart1();
+
+   return 0;
+}
+console_initcall(zedboard_console_init);
diff --git a/arch/arm/boards/avnet-zedboard/config.h 
b/arch/arm/boards/avnet-zedboard/config.h
new file mode 100644
index 000..ca15136
--- /dev/null
+++ b/arch/arm/boards/avnet-zedboard/config.h
@@ -0,0 +1,4 @@
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#endif /* __CONFIG_H */
diff --git a/arch/arm/boards/avnet-zedboard/env/init/config-board 
b/arch/arm/boards/avnet-zedboard/env/init/config-board
new file mode 100644
index 000..9957653
--- /dev/null
+++ b/arch/arm/boards/avnet-zedboard/env/init/config-board
@@ -0,0 +1,7 @@
+#!/bin/sh
+
+# board defaults, do not change in running system. Change /env/config
+# instead
+
+global.hostname=ZedBoard
+global.linux.bootargs.base="console=ttyPS1,115200"
diff --git a/arch/arm/boards/avnet-zedboard/flash_header.c 
b/arch/arm/boards/avnet-zedboard/flash_header.c
new file mode 100644
index 000..e7e2f8d
--- /dev/null
+++ b/arch/arm/boards/avnet-zedboard/flash_header.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) 2012 Steffen Trumtrar 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+void __naked __flash_header_start go(void)
+{
+   __asm__ __volatile__ (
+   "b barebox_arm_reset_vector\n"
+   "1: b 1b\n"
+   "1: b 1b\n"
+   "1: b 1b\n"
+   "1: b 1b\n"
+   "1: b 1b\n"
+   "1: b 1b\n"
+   "1: b 1b\n"
+   );
+}
+
+#define REG(a, v) { .addr = cpu_to_le32(a), .val = cpu_to_le32(v), }
+
+struct zynq_reg_entry __ps7reg_entry_section reg_entry[] = {
+   REG(ZYNQ_SLCR_UNLOCK, 0xDF0D),
+   REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_CLK_621_TRUE, 0x0001),
+   REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_APER_CLK_CTRL, 0x01FC044D),
+
+   REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CTRL, 0x00028008),
+   REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CFG, 0x000FA220),
+   REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CTRL, 0x00028010),
+   REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CTRL

[PATCH v2 4/5] ARM: zynq: add zynq fsbl checksum script

2013-03-19 Thread Steffen Trumtrar 
The bootrom only reads an image if the correct checksum is present in the
header. The calculation is pretty simple:
sum over all words from 0x20 to 0x44
Two of this words are the image length. That is why the checksum can not be
calculated until barebox_image_size is known.
The easiest solution is a program that has to be run after make.
Maybe this can be replaced with some linker-fu.

Signed-off-by: Steffen Trumtrar 
---
 scripts/Makefile|  1 +
 scripts/zynq_checksum.c | 72 +
 2 files changed, 73 insertions(+)
 create mode 100644 scripts/zynq_checksum.c

diff --git a/scripts/Makefile b/scripts/Makefile
index 08b325c..41c892e 100644
--- a/scripts/Makefile
+++ b/scripts/Makefile
@@ -12,6 +12,7 @@ hostprogs-$(CONFIG_ARCH_NETX)+= gen_netx_image
 hostprogs-$(CONFIG_ARCH_OMAP)+= omap_signGP mk-am35xx-spi-image
 hostprogs-$(CONFIG_ARCH_S5PCxx)  += s5p_cksum
 hostprogs-$(CONFIG_ARCH_DAVINCI) += mkublheader
+hostprogs-$(CONFIG_ARCH_ZYNQ)   += zynq_checksum
 
 HOSTLOADLIBES_omap4_usbboot = -lpthread
 omap4_usbboot-objs   := usb_linux.o omap4_usbboot.o
diff --git a/scripts/zynq_checksum.c b/scripts/zynq_checksum.c
new file mode 100644
index 000..f32db61
--- /dev/null
+++ b/scripts/zynq_checksum.c
@@ -0,0 +1,72 @@
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static void usage(char *name)
+{
+   printf("Usage: %s barebox.bin \n", name);
+}
+
+int main(int argc, char *argv[])
+{
+   FILE *ifile, *ofile;
+   unsigned int *buf;
+   const char *infile;
+   const char *outfile;
+   struct stat st;
+   unsigned int i;
+   unsigned long sum = 0;
+
+   if (argc != 3) {
+   usage(argv[0]);
+   exit(1);
+   }
+
+   infile = argv[1];
+   outfile = argv[2];
+
+   if (stat(infile, &st) == -1) {
+   perror("stat");
+   exit(EXIT_FAILURE);
+   }
+
+   buf = malloc(sizeof(*buf) * st.st_size);
+   if (!buf) {
+   fprintf(stderr, "Unable to allocate buffer\n");
+   return -1;
+   }
+   ifile = fopen(infile, "rb");
+   if (!ifile) {
+   fprintf(stderr, "Cannot open %s for reading\n",
+   infile);
+   free(buf);
+   exit(EXIT_FAILURE);
+   }
+   ofile = fopen(outfile, "wb");
+   if (!ofile) {
+   fprintf(stderr, "Cannot open %s for writing\n",
+   outfile);
+   fclose(ifile);
+   free(buf);
+   exit(EXIT_FAILURE);
+   }
+
+   fread(buf, 4, st.st_size, ifile);
+
+   for (i = 0x8; i < 0x12; i++)
+   sum += htole32(buf[i]);
+
+   sum = ~sum;
+   buf[i] = sum;
+
+   fwrite(buf, st.st_size / 4, 4, ofile);
+
+   fclose(ofile);
+   fclose(ifile);
+   free(buf);
+
+   return 0;
+}
-- 
1.8.2.rc2


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[PATCH v2 2/5] ARM: zynq: Add new architecture zynq

2013-03-19 Thread Steffen Trumtrar 
Add basic support for the Xilinx Zynq-7000 EPP architecture.
The Zynq-7000 is an embedded processing platform that combines a Cortex A9
dualcore MPSoC with an Artix-7 FPGA.

Signed-off-by: Steffen Trumtrar 
---
 arch/arm/Kconfig   |   5 +
 arch/arm/Makefile  |   2 +
 arch/arm/mach-zynq/Kconfig |  39 ++
 arch/arm/mach-zynq/Makefile|   1 +
 arch/arm/mach-zynq/devices.c   |  14 +++
 arch/arm/mach-zynq/include/mach/barebox.lds.h  |   9 ++
 arch/arm/mach-zynq/include/mach/debug_ll.h |  37 ++
 arch/arm/mach-zynq/include/mach/devices.h  |  13 ++
 .../arm/mach-zynq/include/mach/zynq-flash-header.h |  40 +++
 arch/arm/mach-zynq/include/mach/zynq7000-regs.h| 132 +
 arch/arm/mach-zynq/zynq.c  |  56 +
 include/asm-generic/barebox.lds.h  |   3 +-
 12 files changed, 350 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-zynq/Kconfig
 create mode 100644 arch/arm/mach-zynq/Makefile
 create mode 100644 arch/arm/mach-zynq/devices.c
 create mode 100644 arch/arm/mach-zynq/include/mach/barebox.lds.h
 create mode 100644 arch/arm/mach-zynq/include/mach/debug_ll.h
 create mode 100644 arch/arm/mach-zynq/include/mach/devices.h
 create mode 100644 arch/arm/mach-zynq/include/mach/zynq-flash-header.h
 create mode 100644 arch/arm/mach-zynq/include/mach/zynq7000-regs.h
 create mode 100644 arch/arm/mach-zynq/zynq.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 28332ec..8431fa8 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -110,6 +110,10 @@ config ARCH_TEGRA
select CPU_ARM926T
select HAS_DEBUG_LL
 
+config ARCH_ZYNQ
+   bool "Xilinx Zynq-based boards"
+   select HAS_DEBUG_LL
+
 endchoice
 
 source arch/arm/cpu/Kconfig
@@ -126,6 +130,7 @@ source arch/arm/mach-pxa/Kconfig
 source arch/arm/mach-samsung/Kconfig
 source arch/arm/mach-versatile/Kconfig
 source arch/arm/mach-tegra/Kconfig
+source arch/arm/mach-zynq/Kconfig
 
 config ARM_ASM_UNIFIED
bool
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index fcb2969..ceb45dc 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -64,6 +64,7 @@ machine-$(CONFIG_ARCH_PXA):= pxa
 machine-$(CONFIG_ARCH_SAMSUNG) := samsung
 machine-$(CONFIG_ARCH_VERSATILE)   := versatile
 machine-$(CONFIG_ARCH_TEGRA)   := tegra
+machine-$(CONFIG_ARCH_ZYNQ):= zynq
 
 # Board directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
@@ -157,6 +158,7 @@ board-$(CONFIG_MACH_SABRELITE)  := 
freescale-mx6-sabrelite
 board-$(CONFIG_MACH_TX53)  := karo-tx53
 board-$(CONFIG_MACH_GUF_VINCELL)   := guf-vincell
 board-$(CONFIG_MACH_EFIKA_MX_SMARTBOOK):= efika-mx-smartbook
+board-$(CONFIG_MACH_ZEDBOARD)  := avnet-zedboard
 
 machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
 
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
new file mode 100644
index 000..3965ad4
--- /dev/null
+++ b/arch/arm/mach-zynq/Kconfig
@@ -0,0 +1,39 @@
+if ARCH_ZYNQ
+
+config ARCH_TEXT_BASE
+   hex
+   default 0x1ff0 if MACH_ZEDBOARD
+
+config ZYNQ_DEBUG_LL_UART_BASE
+   hex
+   default 0xe0001000 if MACH_ZEDBOARD
+
+config BOARDINFO
+   default "ZedBoard" if MACH_ZEDBOARD
+
+choice
+   prompt "Xilinx Zynq type board"
+
+config ARCH_ZYNQ7000
+   bool "Zynq-7000"
+   select CPU_V7
+   select DRIVER_SERIAL_CADENCE
+   select CLKDEV_LOOKUP
+   select COMMON_CLK
+   select ARM_SMP_TWD
+
+endchoice
+
+if ARCH_ZYNQ7000
+
+choice
+   prompt "Zynq-7000 Board Type"
+
+config MACH_ZEDBOARD
+   bool "Avnet Zynq-7000 ZedBoard"
+   select MACH_HAS_LOWLEVEL_INIT
+
+endchoice
+endif
+
+endif
diff --git a/arch/arm/mach-zynq/Makefile b/arch/arm/mach-zynq/Makefile
new file mode 100644
index 000..459c957
--- /dev/null
+++ b/arch/arm/mach-zynq/Makefile
@@ -0,0 +1 @@
+obj-y += zynq.o devices.o clk-zynq7000.o
diff --git a/arch/arm/mach-zynq/devices.c b/arch/arm/mach-zynq/devices.c
new file mode 100644
index 000..2bb3c92
--- /dev/null
+++ b/arch/arm/mach-zynq/devices.c
@@ -0,0 +1,14 @@
+#include 
+#include 
+#include 
+
+static inline struct device_d *zynq_add_device(char *name, int id, void *base, 
int size, void *pdata)
+{
+   return add_generic_device(name, id, NULL, (resource_size_t)base, size,
+ IORESOURCE_MEM, pdata);
+}
+
+struct device_d *zynq_add_uart(void *base, int id)
+{
+   return zynq_add_device("cadence-uart", id, base, 0x1000, NULL);
+}
diff --git a/arch/arm/mach-zynq/include/mach/barebox.lds.h 
b/arch/arm/mach-zynq/include/mach/barebox.lds.h
new file mode 100644
index 000..674a4ac
--- /dev/null
+++ b/arch/arm/mach-zynq/include/mach/barebox.lds.h
@@ -0,0 +1,9 @@
+#define PR