Re: [PATCH urgent] ARM: fix the memset fix
Hi Nico, ignore this one, you were not meant to be on Cc. Sascha On Thu, May 23, 2013 at 08:31:15AM +0200, Sascha Hauer wrote: From: Nicolas Pitre nicolas.pi...@linaro.org From Kernel commit 418df63a ARM: 7670/1: fix the memset fix | Commit 455bd4c430b0 (ARM: 7668/1: fix memset-related crashes caused by | recent GCC (4.7.2) optimizations) attempted to fix a compliance issue | with the memset return value. However the memset itself became broken | by that patch for misaligned pointers. | | This fixes the above by branching over the entry code from the | misaligned fixup code to avoid reloading the original pointer. | | Also, because the function entry alignment is wrong in the Thumb mode | compilation, that fixup code is moved to the end. | | While at it, the entry instructions are slightly reworked to help dual | issue pipelines. | | Signed-off-by: Nicolas Pitre n...@linaro.org | Tested-by: Alexander Holler hol...@ahsoftware.de | Signed-off-by: Russell King rmk+ker...@arm.linux.org.uk Signed-off-by: Sascha Hauer s.ha...@pengutronix.de --- This was reported one of our customers. One effect was that the md5sum implementation produced wrong results. arch/arm/lib/memset.S | 33 + 1 file changed, 13 insertions(+), 20 deletions(-) diff --git a/arch/arm/lib/memset.S b/arch/arm/lib/memset.S index 5e35d7f..c4d2672 100644 --- a/arch/arm/lib/memset.S +++ b/arch/arm/lib/memset.S @@ -14,31 +14,15 @@ .text .align 5 - .word 0 - -1: subsr2, r2, #4 @ 1 do we have enough - blt 5f @ 1 bytes to align with? - cmp r3, #2 @ 1 - strltb r1, [ip], #1@ 1 - strleb r1, [ip], #1@ 1 - strbr1, [ip], #1@ 1 - add r2, r2, r3 @ 1 (r2 = r2 - (4 - r3)) -/* - * The pointer is now aligned and the length is adjusted. Try doing the - * memset again. - */ ENTRY(memset) -/* - * Preserve the contents of r0 for the return value. - */ - mov ip, r0 - andsr3, ip, #3 @ 1 unaligned? - bne 1b @ 1 + andsr3, r0, #3 @ 1 unaligned? + mov ip, r0 @ preserve r0 as return value + bne 6f @ 1 /* * we know that the pointer in ip is aligned to a word boundary. */ - orr r1, r1, r1, lsl #8 +1: orr r1, r1, r1, lsl #8 orr r1, r1, r1, lsl #16 mov r3, r1 cmp r2, #16 @@ -127,5 +111,14 @@ ENTRY(memset) tst r2, #1 strneb r1, [ip], #1 mov pc, lr + +6: subsr2, r2, #4 @ 1 do we have enough + blt 5b @ 1 bytes to align with? + cmp r3, #2 @ 1 + strltb r1, [ip], #1@ 1 + strleb r1, [ip], #1@ 1 + strbr1, [ip], #1@ 1 + add r2, r2, r3 @ 1 (r2 = r2 - (4 - r3)) + b 1b ENDPROC(memset) -- 1.8.2.rc2 -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH] defaultenv-2: Fix settings entry
On Wed, May 22, 2013 at 04:24:02PM +0200, Steffen Trumtrar wrote: There is no settings-entries-edit command. This results in a recursive call to the settings menu. Use the missing boot-entries-edit command instead. Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de Applied, thanks Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH 2/2] arm: am33xx: add pinmux config for RMII2
Signed-off-by: Jan Luebbe j...@pengutronix.de
---
arch/arm/mach-omap/am33xx_mux.c | 24
arch/arm/mach-omap/include/mach/am33xx-mux.h |2 ++
2 files changed, 26 insertions(+)
diff --git a/arch/arm/mach-omap/am33xx_mux.c b/arch/arm/mach-omap/am33xx_mux.c
index 61014d9..424d120 100644
--- a/arch/arm/mach-omap/am33xx_mux.c
+++ b/arch/arm/mach-omap/am33xx_mux.c
@@ -148,6 +148,20 @@ static const __maybe_unused struct module_pin_mux
rmii1_pin_mux[] = {
{-1},
};
+static const __maybe_unused struct module_pin_mux rmii2_pin_mux[] = {
+ {OFFSET(gpmc_a0), MODE(3)}, /* RMII2_TXEN */
+ {OFFSET(gpmc_a4), MODE(3)}, /* RMII2_TXD1 */
+ {OFFSET(gpmc_a5), MODE(3)}, /* RMII2_TXD0 */
+ {OFFSET(gpmc_a10), MODE(3) | RXACTIVE},/* RMII2_RXD1 */
+ {OFFSET(gpmc_a11), MODE(3) | RXACTIVE},/* RMII2_RXD0 */
+ {OFFSET(gpmc_wait0), MODE(3) | RXACTIVE}, /* RMII2_CRS */
+ {OFFSET(gpmc_wpn), MODE(3) | RXACTIVE}, /* RMII2_RXERR */
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN},/* MDIO_CLK */
+ {OFFSET(mii1_col), MODE(1) | RXACTIVE}, /* RMII2_REFCLK */
+ {-1},
+};
+
#ifdef CONFIG_NOR
static const __maybe_unused struct module_pin_mux nor_pin_mux[] = {
{OFFSET(lcd_data0), MODE(1) | PULLUDEN},/* NOR_A0 */
@@ -261,6 +275,16 @@ void am33xx_enable_mii1_pin_mux(void)
configure_module_pin_mux(mii1_pin_mux);
}
+void am33xx_enable_rmii1_pin_mux(void)
+{
+ configure_module_pin_mux(rmii1_pin_mux);
+}
+
+void am33xx_enable_rmii2_pin_mux(void)
+{
+ configure_module_pin_mux(rmii2_pin_mux);
+}
+
void am33xx_enable_i2c0_pin_mux(void)
{
configure_module_pin_mux(i2c0_pin_mux);
diff --git a/arch/arm/mach-omap/include/mach/am33xx-mux.h
b/arch/arm/mach-omap/include/mach/am33xx-mux.h
index e0f7077..44b93bd 100644
--- a/arch/arm/mach-omap/include/mach/am33xx-mux.h
+++ b/arch/arm/mach-omap/include/mach/am33xx-mux.h
@@ -248,6 +248,8 @@ extern void configure_module_pin_mux(const struct
module_pin_mux *mod_pin_mux);
/* Standard mux settings */
extern void am33xx_enable_mii1_pin_mux(void);
+extern void am33xx_enable_rmii1_pin_mux(void);
+extern void am33xx_enable_rmii2_pin_mux(void);
extern void am33xx_enable_i2c0_pin_mux(void);
extern void am33xx_enable_i2c1_pin_mux(void);
extern void am33xx_enable_i2c2_pin_mux(void);
--
1.7.10.4
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[PATCH 1/2] arm: am33xx: add pinmux and clock config for UART2
Signed-off-by: Jan Luebbe j...@pengutronix.de
---
arch/arm/mach-omap/am33xx_clock.c |8
arch/arm/mach-omap/am33xx_mux.c| 11 +++
arch/arm/mach-omap/include/mach/am33xx-clock.h |3 +++
arch/arm/mach-omap/include/mach/am33xx-mux.h |1 +
4 files changed, 23 insertions(+)
diff --git a/arch/arm/mach-omap/am33xx_clock.c
b/arch/arm/mach-omap/am33xx_clock.c
index a28540c..4451d62 100644
--- a/arch/arm/mach-omap/am33xx_clock.c
+++ b/arch/arm/mach-omap/am33xx_clock.c
@@ -89,6 +89,14 @@ static void per_clocks_enable(void)
__raw_writel(PRCM_MOD_EN, CM_WKUP_UART0_CLKCTRL);
while (__raw_readl(CM_WKUP_UART0_CLKCTRL) != PRCM_MOD_EN);
+ /* UART1 */
+ __raw_writel(PRCM_MOD_EN, CM_PER_UART1_CLKCTRL);
+ while (__raw_readl(CM_PER_UART1_CLKCTRL) != PRCM_MOD_EN);
+
+ /* UART2 */
+ __raw_writel(PRCM_MOD_EN, CM_PER_UART2_CLKCTRL);
+ while (__raw_readl(CM_PER_UART2_CLKCTRL) != PRCM_MOD_EN);
+
/* UART3 */
__raw_writel(PRCM_MOD_EN, CM_PER_UART3_CLKCTRL);
while (__raw_readl(CM_PER_UART3_CLKCTRL) != PRCM_MOD_EN);
diff --git a/arch/arm/mach-omap/am33xx_mux.c b/arch/arm/mach-omap/am33xx_mux.c
index 36fe379..61014d9 100644
--- a/arch/arm/mach-omap/am33xx_mux.c
+++ b/arch/arm/mach-omap/am33xx_mux.c
@@ -27,6 +27,12 @@ static const __maybe_unused struct module_pin_mux
uart0_pin_mux[] = {
{-1},
};
+static const __maybe_unused struct module_pin_mux uart2_pin_mux[] = {
+ {OFFSET(mii1_txclk), (MODE(1) | PULLUDEN | RXACTIVE)}, /* UART2_RXD */
+ {OFFSET(mii1_rxclk), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
+ {-1},
+};
+
static const __maybe_unused struct module_pin_mux uart3_pin_mux[] = {
{OFFSET(spi0_cs1), (MODE(1) | PULLUDEN | RXACTIVE)},/* UART3_RXD */
{OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
@@ -275,6 +281,11 @@ void am33xx_enable_uart0_pin_mux(void)
configure_module_pin_mux(uart0_pin_mux);
}
+void am33xx_enable_uart2_pin_mux(void)
+{
+ configure_module_pin_mux(uart2_pin_mux);
+}
+
void am33xx_enable_mmc0_pin_mux(void)
{
configure_module_pin_mux(mmc0_pin_mux);
diff --git a/arch/arm/mach-omap/include/mach/am33xx-clock.h
b/arch/arm/mach-omap/include/mach/am33xx-clock.h
index 2ecfc5f..3d1f074 100644
--- a/arch/arm/mach-omap/include/mach/am33xx-clock.h
+++ b/arch/arm/mach-omap/include/mach/am33xx-clock.h
@@ -136,7 +136,10 @@
#define CM_PER_GPIO1_CLKCTRL(CM_PER + 0xAC) /* GPIO1 */
#define CM_PER_GPIO2_CLKCTRL(CM_PER + 0xB0) /* GPIO2 */
#define CM_PER_GPIO3_CLKCTRL(CM_PER + 0xB4) /* GPIO3 */
+#define CM_PER_UART1_CLKCTRL(CM_PER + 0x6C) /* UART1 */
+#define CM_PER_UART2_CLKCTRL(CM_PER + 0x70) /* UART2 */
#define CM_PER_UART3_CLKCTRL(CM_PER + 0x74) /* UART3 */
+#define CM_PER_UART4_CLKCTRL(CM_PER + 0x78) /* UART4 */
#define CM_PER_I2C1_CLKCTRL (CM_PER + 0x48) /* I2C1 */
#define CM_PER_I2C2_CLKCTRL (CM_PER + 0x44) /* I2C2 */
#define CM_WKUP_GPIO0_CLKCTRL (CM_WKUP + 0x8) /* GPIO0 */
diff --git a/arch/arm/mach-omap/include/mach/am33xx-mux.h
b/arch/arm/mach-omap/include/mach/am33xx-mux.h
index 896e958..e0f7077 100644
--- a/arch/arm/mach-omap/include/mach/am33xx-mux.h
+++ b/arch/arm/mach-omap/include/mach/am33xx-mux.h
@@ -252,6 +252,7 @@ extern void am33xx_enable_i2c0_pin_mux(void);
extern void am33xx_enable_i2c1_pin_mux(void);
extern void am33xx_enable_i2c2_pin_mux(void);
extern void am33xx_enable_uart0_pin_mux(void);
+extern void am33xx_enable_uart2_pin_mux(void);
extern void am33xx_enable_mmc0_pin_mux(void);
#endif /*__AM33XX_MUX_H__ */
--
1.7.10.4
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2013.05 breaking Linux boot on imx28 CFA-10036
Hi, I've tested lately both 2013.05.0 and the master of Barebox on the imx28 cfa-10036 board we have. Everything works fine with 2013.04.0. The issue I have is that Barebox in itself works fine, however, Linux fails to boot after it has been started by Barebox, quite early and badly: http://code.bulix.org/s3z010-83581 I've tried to bisect it, but didn't get very far, since there are other issues coming in, that prevent a full Linux boot (but it might be related to Linux itself, anyway.) So, the last fully working commit I could find is cf95711e Its child commit, 9d8e0835, boots the kernel, but just before actually booting it, displays the error fdt_initrd: FDT_ERR_BADLAYOUT, so that might be an hint. The configuration I'm using is cfa10036_defconfig. Thanks, Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: 2013.05 breaking Linux boot on imx28 CFA-10036
On Thu, 2013-05-23 at 11:46 +0200, Maxime Ripard wrote: I've tested lately both 2013.05.0 and the master of Barebox on the imx28 cfa-10036 board we have. Everything works fine with 2013.04.0. The issue I have is that Barebox in itself works fine, however, Linux fails to boot after it has been started by Barebox, quite early and badly: http://code.bulix.org/s3z010-83581 Could you try the not-yet-released stable branch? http://git.pengutronix.de/?p=barebox.git;a=shortlog;h=refs/heads/stable/v2013.05 -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
stable releases
Hi All, I more and more notice that we are not able to find and eliminate bugs before the release but often weeks after a release. After trying to avoid the additional work for as long as I could I feel we have to do something about it, so I intend to do stable releases more frequently. So if you have a patch included in stable releases please add a 'Stable' tag to the patch, possibly followed by the oldest release the patch is relevant for, so: Stable: v2013.04.0 See the following patches which I currently have collected for the next stable release (v2013.05.1). I'll release this in the next few days. If you want to have patches added, please say so. Sascha 8--- The following changes since commit 5fdb9c0829b12e042e8fa1131bf2eee180e2b11b: Release v2013.05.0 (2013-05-06 09:28:07 +0200) are available in the git repository at: git://git.pengutronix.de/git/barebox.git stable/v2013.05 for you to fetch changes up to 95ce3f3ffe29a968f40ee43eaea5f65f9f73b72b: ARM: ccmx51: Another fix SDRAM size detection (2013-05-23 09:31:31 +0200) Alexander Shiyan (1): ARM: ccmx51: Another fix SDRAM size detection Alexandre Belloni (1): sama5d3xek: correct rootfs nand partition Enrico Scholz (3): ARM v7: fix mmu-off operation ARM v7: v7_mmu_cache_flush(): do not restore r0-r3 (minor optimization) ARM v7: added v7_mmu_cache_invalidate() Juergen Beisert (1): MXS: fix SoC detecting Lucas Stach (1): arm: properly init alignment trap bit Nicolas Pitre (1): ARM: fix the memset fix Sascha Hauer (4): fdt: Fix dt memreserve entry ARM: invalidate data caches during early init ARM: i.MX: Allow disabling SDRAM autodetection ARM: i.MX: ccxmx51: detect SDRAM size by board id Steffen Trumtrar (1): defaultenv-2: Fix settings entry arch/arm/boards/ccxmx51/ccxmx51.c | 63 +++- arch/arm/boards/ccxmx51/ccxmx51.h | 1 + arch/arm/boards/ccxmx51/lowlevel.c | 4 +- arch/arm/boards/sama5d3xek/env/config | 2 +- arch/arm/cpu/cache-armv7.S | 74 - arch/arm/cpu/cache.c| 21 ++ arch/arm/cpu/start-pbl.c| 2 + arch/arm/cpu/start.c| 2 + arch/arm/include/asm/barebox-arm-head.h | 2 +- arch/arm/include/asm/cache.h| 5 +++ arch/arm/lib/memset.S | 33 ++- arch/arm/mach-imx/esdctl.c | 14 +++ arch/arm/mach-imx/include/mach/esdctl.h | 1 + arch/arm/mach-mxs/imx.c | 1 + defaultenv-2/menu/menu/settings | 2 +- drivers/of/fdt.c| 3 +- 16 files changed, 154 insertions(+), 76 deletions(-) -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: 2013.05 breaking Linux boot on imx28 CFA-10036
Hi Jan, On Thu, May 23, 2013 at 12:44:16PM +0200, Jan Lübbe wrote: On Thu, 2013-05-23 at 11:46 +0200, Maxime Ripard wrote: I've tested lately both 2013.05.0 and the master of Barebox on the imx28 cfa-10036 board we have. Everything works fine with 2013.04.0. The issue I have is that Barebox in itself works fine, however, Linux fails to boot after it has been started by Barebox, quite early and badly: http://code.bulix.org/s3z010-83581 Could you try the not-yet-released stable branch? http://git.pengutronix.de/?p=barebox.git;a=shortlog;h=refs/heads/stable/v2013.05 Hmm, I somehow overlooked that branch. It works now, thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: 2013.05 breaking Linux boot on imx28 CFA-10036
On Thu, May 23, 2013 at 02:52:00PM +0200, Maxime Ripard wrote: Hi Jan, On Thu, May 23, 2013 at 12:44:16PM +0200, Jan Lübbe wrote: On Thu, 2013-05-23 at 11:46 +0200, Maxime Ripard wrote: I've tested lately both 2013.05.0 and the master of Barebox on the imx28 cfa-10036 board we have. Everything works fine with 2013.04.0. The issue I have is that Barebox in itself works fine, however, Linux fails to boot after it has been started by Barebox, quite early and badly: http://code.bulix.org/s3z010-83581 Could you try the not-yet-released stable branch? http://git.pengutronix.de/?p=barebox.git;a=shortlog;h=refs/heads/stable/v2013.05 Hmm, I somehow overlooked that branch. It works now, thanks! And just for the record, this issue is fixed with the commit 9c56cbb6. Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH 1/2 v2] cfi_flash: add shift option for some cfi memory chips
On Wed, May 22, 2013 at 09:53:39AM +0200, Oleksij Rempel wrote: From: Oleksij Rempel bug-tr...@fisher-privat.net Many cfi chips support 16 and 8 bit modes. Most important difference is use of so called Q15/A-1 pin. In 16bit mode this pin is used for data IO. In 8bit mode, it is an address input which add one more least significant bit (LSB). In this case we should shift all adresses by one: For example 0xaa 1 = 0x154 Signed-off-by: Oleksij Rempel li...@rempel-privat.de Applied, thanks Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH 2/2] cfi_flash: size_ratio should not be 0
On Wed, May 22, 2013 at 09:53:40AM +0200, Oleksij Rempel wrote:
We will get size = 0 if size_ratio = 0
Signed-off-by: Oleksij Rempel li...@rempel-privat.de
---
drivers/mtd/nor/cfi_flash.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nor/cfi_flash.c b/drivers/mtd/nor/cfi_flash.c
index 4b4e29d..85e96ce 100644
--- a/drivers/mtd/nor/cfi_flash.c
+++ b/drivers/mtd/nor/cfi_flash.c
@@ -371,7 +371,8 @@ static ulong flash_get_size (struct flash_info *info)
size_ratio = info-portwidth / info-chipwidth;
/* if the chip is x8/x16 reduce the ratio by half */
if ((info-interface == FLASH_CFI_X8X16)
- (info-chipwidth == FLASH_CFI_BY8)) {
+ (info-chipwidth == FLASH_CFI_BY8)
+ (size_ratio != 1)) {
size_ratio = 1;
}
Could you elaborate in which constellation this happens?
Sascha
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Re: [PATCH] mtd-core: fix mtd erase operation for non-uniform flashes.
On Wed, May 22, 2013 at 05:54:16PM +0100, Renaud Barbier wrote: This patch supports the erasing of CFI flash with non-uniform sector. When more than one erase region exists, the mtd_erasesize function assigns the erase size of the sector to the erase_info structure. The problem was discovered when erasing /dev/env0 on my PPC board. This is a partition of size 0x8000 at offset 0 of a 32MB Intel compatible flash with a bottom boot block i.e 4 32KB sectors followed by 255 128KB sectors. barebox unprotect /dev/env0 barebox erase /dev/env0 cfi_erase: start = 0x0, end = 0x3, count = 0x2 Flash erase error at address fe008000 Block Erase Error. Block locked. erase: I/O error The error above is that a count of 0x2 is passed instead of 0x8000 by mtd_op_erase. This is because the code does not take into account multiple erase regions. After taking into account the erase regions, only the first sector is erased: barebox unprotect /dev/env0 barebox erase /dev/env0 cfi_erase: start = 0x0, end = 0x0, count = 0x8000 Signed-off-by: Renaud Barbier renaud.barb...@ge.com Applied, thanks Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [RFC, PATCH v2 1/3] MIPS: add Atheros ar531x family support
Hi Oleksij,
On Wed, May 22, 2013 at 09:49:47AM +0200, Oleksij Rempel wrote:
Signed-off-by: Oleksij Rempel li...@rempel-privat.de
Signed-off-by: Antony Pavlov antonynpav...@gmail.com
+
+/*
+ * This table is indexed by bits 5..4 of the CLOCKCTL1 register
+ * to determine the predevisor value.
+ */
+static int CLOCKCTL1_PREDIVIDE_TABLE[4] = { 1, 2, 4, 5 };
+
+static unsigned int
+ar2312_cpu_frequency(void)
+{
+ unsigned int predivide_mask, predivide_shift;
+ unsigned int multiplier_mask, multiplier_shift;
+ unsigned int clockCtl1, preDivideSelect, preDivisor, multiplier;
No CamelCase please.
+static int platform_init(void)
+{
+ add_generic_device(ar2312_reset, DEVICE_ID_SINGLE, NULL,
+ KSEG1ADDR(AR2312_RESETTMR), 0x4,
+ IORESOURCE_MEM, NULL);
+ watchdog_init();
+ flash_init();
+ ether_init();
Whether or not the flash/ethernet/serial device is available is board
specific, not SoC specific, so this should be done in board code. It's
good to provide helpers to make this simple for the board code though,
so a good option would be to add a SoC prefix to the functions and call
it from board code.
Otherwise I am fine with this patch, but maybe Antony still has some
comments.
Sascha
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Re: imx31 bcb
On Wed, May 22, 2013 at 04:04:56PM +0200, Rodney Antonisse wrote: Is there anybody out there who successfully used the bcb command in barebox? I just can't seem to get a valid bcb without using the Freescale kobs-ng tools (which is not my preferred way of preparing the nand). Are we really talking about i.MX31 here? The bcb command is only available on i.MX28 Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [RFC, PATCH v2 1/3] MIPS: add Atheros ar531x family support
Am 23.05.2013 15:35, schrieb Sascha Hauer:
Hi Oleksij,
On Wed, May 22, 2013 at 09:49:47AM +0200, Oleksij Rempel wrote:
Signed-off-by: Oleksij Rempel li...@rempel-privat.de
Signed-off-by: Antony Pavlov antonynpav...@gmail.com
+
+/*
+ * This table is indexed by bits 5..4 of the CLOCKCTL1 register
+ * to determine the predevisor value.
+ */
+static int CLOCKCTL1_PREDIVIDE_TABLE[4] = { 1, 2, 4, 5 };
+
+static unsigned int
+ar2312_cpu_frequency(void)
+{
+ unsigned int predivide_mask, predivide_shift;
+ unsigned int multiplier_mask, multiplier_shift;
+ unsigned int clockCtl1, preDivideSelect, preDivisor, multiplier;
No CamelCase please.
ok. i'll fix it.
+static int platform_init(void)
+{
+ add_generic_device(ar2312_reset, DEVICE_ID_SINGLE, NULL,
+ KSEG1ADDR(AR2312_RESETTMR), 0x4,
+ IORESOURCE_MEM, NULL);
+ watchdog_init();
+ flash_init();
+ ether_init();
Whether or not the flash/ethernet/serial device is available is board
specific, not SoC specific, so this should be done in board code. It's
good to provide helpers to make this simple for the board code though,
so a good option would be to add a SoC prefix to the functions and call
it from board code.
Probably it will make sense to have generic type of board. Because this
will work with most configurations. Since it is WiSoC (Wireless SoC),
ethernet is on chip too.
Otherwise I am fine with this patch, but maybe Antony still has some
comments.
--
Regards,
Oleksij
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[PATCH] MCI: support boot partitions
(newer?) eMMCs have some areas intended for bootloaders. This series adds support for them. i.MX SoCs support booting from these areas which is quite convenient since we no longer have to take care about the regular partition table. Also this series adds a new device parameter convenience helper for enums. Sascha Sascha Hauer (3): param: Add info function param: Add helpers to provide an enum parameter mci: Add support for MMC boot partitions drivers/base/driver.c | 8 ++- drivers/mci/Kconfig| 3 + drivers/mci/mci-core.c | 192 ++--- include/mci.h | 31 +++- include/param.h| 15 lib/parameter.c| 104 +++ 6 files changed, 308 insertions(+), 45 deletions(-) ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH 3/3] mci: Add support for MMC boot partitions
Some MMC cards support boot partitions. These are special regions
on the MMC card intended to put a bootloader on.
This patch adds support for these partitions, they are accessible
as /dev/diskx.boot[0|1].
Additionally the partitions can be configured bootable using a
device parameter. This can be used to mark the user area or one
of the boot partitions as bootable.
Since this feature is mostly seen on eMMC cards it is made optional
to lower the size impact for boards which do not have eMMC.
Signed-off-by: Sascha Hauer s.ha...@pengutronix.de
---
drivers/mci/Kconfig| 3 +
drivers/mci/mci-core.c | 192 ++---
include/mci.h | 31 +++-
3 files changed, 183 insertions(+), 43 deletions(-)
diff --git a/drivers/mci/Kconfig b/drivers/mci/Kconfig
index 9558f28..7f28d13 100644
--- a/drivers/mci/Kconfig
+++ b/drivers/mci/Kconfig
@@ -29,6 +29,9 @@ config MCI_WRITE
default y
select DISK_WRITE
+config MCI_MMC_BOOT_PARTITIONS
+ bool support MMC boot partitions
+
comment --- MCI host drivers ---
config MCI_MXS
diff --git a/drivers/mci/mci-core.c b/drivers/mci/mci-core.c
index 90ac2a3..5367b4f 100644
--- a/drivers/mci/mci-core.c
+++ b/drivers/mci/mci-core.c
@@ -388,6 +388,35 @@ static int mci_switch(struct mci *mci, unsigned set,
unsigned index,
return mci_send_cmd(mci, cmd, NULL);
}
+static int mci_calc_blk_cnt(uint64_t cap, unsigned shift)
+{
+ unsigned ret = cap shift;
+
+ if (ret 0x7fff) {
+ pr_warn(Limiting card size due to 31 bit contraints\n);
+ return 0x7fff;
+ }
+
+ return (int)ret;
+}
+
+static void mci_part_add(struct mci *mci, uint64_t size,
+unsigned int part_cfg, char *name, int idx, bool ro,
+int area_type)
+{
+ struct mci_part *part = mci-part[mci-nr_parts];
+
+ part-mci = mci;
+ part-size = size;
+ part-blk.cdev.name = name;
+ part-blk.blockbits = SECTOR_SHIFT;
+ part-blk.num_blocks = mci_calc_blk_cnt(size, part-blk.blockbits);
+ part-area_type = area_type;
+ part-part_cfg = part_cfg;
+
+ mci-nr_parts++;
+}
+
/**
* Change transfer frequency for an MMC card
* @param mci MCI instance
@@ -442,6 +471,25 @@ static int mmc_change_freq(struct mci *mci)
else
mci-card_caps |= MMC_MODE_HS;
+ if (mci-ext_csd[EXT_CSD_REV] = 3 mci-ext_csd[EXT_CSD_BOOT_MULT]) {
+ int idx;
+ unsigned int part_size;
+
+ for (idx = 0; idx MMC_NUM_BOOT_PARTITION; idx++) {
+ char *name;
+ part_size = mci-ext_csd[EXT_CSD_BOOT_MULT] 17;
+
+ name = asprintf(%s.boot%d, mci-cdevname, idx);
+ mci_part_add(mci, part_size,
+ EXT_CSD_PART_CONFIG_ACC_BOOT0 + idx,
+ name, idx, true,
+ MMC_BLK_DATA_AREA_BOOT);
+ }
+
+ mci-ext_csd_part_config = mci-ext_csd[EXT_CSD_PART_CONFIG];
+ mci-bootpart = (mci-ext_csd_part_config 3) 0x7;
+ }
+
return 0;
}
@@ -1063,6 +,10 @@ static int mci_startup(struct mci *mci)
/* we setup the blocklength only one times for all accesses to this
media */
err = mci_set_blocklen(mci, mci-read_bl_len);
+ mci_part_add(mci, mci-capacity, 0,
+ mci-cdevname, 0, true,
+ MMC_BLK_DATA_AREA_MAIN);
+
return err;
}
@@ -1104,6 +1156,36 @@ static int sd_send_if_cond(struct mci *mci)
return 0;
}
+static int mci_blk_part_switch(struct mci_part *part)
+{
+ struct mci *mci = part-mci;
+ int ret;
+
+ if (!IS_ENABLED(CONFIG_MCI_MMC_BOOT_PARTITIONS))
+ return 0;
+
+ if (mci-part_curr == part)
+ return 0;
+
+ if (!IS_SD(mci)) {
+ u8 part_config = mci-ext_csd_part_config;
+
+ part_config = ~EXT_CSD_PART_CONFIG_ACC_MASK;
+ part_config |= part-part_cfg;
+
+ ret = mci_switch(mci, EXT_CSD_CMD_SET_NORMAL,
+ EXT_CSD_PART_CONFIG, part_config);
+ if (ret)
+ return ret;
+
+ mci-ext_csd_part_config = part_config;
+ }
+
+ mci-part_curr = part;
+
+ return 0;
+}
+
/* -- attach to the blocklayer --- */
/**
@@ -1119,10 +1201,13 @@ static int sd_send_if_cond(struct mci *mci)
static int __maybe_unused mci_sd_write(struct block_device *blk,
const void *buffer, int block, int num_blocks)
{
- struct mci *mci = container_of(blk, struct mci, blk);
+ struct mci_part *part = container_of(blk, struct mci_part, blk);
+ struct mci *mci = part-mci;
struct mci_host *host =
Re: [PATCH 2/2] cfi_flash: size_ratio should not be 0
Am 23.05.2013 15:13, schrieb Sascha Hauer:
On Wed, May 22, 2013 at 09:53:40AM +0200, Oleksij Rempel wrote:
We will get size = 0 if size_ratio = 0
Signed-off-by: Oleksij Rempel li...@rempel-privat.de
---
drivers/mtd/nor/cfi_flash.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nor/cfi_flash.c b/drivers/mtd/nor/cfi_flash.c
index 4b4e29d..85e96ce 100644
--- a/drivers/mtd/nor/cfi_flash.c
+++ b/drivers/mtd/nor/cfi_flash.c
@@ -371,7 +371,8 @@ static ulong flash_get_size (struct flash_info *info)
size_ratio = info-portwidth / info-chipwidth;
/* if the chip is x8/x16 reduce the ratio by half */
if ((info-interface == FLASH_CFI_X8X16)
-(info-chipwidth == FLASH_CFI_BY8)) {
+(info-chipwidth == FLASH_CFI_BY8)
+(size_ratio != 1)) {
size_ratio = 1;
}
Could you elaborate in which constellation this happens?
It happens in my case with MX29LV320MBTC attached to atheros ar2313.
Both of them support x8 and x16 modes, but attached only in x8. Plus
this chip enables LSB in 8 bit mode.
--
Regards,
Oleksij
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[PATCH] net: fec_imx: default phy address to -1 for dt probe
To enable automatic probing of the phy.
Signed-off-by: Sascha Hauer s.ha...@pengutronix.de
---
drivers/net/fec_imx.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/fec_imx.c b/drivers/net/fec_imx.c
index 1a85d15..25d8d8e 100644
--- a/drivers/net/fec_imx.c
+++ b/drivers/net/fec_imx.c
@@ -707,6 +707,7 @@ static int fec_probe(struct device_d *dev)
if (dev-device_node) {
ret = fec_probe_dt(dev, fec);
+ fec-phy_addr = -1;
} else if (pdata) {
fec-interface = pdata-xcv_type;
fec-phy_init = pdata-phy_init;
--
1.8.2.rc2
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Re: 2013.05 breaking Linux boot on imx28 CFA-10036
On Thu, May 23, 2013 at 02:52:00PM +0200, Maxime Ripard wrote: Hi Jan, On Thu, May 23, 2013 at 12:44:16PM +0200, Jan Lübbe wrote: On Thu, 2013-05-23 at 11:46 +0200, Maxime Ripard wrote: I've tested lately both 2013.05.0 and the master of Barebox on the imx28 cfa-10036 board we have. Everything works fine with 2013.04.0. The issue I have is that Barebox in itself works fine, however, Linux fails to boot after it has been started by Barebox, quite early and badly: http://code.bulix.org/s3z010-83581 Could you try the not-yet-released stable branch? http://git.pengutronix.de/?p=barebox.git;a=shortlog;h=refs/heads/stable/v2013.05 Hmm, I somehow overlooked that branch. I created it just this morning ;) Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH 1/2] arm: am33xx: add pinmux and clock config for UART2
On Thu, May 23, 2013 at 11:45:57AM +0200, Jan Luebbe wrote:
Signed-off-by: Jan Luebbe j...@pengutronix.de
Applied, thanks
Sascha
---
arch/arm/mach-omap/am33xx_clock.c |8
arch/arm/mach-omap/am33xx_mux.c| 11 +++
arch/arm/mach-omap/include/mach/am33xx-clock.h |3 +++
arch/arm/mach-omap/include/mach/am33xx-mux.h |1 +
4 files changed, 23 insertions(+)
diff --git a/arch/arm/mach-omap/am33xx_clock.c
b/arch/arm/mach-omap/am33xx_clock.c
index a28540c..4451d62 100644
--- a/arch/arm/mach-omap/am33xx_clock.c
+++ b/arch/arm/mach-omap/am33xx_clock.c
@@ -89,6 +89,14 @@ static void per_clocks_enable(void)
__raw_writel(PRCM_MOD_EN, CM_WKUP_UART0_CLKCTRL);
while (__raw_readl(CM_WKUP_UART0_CLKCTRL) != PRCM_MOD_EN);
+ /* UART1 */
+ __raw_writel(PRCM_MOD_EN, CM_PER_UART1_CLKCTRL);
+ while (__raw_readl(CM_PER_UART1_CLKCTRL) != PRCM_MOD_EN);
+
+ /* UART2 */
+ __raw_writel(PRCM_MOD_EN, CM_PER_UART2_CLKCTRL);
+ while (__raw_readl(CM_PER_UART2_CLKCTRL) != PRCM_MOD_EN);
+
/* UART3 */
__raw_writel(PRCM_MOD_EN, CM_PER_UART3_CLKCTRL);
while (__raw_readl(CM_PER_UART3_CLKCTRL) != PRCM_MOD_EN);
diff --git a/arch/arm/mach-omap/am33xx_mux.c b/arch/arm/mach-omap/am33xx_mux.c
index 36fe379..61014d9 100644
--- a/arch/arm/mach-omap/am33xx_mux.c
+++ b/arch/arm/mach-omap/am33xx_mux.c
@@ -27,6 +27,12 @@ static const __maybe_unused struct module_pin_mux
uart0_pin_mux[] = {
{-1},
};
+static const __maybe_unused struct module_pin_mux uart2_pin_mux[] = {
+ {OFFSET(mii1_txclk), (MODE(1) | PULLUDEN | RXACTIVE)}, /* UART2_RXD */
+ {OFFSET(mii1_rxclk), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
+ {-1},
+};
+
static const __maybe_unused struct module_pin_mux uart3_pin_mux[] = {
{OFFSET(spi0_cs1), (MODE(1) | PULLUDEN | RXACTIVE)},/* UART3_RXD */
{OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
@@ -275,6 +281,11 @@ void am33xx_enable_uart0_pin_mux(void)
configure_module_pin_mux(uart0_pin_mux);
}
+void am33xx_enable_uart2_pin_mux(void)
+{
+ configure_module_pin_mux(uart2_pin_mux);
+}
+
void am33xx_enable_mmc0_pin_mux(void)
{
configure_module_pin_mux(mmc0_pin_mux);
diff --git a/arch/arm/mach-omap/include/mach/am33xx-clock.h
b/arch/arm/mach-omap/include/mach/am33xx-clock.h
index 2ecfc5f..3d1f074 100644
--- a/arch/arm/mach-omap/include/mach/am33xx-clock.h
+++ b/arch/arm/mach-omap/include/mach/am33xx-clock.h
@@ -136,7 +136,10 @@
#define CM_PER_GPIO1_CLKCTRL(CM_PER + 0xAC) /* GPIO1 */
#define CM_PER_GPIO2_CLKCTRL(CM_PER + 0xB0) /* GPIO2 */
#define CM_PER_GPIO3_CLKCTRL(CM_PER + 0xB4) /* GPIO3 */
+#define CM_PER_UART1_CLKCTRL(CM_PER + 0x6C) /* UART1 */
+#define CM_PER_UART2_CLKCTRL(CM_PER + 0x70) /* UART2 */
#define CM_PER_UART3_CLKCTRL(CM_PER + 0x74) /* UART3 */
+#define CM_PER_UART4_CLKCTRL(CM_PER + 0x78) /* UART4 */
#define CM_PER_I2C1_CLKCTRL (CM_PER + 0x48) /* I2C1 */
#define CM_PER_I2C2_CLKCTRL (CM_PER + 0x44) /* I2C2 */
#define CM_WKUP_GPIO0_CLKCTRL (CM_WKUP + 0x8) /* GPIO0 */
diff --git a/arch/arm/mach-omap/include/mach/am33xx-mux.h
b/arch/arm/mach-omap/include/mach/am33xx-mux.h
index 896e958..e0f7077 100644
--- a/arch/arm/mach-omap/include/mach/am33xx-mux.h
+++ b/arch/arm/mach-omap/include/mach/am33xx-mux.h
@@ -252,6 +252,7 @@ extern void am33xx_enable_i2c0_pin_mux(void);
extern void am33xx_enable_i2c1_pin_mux(void);
extern void am33xx_enable_i2c2_pin_mux(void);
extern void am33xx_enable_uart0_pin_mux(void);
+extern void am33xx_enable_uart2_pin_mux(void);
extern void am33xx_enable_mmc0_pin_mux(void);
#endif /*__AM33XX_MUX_H__ */
--
1.7.10.4
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[PATCH] ARM: cfa10036: Add more board ID for boot time detection
From: Brian Lilly br...@crystalfontz.com
As new breakout boards are being developped, we need to add their IDs in
the device detection code, otherwise they will be treated as regular
CFA-10036.
Signed-off-by: Brian Lilly br...@crystalfontz.com
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
arch/arm/boards/crystalfontz-cfa10036/hwdetect.c | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boards/crystalfontz-cfa10036/hwdetect.c
b/arch/arm/boards/crystalfontz-cfa10036/hwdetect.c
index 5eb3ca4..21199d6 100644
--- a/arch/arm/boards/crystalfontz-cfa10036/hwdetect.c
+++ b/arch/arm/boards/crystalfontz-cfa10036/hwdetect.c
@@ -29,6 +29,10 @@ enum board_type {
BOARD_ID_CFA10036 = 0,
BOARD_ID_CFA10037 = 1,
BOARD_ID_CFA10049 = 2,
+ BOARD_ID_CFA10055 = 3,
+ BOARD_ID_CFA10056 = 4,
+ BOARD_ID_CFA10057 = 5,
+ BOARD_ID_CFA10058 = 6,
};
struct cfa_eeprom_info {
@@ -83,6 +87,18 @@ void cfa10036_detect_hw(void)
case BOARD_ID_CFA10049:
board_name = cfa10049;
break;
+ case BOARD_ID_CFA10055:
+ board_name = cfa10055;
+ break;
+ case BOARD_ID_CFA10056:
+ board_name = cfa10056;
+ break;
+ case BOARD_ID_CFA10057:
+ board_name = cfa10057;
+ break;
+ case BOARD_ID_CFA10058:
+ board_name = cfa10058;
+ break;
default:
pr_err(Board ID not supported\n);
return;
--
1.8.1.2
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