[PATCH 1/2] ARM: i.MX: move esdctl device registration to soc_init
The esdctl devices are currently not in the devicetrees. this means
they are not registered when booting from the devicetree. Move the
device registration from soc_devices_init to soc_init which is called
even with devicetree support so that we get esdctl devices.
Signed-off-by: Sascha Hauer s.ha...@pengutronix.de
---
arch/arm/mach-imx/imx1.c | 2 +-
arch/arm/mach-imx/imx25.c | 2 +-
arch/arm/mach-imx/imx27.c | 4 ++--
arch/arm/mach-imx/imx31.c | 2 +-
arch/arm/mach-imx/imx35.c | 2 +-
arch/arm/mach-imx/imx51.c | 2 +-
arch/arm/mach-imx/imx53.c | 2 +-
7 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-imx/imx1.c b/arch/arm/mach-imx/imx1.c
index ecd71b8..78a0242 100644
--- a/arch/arm/mach-imx/imx1.c
+++ b/arch/arm/mach-imx/imx1.c
@@ -55,6 +55,7 @@ void imx1_setup_eimcs(size_t cs, unsigned upper, unsigned
lower)
int imx1_init(void)
{
imx1_detect_reset_source();
+ add_generic_device(imx1-sdramc, 0, NULL, MX1_SDRAMC_BASE_ADDR, 0x100,
IORESOURCE_MEM, NULL);
return 0;
}
@@ -70,7 +71,6 @@ int imx1_devices_init(void)
add_generic_device(imx1-gpio, 2, NULL, MX1_GPIO3_BASE_ADDR, 0x100,
IORESOURCE_MEM, NULL);
add_generic_device(imx1-gpio, 3, NULL, MX1_GPIO4_BASE_ADDR, 0x100,
IORESOURCE_MEM, NULL);
add_generic_device(imx1-wdt, 0, NULL, MX1_WDT_BASE_ADDR, 0x100,
IORESOURCE_MEM, NULL);
- add_generic_device(imx1-sdramc, 0, NULL, MX1_SDRAMC_BASE_ADDR, 0x100,
IORESOURCE_MEM, NULL);
return 0;
}
diff --git a/arch/arm/mach-imx/imx25.c b/arch/arm/mach-imx/imx25.c
index 1d94419..1f87787 100644
--- a/arch/arm/mach-imx/imx25.c
+++ b/arch/arm/mach-imx/imx25.c
@@ -56,6 +56,7 @@ u64 imx_uid(void)
int imx25_init(void)
{
imx25_boot_save_loc((void *)MX25_CCM_BASE_ADDR);
+ add_generic_device(imx25-esdctl, 0, NULL, MX25_ESDCTL_BASE_ADDR,
0x1000, IORESOURCE_MEM, NULL);
return 0;
}
@@ -73,7 +74,6 @@ int imx25_devices_init(void)
add_generic_device(imx31-gpio, 2, NULL, MX25_GPIO3_BASE_ADDR, 0x1000,
IORESOURCE_MEM, NULL);
add_generic_device(imx31-gpio, 3, NULL, MX25_GPIO4_BASE_ADDR, 0x1000,
IORESOURCE_MEM, NULL);
add_generic_device(imx21-wdt, 0, NULL, MX25_WDOG_BASE_ADDR, 0x1000,
IORESOURCE_MEM, NULL);
- add_generic_device(imx25-esdctl, 0, NULL, MX25_ESDCTL_BASE_ADDR,
0x1000, IORESOURCE_MEM, NULL);
return 0;
}
diff --git a/arch/arm/mach-imx/imx27.c b/arch/arm/mach-imx/imx27.c
index e0f4765..d3eaa87 100644
--- a/arch/arm/mach-imx/imx27.c
+++ b/arch/arm/mach-imx/imx27.c
@@ -101,6 +101,8 @@ int imx27_init(void)
{
imx27_silicon_revision();
imx27_boot_save_loc((void *)MX27_SYSCTRL_BASE_ADDR);
+ add_generic_device(imx27-esdctl, DEVICE_ID_SINGLE, NULL,
+ MX27_ESDCTL_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
return 0;
}
@@ -124,8 +126,6 @@ int imx27_devices_init(void)
add_generic_device(imx1-gpio, 4, NULL, MX27_GPIO5_BASE_ADDR, 0x100,
IORESOURCE_MEM, NULL);
add_generic_device(imx1-gpio, 5, NULL, MX27_GPIO6_BASE_ADDR, 0x100,
IORESOURCE_MEM, NULL);
add_generic_device(imx21-wdt, 0, NULL, MX27_WDOG_BASE_ADDR, 0x1000,
IORESOURCE_MEM, NULL);
- add_generic_device(imx27-esdctl, DEVICE_ID_SINGLE, NULL,
- MX27_ESDCTL_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device(imx27-usb-misc, 0, NULL, MX27_USB_OTG_BASE_ADDR +
0x600, 0x100, IORESOURCE_MEM, NULL);
return 0;
diff --git a/arch/arm/mach-imx/imx31.c b/arch/arm/mach-imx/imx31.c
index eb0c415..3013f02 100644
--- a/arch/arm/mach-imx/imx31.c
+++ b/arch/arm/mach-imx/imx31.c
@@ -29,6 +29,7 @@ void imx31_setup_weimcs(size_t cs, unsigned upper, unsigned
lower,
int imx31_init(void)
{
+ add_generic_device(imx31-esdctl, 0, NULL, MX31_ESDCTL_BASE_ADDR,
0x1000, IORESOURCE_MEM, NULL);
return 0;
}
@@ -44,7 +45,6 @@ int imx31_devices_init(void)
add_generic_device(imx31-gpio, 1, NULL, MX31_GPIO2_BASE_ADDR, 0x1000,
IORESOURCE_MEM, NULL);
add_generic_device(imx31-gpio, 2, NULL, MX31_GPIO3_BASE_ADDR, 0x1000,
IORESOURCE_MEM, NULL);
add_generic_device(imx21-wdt, 0, NULL, MX31_WDOG_BASE_ADDR, 0x1000,
IORESOURCE_MEM, NULL);
- add_generic_device(imx31-esdctl, 0, NULL, MX31_ESDCTL_BASE_ADDR,
0x1000, IORESOURCE_MEM, NULL);
add_generic_device(imx31-usb-misc, 0, NULL, MX31_USB_OTG_BASE_ADDR +
0x600, 0x100, IORESOURCE_MEM, NULL);
return 0;
diff --git a/arch/arm/mach-imx/imx35.c b/arch/arm/mach-imx/imx35.c
index 14ddba3..40f5770 100644
--- a/arch/arm/mach-imx/imx35.c
+++ b/arch/arm/mach-imx/imx35.c
@@ -56,6 +56,7 @@ int imx35_init(void)
imx35_silicon_revision();
imx35_boot_save_loc((void *)MX35_CCM_BASE_ADDR);
+ add_generic_device(imx35-esdctl, 0, NULL, MX35_ESDCTL_BASE_ADDR,
0x1000, IORESOURCE_MEM, NULL);
return 0;
}
@@ -72,7 +73,6 @@ int imx35_devices_init(void)
add_generic_device(imx31-gpio, 1, NULL,
[PATCH 2/2] ARM: dts: imx53 qsb: remove wrong memory bank
The i.MX53 qsb has 1GiB of memory, but it's divided into two non
contigous banks. Remove the wrong memory node since it's overwritten
with the correct values during wuntime anyway.
Signed-off-by: Sascha Hauer s.ha...@pengutronix.de
---
arch/arm/dts/imx53-qsb.dts | 4
1 file changed, 4 deletions(-)
diff --git a/arch/arm/dts/imx53-qsb.dts b/arch/arm/dts/imx53-qsb.dts
index 3be4ff2..f988ca9 100644
--- a/arch/arm/dts/imx53-qsb.dts
+++ b/arch/arm/dts/imx53-qsb.dts
@@ -26,10 +26,6 @@
};
};
- memory {
- reg = 0x7000 0x4000;
- };
-
display@di0 {
compatible = fsl,imx-parallel-display;
crtcs = ipu 0;
--
1.8.4.rc3
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[PATCH] AM33xx: Make OSC frequency board depended
The oscillator frequency varies on different AM33xx boards.
Pass the osc frequency from lowlevel board code
to set the correct one on every board.
Signed-off-by: Teresa Gámez t.ga...@phytec.de
---
arch/arm/boards/beaglebone/lowlevel.c |2 +-
arch/arm/boards/pcm051/lowlevel.c |2 +-
arch/arm/mach-omap/am33xx_clock.c | 26
arch/arm/mach-omap/include/mach/am33xx-clock.h |8 +--
4 files changed, 16 insertions(+), 22 deletions(-)
diff --git a/arch/arm/boards/beaglebone/lowlevel.c
b/arch/arm/boards/beaglebone/lowlevel.c
index d871ca1..2f3b3df 100644
--- a/arch/arm/boards/beaglebone/lowlevel.c
+++ b/arch/arm/boards/beaglebone/lowlevel.c
@@ -198,7 +198,7 @@ void beaglebone_sram_init(void)
u32 regVal, uart_base;
/* Setup the PLLs and the clocks for the peripherals */
- pll_init(MPUPLL_M_500);
+ pll_init(MPUPLL_M_500, 24);
beaglebone_config_ddr();
diff --git a/arch/arm/boards/pcm051/lowlevel.c
b/arch/arm/boards/pcm051/lowlevel.c
index f4a1742..dd06c6a 100644
--- a/arch/arm/boards/pcm051/lowlevel.c
+++ b/arch/arm/boards/pcm051/lowlevel.c
@@ -159,7 +159,7 @@ void pcm051_sram_init(void)
u32 regVal, uart_base;
/* Setup the PLLs and the clocks for the peripherals */
- pll_init(MPUPLL_M_600);
+ pll_init(MPUPLL_M_600, 25);
pcm051_config_ddr();
diff --git a/arch/arm/mach-omap/am33xx_clock.c
b/arch/arm/mach-omap/am33xx_clock.c
index 9928e9f..c6cae42 100644
--- a/arch/arm/mach-omap/am33xx_clock.c
+++ b/arch/arm/mach-omap/am33xx_clock.c
@@ -156,7 +156,7 @@ static void per_clocks_enable(void)
while (__raw_readl(CM_PER_SPI1_CLKCTRL) != PRCM_MOD_EN);
}
-static void mpu_pll_config(int mpupll_M)
+static void mpu_pll_config(int mpupll_M, int osc)
{
u32 clkmode, clksel, div_m2;
@@ -170,7 +170,7 @@ static void mpu_pll_config(int mpupll_M)
while(__raw_readl(CM_IDLEST_DPLL_MPU) != 0x0100);
clksel = clksel (~0x7);
- clksel = clksel | ((mpupll_M 0x8) | MPUPLL_N);
+ clksel = clksel | ((mpupll_M 0x8) | (osc - 1));
__raw_writel(clksel, CM_CLKSEL_DPLL_MPU);
div_m2 = div_m2 ~0x1f;
@@ -183,7 +183,7 @@ static void mpu_pll_config(int mpupll_M)
while(__raw_readl(CM_IDLEST_DPLL_MPU) != 0x1);
}
-static void core_pll_config(void)
+static void core_pll_config(int osc)
{
u32 clkmode, clksel, div_m4, div_m5, div_m6;
@@ -199,7 +199,7 @@ static void core_pll_config(void)
while(__raw_readl(CM_IDLEST_DPLL_CORE) != 0x0100);
clksel = clksel (~0x7);
- clksel = clksel | ((COREPLL_M 0x8) | COREPLL_N);
+ clksel = clksel | ((COREPLL_M 0x8) | (osc - 1));
__raw_writel(clksel, CM_CLKSEL_DPLL_CORE);
div_m4 = div_m4 ~0x1f;
@@ -221,7 +221,7 @@ static void core_pll_config(void)
while(__raw_readl(CM_IDLEST_DPLL_CORE) != 0x1);
}
-static void per_pll_config(void)
+static void per_pll_config(int osc)
{
u32 clkmode, clksel, div_m2;
@@ -235,7 +235,7 @@ static void per_pll_config(void)
while(__raw_readl(CM_IDLEST_DPLL_PER) != 0x0100);
clksel = clksel (~0x7);
- clksel = clksel | ((PERPLL_M 0x8) | PERPLL_N);
+ clksel = clksel | ((PERPLL_M 0x8) | (osc - 1));
__raw_writel(clksel, CM_CLKSEL_DPLL_PER);
div_m2 = div_m2 ~0x7f;
@@ -248,7 +248,7 @@ static void per_pll_config(void)
while(__raw_readl(CM_IDLEST_DPLL_PER) != 0x1);
}
-static void ddr_pll_config(void)
+static void ddr_pll_config(int osc)
{
u32 clkmode, clksel, div_m2;
@@ -263,7 +263,7 @@ static void ddr_pll_config(void)
while ((__raw_readl(CM_IDLEST_DPLL_DDR) 0x0100) != 0x0100);
clksel = clksel (~0x7);
- clksel = clksel | ((DDRPLL_M 0x8) | DDRPLL_N);
+ clksel = clksel | ((DDRPLL_M 0x8) | (osc - 1));
__raw_writel(clksel, CM_CLKSEL_DPLL_DDR);
div_m2 = div_m2 0xFFE0;
@@ -294,12 +294,12 @@ void enable_ddr_clocks(void)
/*
* Configure the PLL/PRCM for necessary peripherals
*/
-void pll_init(int mpupll_M)
+void pll_init(int mpupll_M, int osc)
{
- mpu_pll_config(mpupll_M);
- core_pll_config();
- per_pll_config();
- ddr_pll_config();
+ mpu_pll_config(mpupll_M, osc);
+ core_pll_config(osc);
+ per_pll_config(osc);
+ ddr_pll_config(osc);
/* Enable the required interconnect clocks */
interface_clocks_enable();
/* Enable power domain transition */
diff --git a/arch/arm/mach-omap/include/mach/am33xx-clock.h
b/arch/arm/mach-omap/include/mach/am33xx-clock.h
index 968509e..6035da6 100644
--- a/arch/arm/mach-omap/include/mach/am33xx-clock.h
+++ b/arch/arm/mach-omap/include/mach/am33xx-clock.h
@@ -23,20 +23,16 @@
/* Put the pll config values over here */
-#define OSC24
-
/* MAIN PLL Fdll = 1 GHZ, */
#define MPUPLL_M_500 500 /* 125 * n */
#define
Re: [PATCH] AM33xx: Make OSC frequency board depended
On Tue, 2013-08-20 at 14:10 +0200, Teresa Gámez wrote: The oscillator frequency varies on different AM33xx boards. Pass the osc frequency from lowlevel board code to set the correct one on every board. Signed-off-by: Teresa Gámez t.ga...@phytec.de --- arch/arm/boards/beaglebone/lowlevel.c |2 +- arch/arm/boards/pcm051/lowlevel.c |2 +- arch/arm/mach-omap/am33xx_clock.c | 26 arch/arm/mach-omap/include/mach/am33xx-clock.h |8 +-- 4 files changed, 16 insertions(+), 22 deletions(-) Looks good, thanks. Reviewed-by: Jan Luebbe j...@pengutronix.de -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: Porting BareBox to Variscite iMX6 SOM
Thank you Sascha for the additional information in your earlier post! Your comments on the imx-image method got me looking at the menuconfig options and I located a simple mistake I had made when changing other options (while manually editing some files, I had somehow managed to inadvertently disable the support internal boot option). After fixing this, everything now works as I would expect. So, I now have the Variscite iMX6 SOM booted directly from SD to the BareBox shell on UART1. Now I just have to start pulling in all the other devices and getting them configured properly! ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
