[PATCH v2 1/2] ARM: add minimal support for the Freescale Quad UDOO Board

[Raphaël POGGI]

Adding minimal support for the UDOO board.

For more information about the board: http://www.udoo.org/

Signed-off-by: Raphael Poggi 
---
 arch/arm/boards/Makefile  |   1 +
 arch/arm/boards/udoo/Makefile |   3 +
 arch/arm/boards/udoo/board.c  | 204 ++
 arch/arm/boards/udoo/env/config-board |   6 +
 arch/arm/boards/udoo/flash-header-mx6-udoo.imxcfg | 104 +++
 arch/arm/boards/udoo/lowlevel.c   |  17 ++
 arch/arm/configs/imx_v7_defconfig |   1 +
 arch/arm/dts/Makefile |   4 +-
 arch/arm/dts/imx6q-udoo.dts   |  22 +++
 arch/arm/dts/imx6qdl-udoo.dtsi| 111 
 arch/arm/mach-imx/Kconfig |   5 +
 images/Makefile.imx   |   5 +
 12 files changed, 482 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boards/udoo/Makefile
 create mode 100644 arch/arm/boards/udoo/board.c
 create mode 100644 arch/arm/boards/udoo/env/config-board
 create mode 100644 arch/arm/boards/udoo/flash-header-mx6-udoo.imxcfg
 create mode 100644 arch/arm/boards/udoo/lowlevel.c
 create mode 100644 arch/arm/dts/imx6q-udoo.dts
 create mode 100644 arch/arm/dts/imx6qdl-udoo.dtsi

diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index befddd0..a45adee 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -91,6 +91,7 @@ obj-$(CONFIG_MACH_TX25)   += 
karo-tx25/
 obj-$(CONFIG_MACH_TX28)+= karo-tx28/
 obj-$(CONFIG_MACH_TX51)+= karo-tx51/
 obj-$(CONFIG_MACH_TX53)+= karo-tx53/
+obj-$(CONFIG_MACH_UDOO) += udoo/
 obj-$(CONFIG_MACH_USB_A9260)   += usb-a926x/
 obj-$(CONFIG_MACH_USB_A9263)   += usb-a926x/
 obj-$(CONFIG_MACH_USB_A9G20)   += usb-a926x/
diff --git a/arch/arm/boards/udoo/Makefile b/arch/arm/boards/udoo/Makefile
new file mode 100644
index 000..ae17789
--- /dev/null
+++ b/arch/arm/boards/udoo/Makefile
@@ -0,0 +1,3 @@
+obj-y += board.o flash-header-mx6-udoo.dcd.o
+extra-y += flash-header-mx6-udoo.dcd.S flash-header-mx6-udoo.dcd
+lwl-y += lowlevel.o
diff --git a/arch/arm/boards/udoo/board.c b/arch/arm/boards/udoo/board.c
new file mode 100644
index 000..5853f36
--- /dev/null
+++ b/arch/arm/boards/udoo/board.c
@@ -0,0 +1,204 @@
+/*
+ * Copyright (C) 2014 Raphaël Poggi
+ * Copyright (C) 2012 Steffen Trumtrar, Pengutronix
+ *
+ * based on arch/arm/boards/freescale-mx6-arm2/board.c
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static iomux_v3_cfg_t udoo_enet_gpio_pads_1[] = {
+   MX6Q_PAD_ENET_MDIO__ENET_MDIO   | 
MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL),
+   MX6Q_PAD_ENET_MDC__ENET_MDC | 
MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL),
+   MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC  | 
MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL),
+   MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0  | 
MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL),
+   MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1  | 
MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL),
+   MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2  | 
MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL),
+   MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3  | 
MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL),
+   MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL| 
MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL),
+   MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK  | 
MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL),
+   MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC  | 
MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL),
+   /* RGMII reset */
+   /* alimentazione ethernet*/
+   MX6Q_PAD_EIM_EB3__GPIO_2_31 | MUX_PAD_CTRL(NO_PAD_CTRL),
+   /* pin 32 - 1 - (MODE0) all */
+   MX6Q_PAD_RGMII_RD0__GPIO_6_25   | MUX_PAD_CTRL(NO_PAD_CTRL),
+   /* pin 31 - 1 - (MODE1) all */
+   MX6Q_PAD_RGMII_RD1__GPIO_6_27   | MUX_PAD_CTRL(NO_PAD_CTRL),
+   /* pin 28 - 1 - (MODE2) all */
+   MX6Q_PAD_RGMII_RD2__GPIO_6_28   | MUX_PAD_CTRL(NO_PAD_CTRL),
+   /* pin 27 - 1 - (MODE3) all */
+  

[PATCH 2/2] ARM: Rework device tree of UDOO Board to be more flexible.

[Raphaël POGGI]

Device tree of UDOO Board have to be more flexible.
There are a dual imx6 and a quad imx6 boards, with this patch
we can have a same device tree file as a base: arch/arm/dts/imx6qdl-udoo.dtsi
and an other device tree file for specific configuration depending of the board.

Signed-off-by: Raphael Poggi 
---
 arch/arm/boards/udoo/board.c   | 6 +++---
 arch/arm/dts/imx6q-udoo.dts| 3 ++-
 arch/arm/dts/imx6qdl-udoo.dtsi | 5 +++--
 3 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/arch/arm/boards/udoo/board.c b/arch/arm/boards/udoo/board.c
index 5853f36..3cbc0f5 100644
--- a/arch/arm/boards/udoo/board.c
+++ b/arch/arm/boards/udoo/board.c
@@ -166,7 +166,7 @@ static void udoo_epit_init(void)
 
 static int udoo_devices_init(void)
 {
-   if (!of_machine_is_compatible("fsl,imx6q-udoo"))
+   if (!of_machine_is_compatible("udoo,imx6qdl-udoo"))
   return 0;
 
setup_iomux_wdog();
@@ -181,7 +181,7 @@ device_initcall(udoo_devices_init);
 
 static int udoo_coredevices_init(void)
 {
-   if (!of_machine_is_compatible("fsl,imx6q-udoo"))
+   if (!of_machine_is_compatible("udoo,imx6qdl-udoo"))
   return 0;
 
phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
@@ -192,7 +192,7 @@ coredevice_initcall(udoo_coredevices_init);
 
 static int udoo_postcore_init(void)
 {
-   if (!of_machine_is_compatible("fsl,imx6q-udoo"))
+   if (!of_machine_is_compatible("udoo,imx6qdl-udoo"))
   return 0;
 
imx6_init_lowlevel();
diff --git a/arch/arm/dts/imx6q-udoo.dts b/arch/arm/dts/imx6q-udoo.dts
index 2e95978..106a0be 100644
--- a/arch/arm/dts/imx6q-udoo.dts
+++ b/arch/arm/dts/imx6q-udoo.dts
@@ -13,10 +13,11 @@
 
 /dts-v1/;
 
+#include "imx6q.dtsi"
 #include "imx6qdl-udoo.dtsi"
 
 / {
model = "Freescale i.MX6 Quad UDOO Board";
-   compatible = "fsl,imx6q-udoo", "fsl,imx6q";
+   compatible = "udoo,imx6q-udoo", "udoo,imx6qdl-udoo", "fsl,imx6q";
 };
 
diff --git a/arch/arm/dts/imx6qdl-udoo.dtsi b/arch/arm/dts/imx6qdl-udoo.dtsi
index 6220751..4cb6572 100644
--- a/arch/arm/dts/imx6qdl-udoo.dtsi
+++ b/arch/arm/dts/imx6qdl-udoo.dtsi
@@ -11,12 +11,13 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-#include "imx6q.dtsi"
-
 #include 
 #include 
 
 / {
+   model = "Freescale i.MX6 UDOO Board";
+   compatible = "udoo,imx6qdl-udoo", "fsl,imx6q";
+
chosen {
linux,stdout-path = &uart2;
 
-- 
1.8.3.2


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[PATCH v2 7/8] tegra: set AHB clock rate early

[Lucas Stach]

Avoids glitches in later starup phases.

Signed-off-by: Lucas Stach 
---
 arch/arm/mach-tegra/include/mach/tegra20-car.h | 4 
 arch/arm/mach-tegra/tegra_avp_init.c   | 3 +++
 2 files changed, 7 insertions(+)

diff --git a/arch/arm/mach-tegra/include/mach/tegra20-car.h 
b/arch/arm/mach-tegra/include/mach/tegra20-car.h
index a5441de..161e3d8 100644
--- a/arch/arm/mach-tegra/include/mach/tegra20-car.h
+++ b/arch/arm/mach-tegra/include/mach/tegra20-car.h
@@ -112,6 +112,10 @@
 #define CRC_SUPER_SDIV_DIVISOR_SHIFT   0
 #define CRC_SUPER_SDIV_DIVISOR_MASK(0xff << CRC_SUPER_SDIV_DIVISOR_SHIFT)
 
+#define CRC_CLK_SYSTEM_RATE0x030
+#define CRC_CLK_SYSTEM_RATE_AHB_SHIFT  4
+#define CRC_CLK_SYSTEM_RATE_APB_SHIFT  0
+
 #define CRC_CLK_CPU_CMPLX  0x04c
 #define CRC_CLK_CPU_CMPLX_CPU3_CLK_STP (1 << 11)
 #define CRC_CLK_CPU_CMPLX_CPU2_CLK_STP (1 << 10)
diff --git a/arch/arm/mach-tegra/tegra_avp_init.c 
b/arch/arm/mach-tegra/tegra_avp_init.c
index 9f8ccf3..4dd1330 100644
--- a/arch/arm/mach-tegra/tegra_avp_init.c
+++ b/arch/arm/mach-tegra/tegra_avp_init.c
@@ -149,6 +149,9 @@ static void start_cpu0_clocks(void)
   TEGRA_CLK_RESET_BASE + CRC_SCLK_BURST_POLICY);
writel(CRC_SUPER_SDIV_ENB, TEGRA_CLK_RESET_BASE + CRC_SUPER_SCLK_DIV);
 
+   writel(1 << CRC_CLK_SYSTEM_RATE_AHB_SHIFT,
+  TEGRA_CLK_RESET_BASE + CRC_CLK_SYSTEM_RATE);
+
/* deassert clock stop for cpu 0 */
reg = readl(TEGRA_CLK_RESET_BASE + CRC_CLK_CPU_CMPLX);
reg &= ~CRC_CLK_CPU_CMPLX_CPU0_CLK_STP;
-- 
1.8.5.3


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[PATCH v2 8/8] tegra: add Tegra3 startup

[Lucas Stach]

Sets up MSELECT to let main CPUs talk to peripheral devices and starts
high performance A9 CPU cluster.

Signed-off-by: Lucas Stach 
---
 arch/arm/mach-tegra/include/mach/tegra30-car.h  | 31 
 arch/arm/mach-tegra/include/mach/tegra30-flow.h | 23 +++
 arch/arm/mach-tegra/tegra_avp_init.c| 38 -
 3 files changed, 91 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-tegra/include/mach/tegra30-car.h
 create mode 100644 arch/arm/mach-tegra/include/mach/tegra30-flow.h

diff --git a/arch/arm/mach-tegra/include/mach/tegra30-car.h 
b/arch/arm/mach-tegra/include/mach/tegra30-car.h
new file mode 100644
index 000..ce11060
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/tegra30-car.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2014 Lucas Stach 
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ */
+
+/* Register definitions */
+#define CRC_CLK_OUT_ENB_V  0x360
+#define CRC_CLK_OUT_ENB_V_MSELECT  (1 << 3)
+
+#define CRC_CLK_SOURCE_MSEL0x3b4
+#define CRC_CLK_SOURCE_MSEL_SRC_SHIFT  30
+#define CRC_CLK_SOURCE_MSEL_SRC_PLLP   0
+#define CRC_CLK_SOURCE_MSEL_SRC_PLLC   1
+#define CRC_CLK_SOURCE_MSEL_SRC_PLLM   2
+#define CRC_CLK_SOURCE_MSEL_SRC_CLKM   3
+
+#define CRC_RST_DEV_V_SET  0x430
+#define CRC_RST_DEV_V_MSELECT  (1 << 3)
+
+#define CRC_RST_DEV_V_CLR  0x434
diff --git a/arch/arm/mach-tegra/include/mach/tegra30-flow.h 
b/arch/arm/mach-tegra/include/mach/tegra30-flow.h
new file mode 100644
index 000..50a3030
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/tegra30-flow.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2014 Lucas Stach 
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ */
+
+#define FLOW_HALT_CPU_EVENTS   0x000
+#define FLOW_MODE_NONE 0
+#define FLOW_MODE_STOP 2
+
+#define FLOW_CLUSTER_CONTROL   0x02c
+#define FLOW_CLUSTER_CONTROL_ACTIVE_G  (0 << 0)
+#define FLOW_CLUSTER_CONTROL_ACTIVE_LP (1 << 0)
diff --git a/arch/arm/mach-tegra/tegra_avp_init.c 
b/arch/arm/mach-tegra/tegra_avp_init.c
index 4dd1330..3314db4 100644
--- a/arch/arm/mach-tegra/tegra_avp_init.c
+++ b/arch/arm/mach-tegra/tegra_avp_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2013 Lucas Stach 
+ * Copyright (C) 2013-2014 Lucas Stach 
  *
  * Partly based on code (C) Copyright 2010-2011
  * NVIDIA Corporation 
@@ -23,6 +23,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 /* instruct the PMIC to enable the CPU power rail */
 static void enable_maincomplex_powerrail(void)
@@ -84,6 +86,12 @@ static struct pll_config pllx_config_table[][4] = {
{1000, 12, 0, 12},  /* OSC 12.0 MHz */
{1000, 26, 0, 12},  /* OSC 26.0 MHz */
}, /* TEGRA 20 */
+   {
+   {862, 8,  0, 8},
+   {583, 8,  0, 4},
+   {700, 6,  0, 8},
+   {700, 13, 0, 8},
+   }, /* TEGRA 30 */
 };
 
 static void init_pllx(void)
@@ -152,6 +160,20 @@ static void start_cpu0_clocks(void)
writel(1 << CRC_CLK_SYSTEM_RATE_AHB_SHIFT,
   TEGRA_CLK_RESET_BASE + CRC_CLK_SYSTEM_RATE);
 
+   if (tegra_get_chiptype() >= TEGRA30) {
+   /* init MSELECT */
+   writel(CRC_RST_DEV_V_MSELECT,
+  TEGRA_CLK_RESET_BASE + CRC_RST_DEV_V_SET);
+   writel((CRC_CLK_SOURCE_MSEL_SRC_PLLP <<
+  CRC_CLK_SOURCE_MSEL_SRC_SHIFT) | 2,
+  TEGRA_CLK_RESET_BASE + CRC_CLK_SOURCE_MSEL);
+   writel(CRC_CLK_OUT_ENB_V_MSELECT,
+  TEGRA_CLK_RESET_BASE + CRC_CLK_OUT_ENB_V);
+   tegra_ll_delay_usec(3);
+   writel(CRC_RST_DEV_V_MSELECT,
+  TEGRA_CLK_RESET_BASE + CRC_RST_DEV_V_CLR);
+   }
+
/* deassert clock stop for cpu 0 */
reg =

[PATCH v2 5/8] tegra: add Tegra3 to relevant lowlevel functions

[Lucas Stach]

Signed-off-by: Lucas Stach 
---
 arch/arm/mach-tegra/include/mach/lowlevel.h | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/mach-tegra/include/mach/lowlevel.h 
b/arch/arm/mach-tegra/include/mach/lowlevel.h
index 85ab7ef..b39e30e 100644
--- a/arch/arm/mach-tegra/include/mach/lowlevel.h
+++ b/arch/arm/mach-tegra/include/mach/lowlevel.h
@@ -62,6 +62,7 @@ u32 tegra_get_odmdata(void)
 enum tegra_chiptype {
TEGRA_UNK_REV = -1,
TEGRA20 = 0,
+   TEGRA30 = 1,
 };
 
 static __always_inline
@@ -75,6 +76,9 @@ enum tegra_chiptype tegra_get_chiptype(void)
case 0x20:
return TEGRA20;
break;
+   case 0x30:
+   return TEGRA30;
+   break;
default:
return TEGRA_UNK_REV;
break;
@@ -88,6 +92,9 @@ int tegra_get_num_cores(void)
case TEGRA20:
return 2;
break;
+   case TEGRA30:
+   return 4;
+   break;
default:
return 0;
break;
-- 
1.8.5.3


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[PATCH v2 6/8] tegra: add lowlevel DVC

[Lucas Stach]

Allows to talk to external PMIC devices to bring up CPU rail.

Signed-off-by: Lucas Stach 
---
 arch/arm/mach-tegra/include/mach/lowlevel-dvc.h | 72 +
 arch/arm/mach-tegra/include/mach/lowlevel.h |  7 ++-
 arch/arm/mach-tegra/include/mach/tegra20-car.h  |  8 +++
 3 files changed, 86 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-tegra/include/mach/lowlevel-dvc.h

diff --git a/arch/arm/mach-tegra/include/mach/lowlevel-dvc.h 
b/arch/arm/mach-tegra/include/mach/lowlevel-dvc.h
new file mode 100644
index 000..f7f6328
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/lowlevel-dvc.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (C) 2014 Lucas Stach 
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ */
+
+#include 
+#include "mach/tegra20-car.h"
+#include "mach/lowlevel.h"
+
+static __always_inline
+void tegra_dvc_init(void)
+{
+   int div;
+   u32 reg;
+
+   /* reset DVC controller and enable clock */
+   writel(CRC_RST_DEV_H_DVC, TEGRA_CLK_RESET_BASE + CRC_RST_DEV_H_SET);
+   reg = readl(TEGRA_CLK_RESET_BASE + CRC_CLK_OUT_ENB_H);
+   reg |= CRC_CLK_OUT_ENB_H_DVC;
+   writel(reg, TEGRA_CLK_RESET_BASE + CRC_CLK_OUT_ENB_H);
+
+   /* set DVC I2C clock source to CLK_M and aim for 100kHz I2C clock */
+   div = ((tegra_get_osc_clock() * 3) >> 22) - 1;
+   writel((div) | (3 << 30),
+  TEGRA_CLK_RESET_BASE + CRC_CLK_SOURCE_DVC);
+
+   /* clear DVC reset */
+   tegra_ll_delay_usec(3);
+   writel(CRC_RST_DEV_H_DVC, TEGRA_CLK_RESET_BASE + CRC_RST_DEV_H_CLR);
+}
+
+#define TEGRA_I2C_CNFG 0x00
+#define TEGRA_I2C_CMD_ADDR00x04
+#define TEGRA_I2C_CMD_DATA10x0c
+#define TEGRA_I2C_SEND_2_BYTES 0x0a02
+
+static __always_inline
+void tegra_dvc_write_addr(u32 addr, u32 config)
+{
+   writel(addr, TEGRA_DVC_BASE + TEGRA_I2C_CMD_ADDR0);
+   writel(config, TEGRA_DVC_BASE + TEGRA_I2C_CNFG);
+}
+
+static __always_inline
+void tegra_dvc_write_data(u32 data, u32 config)
+{
+   writel(data, TEGRA_DVC_BASE + TEGRA_I2C_CMD_DATA1);
+   writel(config, TEGRA_DVC_BASE + TEGRA_I2C_CNFG);
+}
+
+static inline __attribute__((always_inline))
+void tegra30_tps65911_cpu_rail_enable(void)
+{
+   tegra_dvc_write_addr(0x5a, 2);
+   /* reg 28, 600mV + (35-3) * 12,5mV = 1,0V */
+   tegra_dvc_write_data(0x2328, TEGRA_I2C_SEND_2_BYTES);
+   tegra_ll_delay_usec(1000);
+   /* reg 27, VDDctrl enable */
+   tegra_dvc_write_data(0x0127, TEGRA_I2C_SEND_2_BYTES);
+   tegra_ll_delay_usec(10 * 1000);
+}
diff --git a/arch/arm/mach-tegra/include/mach/lowlevel.h 
b/arch/arm/mach-tegra/include/mach/lowlevel.h
index b39e30e..0fad195 100644
--- a/arch/arm/mach-tegra/include/mach/lowlevel.h
+++ b/arch/arm/mach-tegra/include/mach/lowlevel.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2013 Lucas Stach 
+ * Copyright (C) 2013-2014 Lucas Stach 
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -21,6 +21,9 @@
  * be used by both the main CPU complex (ARMv7) and the AVP (ARMv4).
  */
 
+#ifndef __TEGRA_LOWLEVEL_H
+#define __TEGRA_LOWLEVEL_H
+
 #include 
 #include 
 #include 
@@ -251,3 +254,5 @@ void tegra_avp_reset_vector(uint32_t boarddata);
 
 /* reset vector for the main CPU complex */
 void tegra_maincomplex_entry(void);
+
+#endif /* __TEGRA_LOWLEVEL_H */
diff --git a/arch/arm/mach-tegra/include/mach/tegra20-car.h 
b/arch/arm/mach-tegra/include/mach/tegra20-car.h
index 64873d7..a5441de 100644
--- a/arch/arm/mach-tegra/include/mach/tegra20-car.h
+++ b/arch/arm/mach-tegra/include/mach/tegra20-car.h
@@ -46,6 +46,9 @@
 #define CRC_CLK_OUT_ENB_L_AC97 (1 << 3)
 #define CRC_CLK_OUT_ENB_L_CPU  (1 << 0)
 
+#define CRC_CLK_OUT_ENB_H  0x014
+#define CRC_CLK_OUT_ENB_H_DVC  (1 << 15)
+
 #define CRC_CCLK_BURST_POLICY  0x020
 #define CRC_CCLK_BURST_POLICY_SYS_STATE_SHIFT  28
 #define CRC_CCLK_BURST_POLICY_SYS_STATE_FIQ8
@@ -273,6 +276,11 @@
 
 #define CRC_RST_DEV_L_CLR  0x304
 
+#define CRC_RST_DEV_H_SET  0x308
+#define CRC_RST_DEV_H_DVC  (1 << 15)
+
+#define CRC_RST_DEV_H_CLR  0x30c
+
 #define CRC_RST_CPU_CMPLX_SET  0x340
 
 #define CRC_RST_CPU_CMPLX_CLR  0x344
-- 
1.8.5.3


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[PATCH v2 1/8] tegra: add -fno-jump-tables to lowlevel code

[Lucas Stach]

Lowlevel code runs when not relocated yet, so we have to make extra sure
not to emit jump-tables with absolute adresses when evaluating switch
statements.

Signed-off-by: Lucas Stach 
---
 arch/arm/mach-tegra/Makefile | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 0fa8430..791d5d4 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -1,5 +1,5 @@
-CFLAGS_tegra_avp_init.o := -mcpu=arm7tdmi -march=armv4t
-CFLAGS_pbl-tegra_avp_init.o := -mcpu=arm7tdmi -march=armv4t
+CFLAGS_tegra_avp_init.o := -mcpu=arm7tdmi -march=armv4t -fno-jump-tables
+CFLAGS_pbl-tegra_avp_init.o := -mcpu=arm7tdmi -march=armv4t -fno-jump-tables
 lwl-y += tegra_avp_init.o
 lwl-y += tegra_maincomplex_init.o
 obj-y += tegra20.o
-- 
1.8.5.3


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[PATCH v2 2/8] tegra: lowlevel: switch to __always_inline macro

[Lucas Stach]

Signed-off-by: Lucas Stach 
---
 arch/arm/mach-tegra/include/mach/lowlevel.h | 17 +
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-tegra/include/mach/lowlevel.h 
b/arch/arm/mach-tegra/include/mach/lowlevel.h
index 472348a..fb06e4f 100644
--- a/arch/arm/mach-tegra/include/mach/lowlevel.h
+++ b/arch/arm/mach-tegra/include/mach/lowlevel.h
@@ -21,6 +21,7 @@
  * be used by both the main CPU complex (ARMv7) and the AVP (ARMv4).
  */
 
+#include 
 #include 
 #include 
 #include 
@@ -40,7 +41,7 @@
 #define T20_ODMDATA_UARTID_SHIFT   15
 #define T20_ODMDATA_UARTID_MASK(7 << T20_ODMDATA_UARTID_SHIFT)
 
-static inline __attribute__((always_inline))
+static __always_inline
 u32 tegra_get_odmdata(void)
 {
u32 bctsize, bctptr, odmdata;
@@ -63,7 +64,7 @@ enum tegra_chiptype {
TEGRA20 = 0,
 };
 
-static inline __attribute__((always_inline))
+static __always_inline
 enum tegra_chiptype tegra_get_chiptype(void)
 {
u32 hidrev;
@@ -78,7 +79,7 @@ enum tegra_chiptype tegra_get_chiptype(void)
}
 }
 
-static inline __attribute__((always_inline))
+static __always_inline
 int tegra_get_num_cores(void)
 {
switch (tegra_get_chiptype()) {
@@ -92,7 +93,7 @@ int tegra_get_num_cores(void)
 }
 
 /* Runtime data */
-static inline __attribute__((always_inline))
+static __always_inline
 int tegra_cpu_is_maincomplex(void)
 {
u32 tag0;
@@ -102,7 +103,7 @@ int tegra_cpu_is_maincomplex(void)
return (tag0 & 0xff) == 0x55;
 }
 
-static inline __attribute__((always_inline))
+static __always_inline
 uint32_t tegra20_get_ramsize(void)
 {
switch ((tegra_get_odmdata() & T20_ODMDATA_RAMSIZE_MASK) >>
@@ -125,7 +126,7 @@ static long uart_id_to_base[] = {
TEGRA_UARTE_BASE,
 };
 
-static inline __attribute__((always_inline))
+static __always_inline
 long tegra20_get_debuguart_base(void)
 {
u32 odmdata;
@@ -152,7 +153,7 @@ long tegra20_get_debuguart_base(void)
 #define CRC_OSC_CTRL_OSC_FREQ_SHIFT30
 #define CRC_OSC_CTRL_OSC_FREQ_MASK (0x3 << CRC_OSC_CTRL_OSC_FREQ_SHIFT)
 
-static inline unsigned __attribute__((always_inline))
+static __always_inline
 int tegra_get_osc_clock(void)
 {
u32 osc_ctrl = readl(TEGRA_CLK_RESET_BASE + CRC_OSC_CTRL);
@@ -172,7 +173,7 @@ int tegra_get_osc_clock(void)
}
 }
 
-static inline __attribute__((always_inline))
+static __always_inline
 void tegra_cpu_lowlevel_setup(void)
 {
uint32_t r;
-- 
1.8.5.3


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[PATCH v2 0/8] Lowlevel Tegra3 support

[Lucas Stach]

This is the very basic Tegra3 support. All highlevel things
like pinmux and other drivers still missing.

Allows to start the high performance CPU cluster on Tegra3
and start executing code there.

v2: Use __always_inline compiler macro.

Lucas Stach (8):
  tegra: add -fno-jump-tables to lowlevel code
  tegra: lowlevel: switch to __always_inline macro
  tegra: add break to switch statements
  tegra: add lowlevel delay function
  tegra: add Tegra3 to relevant lowlevel functions
  tegra: add lowlevel DVC
  tegra: set AHB clock rate early
  tegra: add Tegra3 startup

 arch/arm/mach-tegra/Makefile|  4 +-
 arch/arm/mach-tegra/include/mach/lowlevel-dvc.h | 72 +
 arch/arm/mach-tegra/include/mach/lowlevel.h | 85 ++---
 arch/arm/mach-tegra/include/mach/tegra20-car.h  | 12 
 arch/arm/mach-tegra/include/mach/tegra30-car.h  | 31 +
 arch/arm/mach-tegra/include/mach/tegra30-flow.h | 23 +++
 arch/arm/mach-tegra/tegra_avp_init.c| 46 -
 7 files changed, 261 insertions(+), 12 deletions(-)
 create mode 100644 arch/arm/mach-tegra/include/mach/lowlevel-dvc.h
 create mode 100644 arch/arm/mach-tegra/include/mach/tegra30-car.h
 create mode 100644 arch/arm/mach-tegra/include/mach/tegra30-flow.h

-- 
1.8.5.3


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[PATCH v2 3/8] tegra: add break to switch statements

[Lucas Stach]

Avoids a possible miscompilation.

Signed-off-by: Lucas Stach 
---
 arch/arm/mach-tegra/include/mach/lowlevel.h | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/mach-tegra/include/mach/lowlevel.h 
b/arch/arm/mach-tegra/include/mach/lowlevel.h
index fb06e4f..20de1b2 100644
--- a/arch/arm/mach-tegra/include/mach/lowlevel.h
+++ b/arch/arm/mach-tegra/include/mach/lowlevel.h
@@ -74,8 +74,10 @@ enum tegra_chiptype tegra_get_chiptype(void)
switch ((hidrev & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT) {
case 0x20:
return TEGRA20;
+   break;
default:
return TEGRA_UNK_REV;
+   break;
}
 }
 
@@ -110,11 +112,14 @@ uint32_t tegra20_get_ramsize(void)
T20_ODMDATA_RAMSIZE_SHIFT) {
case 1:
return SZ_256M;
+   break;
default:
case 2:
return SZ_512M;
+   break;
case 3:
return SZ_1G;
+   break;
}
 }
 
@@ -162,14 +167,19 @@ int tegra_get_osc_clock(void)
CRC_OSC_CTRL_OSC_FREQ_SHIFT) {
case 0:
return 1300;
+   break;
case 1:
return 1920;
+   break;
case 2:
return 1200;
+   break;
case 3:
return 2600;
+   break;
default:
return 0;
+   break;
}
 }
 
-- 
1.8.5.3


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[PATCH v2 4/8] tegra: add lowlevel delay function

[Lucas Stach]

For proper startup we need to give clocks and IO signals some time to
stabilize. Tegra2 got away without them, but Tegra3 seems to be a bit
pickier.

Signed-off-by: Lucas Stach 
---
 arch/arm/mach-tegra/include/mach/lowlevel.h | 44 +
 arch/arm/mach-tegra/tegra_avp_init.c|  5 
 2 files changed, 49 insertions(+)

diff --git a/arch/arm/mach-tegra/include/mach/lowlevel.h 
b/arch/arm/mach-tegra/include/mach/lowlevel.h
index 20de1b2..85ab7ef 100644
--- a/arch/arm/mach-tegra/include/mach/lowlevel.h
+++ b/arch/arm/mach-tegra/include/mach/lowlevel.h
@@ -183,6 +183,49 @@ int tegra_get_osc_clock(void)
}
 }
 
+#define TIMER_CNTR_1US 0x00
+#define TIMER_USEC_CFG 0x04
+
+static __always_inline
+void tegra_ll_delay_setup(void)
+{
+   u32 reg;
+
+   /*
+* calibrate timer to run at 1MHz
+* TIMERUS_USEC_CFG selects the scale down factor with bits [0:7]
+* representing the divisor and bits [8:15] representing the dividend
+* each in n+1 form.
+*/
+   switch (tegra_get_osc_clock()) {
+   case 1200:
+   reg = 0x000b;
+   break;
+   case 1300:
+   reg = 0x000c;
+   break;
+   case 1920:
+   reg = 0x045f;
+   break;
+   case 2600:
+   reg = 0x0019;
+   break;
+   default:
+   reg = 0;
+   break;
+   }
+
+   writel(reg, TEGRA_TMRUS_BASE + TIMER_USEC_CFG);
+}
+
+static __always_inline
+void tegra_ll_delay_usec(int delay)
+{
+   int timeout = (int)readl(TEGRA_TMRUS_BASE + TIMER_CNTR_1US) + delay;
+
+   while ((int)readl(TEGRA_TMRUS_BASE + TIMER_CNTR_1US) - timeout < 0);
+}
+
 static __always_inline
 void tegra_cpu_lowlevel_setup(void)
 {
@@ -193,6 +236,7 @@ void tegra_cpu_lowlevel_setup(void)
r &= ~0x1f;
r |= 0xd3;
__asm__ __volatile__("msr cpsr, %0" : : "r"(r));
+   tegra_ll_delay_setup();
 }
 
 /* reset vector for the AVP, to be called from board reset vector */
diff --git a/arch/arm/mach-tegra/tegra_avp_init.c 
b/arch/arm/mach-tegra/tegra_avp_init.c
index 2c2d6fc..9f8ccf3 100644
--- a/arch/arm/mach-tegra/tegra_avp_init.c
+++ b/arch/arm/mach-tegra/tegra_avp_init.c
@@ -158,6 +158,9 @@ static void start_cpu0_clocks(void)
reg = readl(TEGRA_CLK_RESET_BASE + CRC_CLK_OUT_ENB_L);
reg |= CRC_CLK_OUT_ENB_L_CPU;
writel(reg, TEGRA_CLK_RESET_BASE + CRC_CLK_OUT_ENB_L);
+
+   /* give clocks some time to settle */
+   tegra_ll_delay_usec(300);
 }
 
 static void maincomplex_powerup(void)
@@ -175,6 +178,8 @@ static void maincomplex_powerup(void)
reg = readl(TEGRA_PMC_BASE + PMC_REMOVE_CLAMPING_CMD);
reg |= PMC_REMOVE_CLAMPING_CMD_CPU;
writel(reg, TEGRA_PMC_BASE + PMC_REMOVE_CLAMPING_CMD);
+
+   tegra_ll_delay_usec(1000);
}
 }
 void tegra_avp_reset_vector(uint32_t boarddata)
-- 
1.8.5.3


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Re: [PATCH 1/2] ARM: i.MX6: saresd: set USB PHY and DR mode

[Robert Schwebel]

Typo in subject (sa"b"re").

rsc

On Mon, Feb 17, 2014 at 01:04:11PM +0100, Lucas Stach wrote:
> Signed-off-by: Lucas Stach 
> ---
>  arch/arm/dts/imx6qdl-sabresd.dtsi | 4 
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/arm/dts/imx6qdl-sabresd.dtsi 
> b/arch/arm/dts/imx6qdl-sabresd.dtsi
> index 346e32a22c56..78c9fd54ebd3 100644
> --- a/arch/arm/dts/imx6qdl-sabresd.dtsi
> +++ b/arch/arm/dts/imx6qdl-sabresd.dtsi
> @@ -280,6 +280,8 @@
>  
>  &usbh1 {
>   vbus-supply = <®_usb_h1_vbus>;
> + phy_type = "utmi";
> + dr_mode = "host";
>   status = "okay";
>  };
>  
> @@ -287,6 +289,8 @@
>   vbus-supply = <®_usb_otg_vbus>;
>   pinctrl-names = "default";
>   pinctrl-0 = <&pinctrl_usbotg>;
> + phy_type = "utmi";
> + dr_mode = "host";
>   disable-over-current;
>   status = "okay";
>  };
> -- 
> 1.8.5.3
> 
> 
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Re: Devicetree Maintenance in barebox

[Jason Cooper]

On Fri, Feb 07, 2014 at 08:13:32AM +0100, Sascha Hauer wrote:
> Hi All,
> 
> It's becoming more obvious that devicetree maintenance is painful
> because we have to sync them to the kernel regularly. My hope was that
> this would get simpler once the devicetrees get their own repository
> outside the kernel, but it seems that won't happen anytime soon.

As one of my todo items from last week's devicetree irc meeting, I've
now proposed just that:

  http://article.gmane.org/gmane.comp.devicetree.compiler/14

Also, cross-posted to devicetree and devicetree-spec.

thx,

Jason.

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Re: [PATCH] Adding minimal support for the UDOO board.

[Raphaël Poggi]

Hum I think I have understand, in fact there is 2 differents type of
UDOO board, one quad and one dual. So I think it is a good idea to add
in imx6qdl-udoo.dtsi a compatible string like "udoo,imx6qdl"
and in the imx6q-udoo.dts a compatible string like "udoo,imx6q" is this right ?

Thanks.

Raphaël

2014-02-17 19:54 GMT+01:00 Alexander Shiyan :
> Hello.
>
> Понедельник, 17 февраля 2014, 19:34 +01:00 от Raphaël Poggi 
> :
>>
>> Hi Alexander,
>>
>> I do not understand the problem with "compatible " :
>>
>> > > +#include "imx6qdl-udoo.dtsi"
>> > > +
>> > > +/ {
>> > > +   model = "Freescale i.MX6 Quad UDOO Board";
>> > > +   compatible = "fsl,imx6q-udoo", "fsl,imx6q";
>> > > +};
>> > > +
>>
>> Can you explain me ?
>
> Please answer the question: What describes imx6qdl-udoo.dtsi and
> what describes imx6q-udoo.dts ?
> I suspect for imx6qdl-udoo.dtsi is a module and imx6q-udoo.dts is a board
> uses this module.
> Kernel (as an our bootloader) may contain specific code used for the
> module and/or for a board. To find out should this code to be executed
> or not, some compatibility tests is used.
> So, you should add compatible string "AAA" to the module DT description
> and strings "BBB", "AAA" to the board.
> I hope I have explained clearly. :)
>
> Thanks.
> ---

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Re: [PATCH] Adding minimal support for the UDOO board.

[Alexander Shiyan]

Hello.

Понедельник, 17 февраля 2014, 19:34 +01:00 от Raphaël Poggi 
:
> 
> Hi Alexander,
> 
> I do not understand the problem with "compatible " :
> 
> > > +#include "imx6qdl-udoo.dtsi"
> > > +
> > > +/ {
> > > +       model = "Freescale i.MX6 Quad UDOO Board";
> > > +       compatible = "fsl,imx6q-udoo", "fsl,imx6q";
> > > +};
> > > +
> 
> Can you explain me ?

Please answer the question: What describes imx6qdl-udoo.dtsi and
what describes imx6q-udoo.dts ?
I suspect for imx6qdl-udoo.dtsi is a module and imx6q-udoo.dts is a board
uses this module.
Kernel (as an our bootloader) may contain specific code used for the
module and/or for a board. To find out should this code to be executed
or not, some compatibility tests is used.
So, you should add compatible string "AAA" to the module DT description
and strings "BBB", "AAA" to the board.
I hope I have explained clearly. :)

Thanks.
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Re: [PATCH 2/7] tegra: add break to switch statements

[Lucas Stach]

Am Montag, den 17.02.2014, 07:53 +0100 schrieb Sascha Hauer:
> On Thu, Feb 13, 2014 at 11:32:46PM +0100, Lucas Stach wrote:
> > Avoids a possible miscompilation.
> > 
> > Signed-off-by: Lucas Stach 
> > ---
> >  arch/arm/mach-tegra/include/mach/lowlevel.h | 10 ++
> >  1 file changed, 10 insertions(+)
> > 
> > diff --git a/arch/arm/mach-tegra/include/mach/lowlevel.h 
> > b/arch/arm/mach-tegra/include/mach/lowlevel.h
> > index 472348a..9081b1c 100644
> > --- a/arch/arm/mach-tegra/include/mach/lowlevel.h
> > +++ b/arch/arm/mach-tegra/include/mach/lowlevel.h
> > @@ -73,8 +73,10 @@ enum tegra_chiptype tegra_get_chiptype(void)
> > switch ((hidrev & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT) {
> > case 0x20:
> > return TEGRA20;
> > +   break;
> > default:
> > return TEGRA_UNK_REV;
> > +   break;
> 
> What kind of miscompilation other than a compiler bug are you thinking
> of? Have you seen that this patch changes anything?
> 

I have to admit that I haven't investigated the issue closely, but this
actually makes the difference between working and nonworking when adding
in the Tegra3 case later on.

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[PATCH 2/2] ARM: i.MX6: sabresd: switch to multi-image

[Lucas Stach]

Signed-off-by: Lucas Stach 
---
 arch/arm/Makefile  |   1 -
 arch/arm/boards/freescale-mx6-sabresd/Makefile |   3 +-
 arch/arm/boards/freescale-mx6-sabresd/board.c  |  33 ++
 .../flash-header-mx6-sabresd.imxcfg| 128 +
 .../freescale-mx6-sabresd/flash-header.imxcfg  | 128 -
 arch/arm/boards/freescale-mx6-sabresd/lowlevel.c   |  11 +-
 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/imx6q-sabresd.dts |   5 +
 arch/arm/dts/imx6qdl-sabresd.dtsi  |  13 +++
 arch/arm/mach-imx/Kconfig  |   8 +-
 images/Makefile.imx|   5 +
 11 files changed, 178 insertions(+), 158 deletions(-)
 create mode 100644 
arch/arm/boards/freescale-mx6-sabresd/flash-header-mx6-sabresd.imxcfg
 delete mode 100644 arch/arm/boards/freescale-mx6-sabresd/flash-header.imxcfg

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 87e8d4a08bfd..daea9da526c9 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -210,7 +210,6 @@ barebox.imximg: $(KBUILD_BINARY) FORCE
 
 boarddir = $(srctree)/arch/arm/boards
 imxcfg-$(CONFIG_MACH_FREESCALE_MX53_SMD) += 
$(boarddir)/freescale-mx53-smd/flash-header.imxcfg
-imxcfg-$(CONFIG_MACH_SABRESD) += 
$(boarddir)/freescale-mx6-sabresd/flash-header.imxcfg
 imxcfg-$(CONFIG_MACH_MX6Q_ARM2) += 
$(boarddir)/freescale-mx6-arm2/flash-header.imxcfg
 imxcfg-$(CONFIG_MACH_CCMX51) += $(boarddir)/ccxmx51/flash-header.imxcfg
 imxcfg-$(CONFIG_MACH_TX51) += 
$(boarddir)/karo-tx51/flash-header-karo-tx51.imxcfg
diff --git a/arch/arm/boards/freescale-mx6-sabresd/Makefile 
b/arch/arm/boards/freescale-mx6-sabresd/Makefile
index 01c7a259e9a5..f72c641e17d1 100644
--- a/arch/arm/boards/freescale-mx6-sabresd/Makefile
+++ b/arch/arm/boards/freescale-mx6-sabresd/Makefile
@@ -1,2 +1,3 @@
-obj-y += board.o
+obj-y += board.o flash-header-mx6-sabresd.dcd.o
+extra-y += flash-header-mx6-sabresd.dcd.S flash-header-mx6-sabresd.dcd
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/freescale-mx6-sabresd/board.c 
b/arch/arm/boards/freescale-mx6-sabresd/board.c
index c87b55538423..4e4ce7a01583 100644
--- a/arch/arm/boards/freescale-mx6-sabresd/board.c
+++ b/arch/arm/boards/freescale-mx6-sabresd/board.c
@@ -40,14 +40,6 @@
 #define PHY_ID_AR8031  0x004dd074
 #define AR_PHY_ID_MASK 0x
 
-static int sabresd_mem_init(void)
-{
-   arm_add_mem_device("ram0", 0x1000, SZ_1G);
-
-   return 0;
-}
-mem_initcall(sabresd_mem_init);
-
 static int ar8031_phy_fixup(struct phy_device *dev)
 {
u16 val;
@@ -71,27 +63,21 @@ static int ar8031_phy_fixup(struct phy_device *dev)
return 0;
 }
 
-static void sabresd_phy_reset(void)
-{
-   /* Reset AR8031 PHY */
-   gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
-   udelay(500);
-   gpio_set_value(IMX_GPIO_NR(1, 25), 1);
-}
-
 static int sabresd_devices_init(void)
 {
+   if (!of_machine_is_compatible("fsl,imx6q-sabresd"))
+   return 0;
+
armlinux_set_architecture(3980);
 
-   devfs_add_partition("disk0", 0, SZ_1M, DEVFS_PARTITION_FIXED, "self0");
-   devfs_add_partition("disk0", SZ_1M + SZ_1M, SZ_512K, 
DEVFS_PARTITION_FIXED, "env0");
return 0;
 }
 device_initcall(sabresd_devices_init);
 
 static int sabresd_coredevices_init(void)
 {
-   sabresd_phy_reset();
+   if (!of_machine_is_compatible("fsl,imx6q-sabresd"))
+   return 0;
 
phy_register_fixup_for_uid(PHY_ID_AR8031, AR_PHY_ID_MASK,
ar8031_phy_fixup);
@@ -102,14 +88,17 @@ static int sabresd_coredevices_init(void)
  * Do this before the fec initializes but after our
  * gpios are available.
  */
-fs_initcall(sabresd_coredevices_init);
+coredevice_initcall(sabresd_coredevices_init);
 
-static int sabresd_core_init(void)
+static int sabresd_postcore_init(void)
 {
+   if (!of_machine_is_compatible("fsl,imx6q-sabresd"))
+   return 0;
+
imx6_init_lowlevel();
 
barebox_set_hostname("sabresd");
 
return 0;
 }
-core_initcall(sabresd_core_init);
+postcore_initcall(sabresd_postcore_init);
diff --git 
a/arch/arm/boards/freescale-mx6-sabresd/flash-header-mx6-sabresd.imxcfg 
b/arch/arm/boards/freescale-mx6-sabresd/flash-header-mx6-sabresd.imxcfg
new file mode 100644
index ..21f217cdf32b
--- /dev/null
+++ b/arch/arm/boards/freescale-mx6-sabresd/flash-header-mx6-sabresd.imxcfg
@@ -0,0 +1,128 @@
+loadaddr 0x1000
+soc imx6
+dcdofs 0x400
+wm 32 0x20e05a8 0x0030
+wm 32 0x20e05b0 0x0030
+wm 32 0x20e0524 0x0030
+wm 32 0x20e051c 0x0030
+
+wm 32 0x20e0518 0x0030
+wm 32 0x20e050c 0x0030
+wm 32 0x20e05b8 0x0030
+wm 32 0x20e05c0 0x0030
+
+wm 32 0x20e05ac 0x00020030
+wm 32 0x20e05b4 0x00020030
+wm 32 0x20e0528 0x00020030
+wm 32 0x20e0520 0x00020030
+
+wm 32 0x20e0514 0x00020030
+wm 32 0x20e0510 0x00020030
+wm 32 0x20e05bc 0x00020030
+wm 32 0x20e05c4 0x0

[PATCH 1/2] ARM: i.MX6: saresd: set USB PHY and DR mode

[Lucas Stach]

Signed-off-by: Lucas Stach 
---
 arch/arm/dts/imx6qdl-sabresd.dtsi | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/dts/imx6qdl-sabresd.dtsi 
b/arch/arm/dts/imx6qdl-sabresd.dtsi
index 346e32a22c56..78c9fd54ebd3 100644
--- a/arch/arm/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/dts/imx6qdl-sabresd.dtsi
@@ -280,6 +280,8 @@
 
 &usbh1 {
vbus-supply = <®_usb_h1_vbus>;
+   phy_type = "utmi";
+   dr_mode = "host";
status = "okay";
 };
 
@@ -287,6 +289,8 @@
vbus-supply = <®_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
+   phy_type = "utmi";
+   dr_mode = "host";
disable-over-current;
status = "okay";
 };
-- 
1.8.5.3


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Re: [PATCH] read_file: Use read_full

[Uwe Kleine-König]

On Thu, Feb 13, 2014 at 10:12:53AM +0100, Sascha Hauer wrote:
> At least NFS does not fulfill read requests > 1024 bytes at once.
> Use read_full in read_file as read doesn't guarantee that the
> whole request can be read at once.
> 
> Signed-off-by: Sascha Hauer 
Acked-by: Uwe Kleine-König 

Thanks
Uwe

-- 
Pengutronix e.K.   | Uwe Kleine-König|
Industrial Linux Solutions | http://www.pengutronix.de/  |

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Re: [PATCH] Adding minimal support for the UDOO board.

[Sascha Hauer]

On Mon, Feb 17, 2014 at 09:00:20AM +0100, Raphaël Poggi wrote:
>Ok I will do this today.�
>By the way, can you tell me how I can reply to this thread using git
>send-email to submit patch ? Like that I don't have to open a new thread
>in the mailing list.�
>I am a beginner in open source community and my question can sound stupid
>for you...
>Thanks
>Rapha

You can do this by adding --in-reply-to  to the git send-email
commandline. Anyway, I prefer new versions of patches to be sent as a
new thread, possibly adding a [PATCH v2] prefix. When a thread contains
multiple versions of the same patch it's often hard to find the most
recent patches when it comes to applying them.

Since you are new to open source community, the most important rule is:
Don't give up when people are nagging about small details of your patch.
At least this means people are looking at your stuff ;)

Sascha


> 
>�014-02-17 8:48 GMT+01:00 Sascha Hauer <[1]s.ha...@pengutronix.de>:
> 
>  Hi Rapha�l,
>  On Sun, Feb 16, 2014 at 02:20:08PM -0800, Rapha�l POGGI wrote:
>  > From: Raphael Poggi <[2]poggi.r...@gmail.com>
>  >
>  > For more information about the board: [3]http://www.udoo.org/
>  >
>  > Signed-off-by: Raphael Poggi <[4]poggi.r...@gmail.com>
> 
>  Your patch contains several coding style issues, most significantly:
>  Please use tabs for indendation, not spaces. You should run
>  scripts/[5]checkpatch.pl over your patch next time, it catches most of
>  the issues.
>  Otherwise your patch looks fine and I applied it after fixing the coding
>  style.
> 
>  Thanks
>  �Sascha
>  > ---
>  > �arch/arm/boards/Makefile � � � � � � � � � � � � �| � 1 +
>  > �arch/arm/boards/udoo/Makefile � � � � � � � � � � | � 3 +
>  > �arch/arm/boards/udoo/board.c � � � � � � � � � � �| 204
>  ++
>  > �arch/arm/boards/udoo/env/config-board � � � � � � | � 6 +
>  > �arch/arm/boards/udoo/flash-header-mx6-udoo.imxcfg | 104 +++
>  > �arch/arm/boards/udoo/lowlevel.c � � � � � � � � � | �17 ++
>  > �arch/arm/configs/imx_v7_defconfig � � � � � � � � | � 1 +
>  > �arch/arm/dts/Makefile � � � � � � � � � � � � � � | � 4 +-
>  > �arch/arm/dts/imx6q-udoo.dts � � � � � � � � � � � | �23 +++
>  > �arch/arm/dts/imx6qdl-udoo.dtsi � � � � � � � � � �| 108 
>  > �arch/arm/mach-imx/Kconfig � � � � � � � � � � � � | � 5 +
>  > �images/Makefile.imx � � � � � � � � � � � � � � � | � 5 +
>  > �12 files changed, 480 insertions(+), 1 deletion(-)
>  > �create mode 100644 arch/arm/boards/udoo/Makefile
>  > �create mode 100644 arch/arm/boards/udoo/board.c
>  > �create mode 100644 arch/arm/boards/udoo/env/config-board
>  > �create mode 100644 arch/arm/boards/udoo/flash-header-mx6-udoo.imxcfg
>  > �create mode 100644 arch/arm/boards/udoo/lowlevel.c
>  > �create mode 100644 arch/arm/dts/imx6q-udoo.dts
>  > �create mode 100644 arch/arm/dts/imx6qdl-udoo.dtsi
>  >
>  > diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
>  > index befddd0..a45adee 100644
>  > --- a/arch/arm/boards/Makefile
>  > +++ b/arch/arm/boards/Makefile
>  > @@ -91,6 +91,7 @@ obj-$(CONFIG_MACH_TX25) � � � � � � � � � � � � � �
>  += karo-tx25/
>  > �obj-$(CONFIG_MACH_TX28) � � � � � � � � � � � � � � �+= karo-tx28/
>  > �obj-$(CONFIG_MACH_TX51) � � � � � � � � � � � � � � �+= karo-tx51/
>  > �obj-$(CONFIG_MACH_TX53) � � � � � � � � � � � � � � �+= karo-tx53/
>  > +obj-$(CONFIG_MACH_UDOO) � � � � � � += udoo/
>  > �obj-$(CONFIG_MACH_USB_A9260) � � � � � � � � += usb-a926x/
>  > �obj-$(CONFIG_MACH_USB_A9263) � � � � � � � � += usb-a926x/
>  > �obj-$(CONFIG_MACH_USB_A9G20) � � � � � � � � += usb-a926x/
>  > diff --git a/arch/arm/boards/udoo/Makefile
>  b/arch/arm/boards/udoo/Makefile
>  > new file mode 100644
>  > index 000..ae17789
>  > --- /dev/null
>  > +++ b/arch/arm/boards/udoo/Makefile
>  > @@ -0,0 +1,3 @@
>  > +obj-y += board.o flash-header-mx6-udoo.dcd.o
>  > +extra-y += flash-header-mx6-udoo.dcd.S flash-header-mx6-udoo.dcd
>  > +lwl-y += lowlevel.o
>  > diff --git a/arch/arm/boards/udoo/board.c
>  b/arch/arm/boards/udoo/board.c
>  > new file mode 100644
>  > index 000..8302609
>  > --- /dev/null
>  > +++ b/arch/arm/boards/udoo/board.c
>  > @@ -0,0 +1,204 @@
>  > +/*
>  > + * Copyright (C) 2014 Rapha�l Poggi
>  > + * Copyright (C) 2012 Steffen Trumtrar, Pengutronix
>  > + *
>  > + * based on arch/arm/boards/freescale-mx6-arm2/board.c
>  > + *
>  > + * This program is free software; you can redistribute it and/or
>  > + * modify it under the terms of the GNU General Public License as
>  > + * published by the Free Software Foundation; either version 2 of
>  > + * the License, or (at your option) any later vers

Re: [PATCH] Adding minimal support for the UDOO board.

[Alexander Shiyan]

Понедельник, 17 февраля 2014, 8:48 +01:00 от Sascha Hauer 
:
> Hi Raphaël,
> 
> On Sun, Feb 16, 2014 at 02:20:08PM -0800, Raphaël POGGI wrote:
> > From: Raphael Poggi 
> > 
> > For more information about the board: http://www.udoo.org/
> > 
> > Signed-off-by: Raphael Poggi 
> 
> Your patch contains several coding style issues, most significantly:
> Please use tabs for indendation, not spaces. You should run
> scripts/checkpatch.pl over your patch next time, it catches most of
> the issues.
> Otherwise your patch looks fine and I applied it after fixing the coding
> style.
...
> > +++ b/arch/arm/dts/imx6q-udoo.dts
> > @@ -0,0 +1,23 @@
> > +/*
> > + * Copyright 2014 Raphaël Poggi
> > + * Copyright 2012 Freescale Semiconductor, Inc.
> > + * Copyright 2011 Linaro Ltd.
> > + *
> > + * The code contained herein is licensed under the GNU General Public
> > + * License. You may obtain a copy of the GNU General Public License
> > + * Version 2 or later at the following locations:
> > + *
> > + * http://www.opensource.org/licenses/gpl-license.html
> > + * http://www.gnu.org/copyleft/gpl.html
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "imx6q.dtsi"

Most likely you not need to include "imx6q.dtsi".

> > +#include "imx6qdl-udoo.dtsi"
> > +
> > +/ {
> > +   model = "Freescale i.MX6 Quad UDOO Board";
> > +   compatible = "fsl,imx6q-udoo", "fsl,imx6q";
> > +};
> > +
> > diff --git a/arch/arm/dts/imx6qdl-udoo.dtsi b/arch/arm/dts/imx6qdl-udoo.dtsi
> > new file mode 100644
> > index 000..c705684
> > --- /dev/null
> > +++ b/arch/arm/dts/imx6qdl-udoo.dtsi
> > @@ -0,0 +1,108 @@
> > +/*
> > + * Copyright 2014 Raphaël Poggi
> > + * Copyright 2011 Freescale Semiconductor, Inc.
> > + * Copyright 2011 Linaro Ltd.
> > + *
> > + * The code contained herein is licensed under the GNU General Public
> > + * License. You may obtain a copy of the GNU General Public License
> > + * Version 2 or later at the following locations:
> > + *
> > + * http://www.opensource.org/licenses/gpl-license.html
> > + * http://www.gnu.org/copyleft/gpl.html
> > + */
> > +#include 
> > +#include 
> > +
> > +/ {

compatible ?

> > +   chosen {
> > +   linux,stdout-path = &uart2;
> > +
> > +   };
> > +
> > +   memory {
> > +   reg = <0x1000 0x4000>;
> > +   };
> > +
> > +   regulators {
> > +   compatible = "simple-bus";
> > +   #address-cells = <1>;
> > +   #size-cells = <0>;
> > +
> > +   reg_2p5v: regulator@0 {
> > +   compatible = "regulator-fixed";
> > +   reg = <0>;
> > +   regulator-name = "2P5V";
> > +   regulator-min-microvolt = <250>;
> > +   regulator-max-microvolt = <250>;
> > +   regulator-always-on;
> > +   };
> > +
> > +   reg_3p3v: regulator@1 {
> > +   compatible = "regulator-fixed";
> > +   reg = <1>;
> > +   regulator-name = "3P3V";
> > +   regulator-min-microvolt = <330>;
> > +   regulator-max-microvolt = <330>;
> > +   regulator-always-on;
> > +   };
> > +
> > +   reg_usb_otg_vbus: regulator@2 {
> > +   compatible = "regulator-fixed";
> > +   reg = <2>;
> > +   regulator-name = "usb_otg_vbus";
> > +   regulator-min-microvolt = <500>;
> > +   regulator-max-microvolt = <500>;
> > +   gpio = <&gpio3 22 0>;
> > +   enable-active-high;

gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;

...

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