Re: [PATCH 0/4] Orion GBE fixes and Marvell PHY driver
On Tue, Jun 24, 2014 at 12:18:07PM +0200, Sebastian Hesselbarth wrote: This patch set comprises some fixes and improvements related with ethernet support on Marvell Orion SoC based boards. Patch 1 adds a check for ePAPR standard phy-connection-type property to of_get_phy_mode. Patch 2 resolves a device name conflict on orion-gbe port names when using more than one controller instance. Patch 3 extends ethernet serial port setup to also check for delayed RGMII interface modes. Patch 4 finally adds a driver for Marvell PHYs with 88E1121R as a first PHY driver. The patches have been tested on Globalscale Guruplug. For ethernet, the board needs a DT fix that has been picked up for Linux v3.16-rc yesterday and should be available in barebox soon. For the second ethernet port, barebox is still missing pinctrl for Kirkwood, but that is next on my polish private branches for submission-TODO list. Sebastian Hesselbarth (4): of: net: respect phy-connection-type property net: orion: generate unique port device names net: orion-gbe: extend RGMII detection to delayed modes net: phy: add support for Marvell PHY drivers Applied, thanks Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH 1/2] sama5d3x: fix HSMC MODE register offset and add TIMINGS register
On Wed, Jun 25, 2014 at 09:45:49AM +0800, Bo Shen wrote:
Hi Matteo,
Thanks for your patch.
Hi Jean-Christophe PLAGNIOL-VILLARD,
For this patch series, can you give some comments (maybe the
question from I need more discussion)? Thanks.
On 06/24/2014 07:26 PM, Matteo Fortini wrote:
As stated in section 29.19.35 of SAMA5D3 Series Datasheet,
MODE register has offset 0x10 and at offset 0x0C there is
a TIMINGS register.
Signed-off-by: Matteo Fortini matteo.fort...@gmail.com
---
arch/arm/mach-at91/include/mach/at91sam9_smc.h | 35
+-
arch/arm/mach-at91/sam9_smc.c | 21
2 files changed, 55 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_smc.h
b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
index d5cf5f7..e4f0f54 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_smc.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
@@ -45,10 +45,24 @@ struct sam9_smc_config {
u8 tdf_cycles:4;
};
+struct sam9_smc_sama5d3_extra_config {
Nitpick: I am thinking another name, maybe: sama5d3_timing_config (?)
+/* Timings register */
+u8 tclr;
+u8 tadl;
+u8 tar;
+u8 ocms;
+u8 trr;
+u8 twb;
+u8 rbnsel;
+u8 nfsel;
+};
+
extern void sam9_smc_configure(int id, int cs, struct sam9_smc_config
*config);
extern void sam9_smc_read(int id, int cs, struct sam9_smc_config *config);
extern void sam9_smc_read_mode(int id, int cs, struct sam9_smc_config
*config);
extern void sam9_smc_write_mode(int id, int cs, struct sam9_smc_config
*config);
+
+extern void sam9_smc_sama5d3_configure(int id, int cs, struct
sam9_smc_config *config, struct sam9_smc_sama5d3_extra_config
*sama5d3_extra_config);
Ditto
#endif
#define AT91_SMC_SETUP 0x00/*
Setup Register for CS n */
@@ -77,7 +91,25 @@ extern void sam9_smc_write_mode(int id, int cs, struct
sam9_smc_config *config);
#defineAT91_SMC_NRDCYCLE (0x1ff 16)
/* Total Read Cycle Length */
#defineAT91_SMC_NRDCYCLE_(x) ((x) 16)
-#define AT91_SMC_MODE 0x0c/* Mode
Register for CS n */
+#define AT91_SMC_TIMINGS0x0c/* Timings
register for CS n */
+#define AT91_SMC_TCLR (0x0f0)
/* CLE to REN Low Delay */
+#define AT91_SMC_TCLR_(x) ((x) 0)
+#define AT91_SMC_TADL (0x0f4)
/* ALE to Data Start */
+#define AT91_SMC_TADL_(x) ((x) 4)
+#define AT91_SMC_TAR(0x0f8)
/* ALE to REN Low Delay */
+#define AT91_SMC_TAR_(x)((x) 8)
+#define AT91_SMC_OCMS (0x112)
/* Off Chip Memory Scrambling Enable */
+#define AT91_SMC_OCMS_(x) ((x) 12)
+#define AT91_SMC_TRR(0x0f 16)
/* Ready to REN Low Delay */
+#define AT91_SMC_TRR_(x)((x) 16)
+#define AT91_SMC_TWB(0x0f 24)
/* WEN High to REN to Busy */
+#define AT91_SMC_TWB_(x)((x) 24)
+#define AT91_SMC_RBNSEL (0x07 28)
/* Ready/Busy Line Selection */
+#define AT91_SMC_RBNSEL_(x) ((x) 28)
+#define AT91_SMC_NFSEL (0x01 31)
/* Nand Flash Selection */
+#define AT91_SMC_NFSEL_(x) ((x) 31)
+
+#define AT91_SMC_MODE ((at91_soc_initdata.type ==
AT91_SOC_SAMA5D3) ? 0x10 : 0x0c)/* Mode Register
for CS n */
Here make me thinking more, if new SoC added and MODE register's
offset is the same as sama5d3, then it will be:
(at91_soc_initdata.type == AT91_SOC_SAMA5D3) ||
(at91_soc_initdata.type == AT91_SOC_NEW1) || (at91_soc_initdata.type
== AT91_SOC_NEW2)
Will this be acceptable?
No.
I think two SoC specific defines, for example
#define AT91_SMC_MODE 0xc
#define AT91_SAMA5_SMC_MODE 0x10
and handling the differences in the code will scale better. I don't like
hiding SoC differences in defines like done in this patch. If there show
up even more differences a SoC specific struct with register offsets
might help.
Sascha
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Re: [PATCH 0/3] MVEBU SoC ID and revision detection
On Tue, Jun 24, 2014 at 01:45:33PM +0200, Sebastian Hesselbarth wrote: This patch set adds support for reading SoC ID and revision from PCIe controllers found on Marvell MVEBU SoCs. Patch 1 adds PCI bus specific OF address translation required for reg property parsing of PCIe controller nodes. Patch 2 selects above PCI OF address translation for MVEBU SoCs. Patch 3 adds common code to find and parse PCIe controller nodes from MVEBU SoC DT and read out SoC ID and revision registers. The patches are based on barebox next with latest MVEBU patches for cleanup and PBL images applied. They have been tested on Marvell Kirkwood, Dove, and Armada 370. Sebastian Hesselbarth (3): drivers: of: import PCI bus specific translator ARM: mvebu: select PCI specific DT bus translator ARM: mvebu: determine SoC id and revision from PCIe nodes Applied, thanks Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH v2] pinctrl: mvebu: add pinctrl drivers for Dove and Kirkwood
On Tue, Jun 24, 2014 at 12:43:48PM +0200, Sebastian Hesselbarth wrote:
This adds pinctrl drivers for Marvell Dove and Kirkwood SoCs based
on a common driver stub. This design is based on the corresponding
Linux driver and should ease additional drivers for Marvell Armada
SoCs.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
Applied with a small change:
+static int kirkwood_pinctrl_probe(struct device_d *dev)
+{
+ const struct of_device_id *match =
+ of_match_node(kirkwood_pinctrl_of_match, dev-device_node);
+ struct mvebu_pinctrl_soc_info *soc =
+ (struct mvebu_pinctrl_soc_info *)match-data;
+
+ mpp_base = dev_request_mem_region(dev, 0);
I added a return value check here. Not checking it means that the driver
could do NULL pointer dereferences during runtime.
I should really fix the places where the check is missing in the tree.
Sascha
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Re: [RFC 2/2] dns325: initial support for D-Link DNS-325
On Tue, Jun 24, 2014 at 01:54:07PM +0200, Sebastian Hesselbarth wrote: On 06/22/2014 10:34 PM, Alexander Aring wrote: This patch add a basic support for the D-Link DNS-325. Currently only booting via uart with kwboot is supported. The barebox kwboot utility doesn't work at the moment. Use kwboot utility from u-boot instead. Signed-off-by: Alexander Aring alex.ar...@gmail.com --- I got the kwbimage values from u-boot with change to work with the barebox kwboot utility. There is also a bug in u-boot kwbimage file which enables 256 MB on chip select 0 and 1. But the DNS-325 has 256 MB on chip select 0 only. This is fixed in this kwbimage file. Alexander, I posted a bunch of MVEBU related patches I had in my private branches. Can you respin your DNS-325 patch based on those? Sascha already applied Marvell MVEBU assorted fixes and cleanup and Convert MVEBU SoCs to DT and PBL_MULTI_IMAGE but they haven't appeared on barebox/next. You can wait a day or two or apply above series yourself. The other 3 pending patch sets are just more improvements but shouldn't (directly) influence your dns-325 support patches. All mvebu patches should now be in -next. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH] MIPS: mach-ath79: drop extra 'select HAVE_CLK'
On Wed, Jun 25, 2014 at 09:30:44AM +0400, Antony Pavlov wrote: We already have 'select COMMON_CLK' so 'select HAVE_CLK' is redundant. Signed-off-by: Antony Pavlov antonynpav...@gmail.com Applied, thanks Sascha --- arch/mips/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 9a240b7..dcd0e58 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -61,7 +61,6 @@ config MACH_MIPS_ATH79 select SYS_SUPPORTS_BIG_ENDIAN select CSRC_R4K_LIB select HAS_DEBUG_LL - select HAVE_CLK select COMMON_CLK select COMMON_CLK_OF_PROVIDER select CLKDEV_LOOKUP -- 1.9.2 ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH 4/4] arm: tegra: enable ARM errata workarounds
From: Lucas Stach l.st...@pengutronix.de
Signed-off-by: Lucas Stach l.st...@pengutronix.de
---
arch/arm/mach-tegra/tegra_maincomplex_init.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-tegra/tegra_maincomplex_init.c
b/arch/arm/mach-tegra/tegra_maincomplex_init.c
index 17490a4..4a362dd 100644
--- a/arch/arm/mach-tegra/tegra_maincomplex_init.c
+++ b/arch/arm/mach-tegra/tegra_maincomplex_init.c
@@ -18,6 +18,7 @@
#include sizes.h
#include asm/barebox-arm-head.h
#include asm/barebox-arm.h
+#include asm/errata.h
#include mach/lowlevel.h
#include mach/tegra20-pmc.h
#include mach/tegra20-car.h
@@ -30,6 +31,23 @@ void tegra_maincomplex_entry(void)
arm_cpu_lowlevel_init();
+ chiptype = tegra_get_chiptype();
+
+ /* enable ARM errata workarounds early */
+ switch (chiptype) {
+ case TEGRA20:
+ enable_arm_errata_716044_war();
+ enable_arm_errata_742230_war();
+ enable_arm_errata_751472_war();
+ break;
+ case TEGRA30:
+ enable_arm_errata_743622_war();
+ enable_arm_errata_751472_war();
+ break;
+ default:
+ break;
+ }
+
/* switch to PLLX */
writel(CRC_CCLK_BURST_POLICY_SYS_STATE_RUN
CRC_CCLK_BURST_POLICY_SYS_STATE_SHIFT |
@@ -38,8 +56,6 @@ void tegra_maincomplex_entry(void)
TEGRA_CLK_RESET_BASE + CRC_CCLK_BURST_POLICY);
writel(CRC_SUPER_CDIV_ENB, TEGRA_CLK_RESET_BASE + CRC_SUPER_CCLK_DIV);
- chiptype = tegra_get_chiptype();
-
if (chiptype = TEGRA114) {
asm(mrc p15, 1, %0, c9, c0, 2 : : r (reg));
reg = ~7;
@@ -51,6 +67,7 @@ void tegra_maincomplex_entry(void)
case TEGRA20:
rambase = 0x0;
ramsize = tegra20_get_ramsize();
+
break;
case TEGRA30:
case TEGRA124:
--
1.9.3
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[PATCH 2/4] arm: imx6: add cpu lowlevel init function
From: Lucas Stach l.st...@pengutronix.de
Enables all relevant errata workarounds for the
i.MX6 SoC.
Signed-off-by: Lucas Stach l.st...@pengutronix.de
---
arch/arm/mach-imx/Makefile | 1 +
arch/arm/mach-imx/cpu_init.c | 27 +++
arch/arm/mach-imx/include/mach/generic.h | 2 ++
3 files changed, 30 insertions(+)
create mode 100644 arch/arm/mach-imx/cpu_init.c
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 03e5b10..1d311a4 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -22,3 +22,4 @@ obj-$(CONFIG_BAREBOX_UPDATE) += imx-bbu-internal.o
obj-$(CONFIG_BAREBOX_UPDATE_IMX_EXTERNAL_NAND) += imx-bbu-external-nand.o
obj-$(CONFIG_BAREBOX_UPDATE_IMX6_NAND) += imx6-bbu-nand.o
pbl-y += esdctl.o
+lwl-y += cpu_init.o
diff --git a/arch/arm/mach-imx/cpu_init.c b/arch/arm/mach-imx/cpu_init.c
new file mode 100644
index 000..68eacf7
--- /dev/null
+++ b/arch/arm/mach-imx/cpu_init.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2014 Lucas Stach, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include asm/barebox-arm-head.h
+#include asm/errata.h
+
+void imx6_cpu_lowlevel_init(void)
+{
+ arm_cpu_lowlevel_init();
+
+ enable_arm_errata_742230_war();
+ enable_arm_errata_743622_war();
+ enable_arm_errata_751472_war();
+ enable_arm_errata_761320_war();
+ enable_arm_errata_794072_war();
+}
diff --git a/arch/arm/mach-imx/include/mach/generic.h
b/arch/arm/mach-imx/include/mach/generic.h
index 506b1da..505a542 100644
--- a/arch/arm/mach-imx/include/mach/generic.h
+++ b/arch/arm/mach-imx/include/mach/generic.h
@@ -33,6 +33,8 @@ int imx51_devices_init(void);
int imx53_devices_init(void);
int imx6_devices_init(void);
+void imx6_cpu_lowlevel_init(void);
+
/* There's a off-by-one betweem the gpio bank number and the gpiochip */
/* range e.g. GPIO_1_5 is gpio 5 under linux */
#define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr))
--
1.9.3
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[PATCH 3/4] arm: imx6: use imx6 specific cpu init function
From: Lucas Stach l.st...@pengutronix.de
Signed-off-by: Lucas Stach l.st...@pengutronix.de
---
arch/arm/boards/boundarydevices-nitrogen6x/lowlevel.c | 5 +++--
arch/arm/boards/datamodul-edm-qmx6/lowlevel.c | 3 ++-
arch/arm/boards/dfi-fs700-m60/lowlevel.c | 7 ---
arch/arm/boards/embest-riotboard/lowlevel.c | 2 +-
arch/arm/boards/freescale-mx6-arm2/lowlevel.c | 3 ++-
arch/arm/boards/freescale-mx6-sabrelite/lowlevel.c| 5 +++--
arch/arm/boards/freescale-mx6-sabresd/lowlevel.c | 3 ++-
arch/arm/boards/gk802/lowlevel.c | 3 ++-
arch/arm/boards/guf-santaro/lowlevel.c| 3 ++-
arch/arm/boards/phytec-phycard-imx6/lowlevel.c| 2 +-
arch/arm/boards/phytec-phyflex-imx6/lowlevel.c| 10 +-
arch/arm/boards/solidrun-hummingboard/lowlevel.c | 3 ++-
arch/arm/boards/tqma6x/lowlevel.c | 4 ++--
arch/arm/boards/udoo/lowlevel.c | 3 ++-
arch/arm/boards/variscite-mx6/lowlevel.c | 2 +-
15 files changed, 34 insertions(+), 24 deletions(-)
diff --git a/arch/arm/boards/boundarydevices-nitrogen6x/lowlevel.c
b/arch/arm/boards/boundarydevices-nitrogen6x/lowlevel.c
index 60a84ef..5371be6 100644
--- a/arch/arm/boards/boundarydevices-nitrogen6x/lowlevel.c
+++ b/arch/arm/boards/boundarydevices-nitrogen6x/lowlevel.c
@@ -1,5 +1,6 @@
#include common.h
#include sizes.h
+#include mach/generic.h
#include asm/barebox-arm-head.h
#include asm/barebox-arm.h
@@ -9,7 +10,7 @@ ENTRY_FUNCTION(start_imx6q_nitrogen6x_1g, r0, r1, r2)
{
void *fdt;
- arm_cpu_lowlevel_init();
+ imx6_cpu_lowlevel_init();
fdt = __dtb_imx6q_nitrogen6x_start - get_runtime_offset();
@@ -22,7 +23,7 @@ ENTRY_FUNCTION(start_imx6dl_nitrogen6x_1g, r0, r1, r2)
{
void *fdt;
- arm_cpu_lowlevel_init();
+ imx6_cpu_lowlevel_init();
fdt = __dtb_imx6dl_nitrogen6x_start - get_runtime_offset();
diff --git a/arch/arm/boards/datamodul-edm-qmx6/lowlevel.c
b/arch/arm/boards/datamodul-edm-qmx6/lowlevel.c
index b1ce4e9..914c275 100644
--- a/arch/arm/boards/datamodul-edm-qmx6/lowlevel.c
+++ b/arch/arm/boards/datamodul-edm-qmx6/lowlevel.c
@@ -21,6 +21,7 @@
#include asm/barebox-arm-head.h
#include asm/barebox-arm.h
#include mach/imx6-mmdc.h
+#include mach/generic.h
static void sdram_init(void)
{
@@ -142,7 +143,7 @@ ENTRY_FUNCTION(start_imx6_realq7, r0, r1, r2)
unsigned long sdram = 0x1000;
void *fdt;
- arm_cpu_lowlevel_init();
+ imx6_cpu_lowlevel_init();
arm_setup_stack(0x0094 - 8);
diff --git a/arch/arm/boards/dfi-fs700-m60/lowlevel.c
b/arch/arm/boards/dfi-fs700-m60/lowlevel.c
index 541e6c1..81b3530 100644
--- a/arch/arm/boards/dfi-fs700-m60/lowlevel.c
+++ b/arch/arm/boards/dfi-fs700-m60/lowlevel.c
@@ -21,6 +21,7 @@
#include asm/barebox-arm.h
#include mach/imx6-mmdc.h
#include mach/imx6-regs.h
+#include mach/generic.h
#include debug_ll.h
@@ -106,7 +107,7 @@ ENTRY_FUNCTION(start_imx6q_dfi_fs700_m60_6q_nanya, r0, r1,
r2)
void *fdt;
int i;
- arm_cpu_lowlevel_init();
+ imx6_cpu_lowlevel_init();
arm_setup_stack(0x0094 - 8);
@@ -125,7 +126,7 @@ ENTRY_FUNCTION(start_imx6q_dfi_fs700_m60_6q_micron, r0, r1,
r2)
void *fdt;
int i;
- arm_cpu_lowlevel_init();
+ imx6_cpu_lowlevel_init();
arm_setup_stack(0x0094 - 8);
@@ -148,7 +149,7 @@ ENTRY_FUNCTION(start_imx6dl_dfi_fs700_m60_6s, r0, r1, r2)
void *fdt;
int i;
- arm_cpu_lowlevel_init();
+ imx6_cpu_lowlevel_init();
arm_setup_stack(0x0092 - 8);
diff --git a/arch/arm/boards/embest-riotboard/lowlevel.c
b/arch/arm/boards/embest-riotboard/lowlevel.c
index 64edd61..c4ef287 100644
--- a/arch/arm/boards/embest-riotboard/lowlevel.c
+++ b/arch/arm/boards/embest-riotboard/lowlevel.c
@@ -30,7 +30,7 @@ ENTRY_FUNCTION(start_imx6s_riotboard, r0, r1, r2)
{
void *fdt;
- arm_cpu_lowlevel_init();
+ imx6_cpu_lowlevel_init();
if (IS_ENABLED(CONFIG_DEBUG_LL)) {
writel(0x4, 0x020e016c);
diff --git a/arch/arm/boards/freescale-mx6-arm2/lowlevel.c
b/arch/arm/boards/freescale-mx6-arm2/lowlevel.c
index 53783bb..5676711 100644
--- a/arch/arm/boards/freescale-mx6-arm2/lowlevel.c
+++ b/arch/arm/boards/freescale-mx6-arm2/lowlevel.c
@@ -2,9 +2,10 @@
#include sizes.h
#include asm/barebox-arm-head.h
#include asm/barebox-arm.h
+#include mach/generic.h
void __naked barebox_arm_reset_vector(void)
{
- arm_cpu_lowlevel_init();
+ imx6_cpu_lowlevel_init();
barebox_arm_entry(0x1000, SZ_2G, NULL);
}
diff --git a/arch/arm/boards/freescale-mx6-sabrelite/lowlevel.c
b/arch/arm/boards/freescale-mx6-sabrelite/lowlevel.c
index a154381..1b47965 100644
--- a/arch/arm/boards/freescale-mx6-sabrelite/lowlevel.c
+++ b/arch/arm/boards/freescale-mx6-sabrelite/lowlevel.c
@@
[PATCH 1/4] arm: add errata workarounds
From: Lucas Stach l.st...@pengutronix.de
Header only implementation, so they can be pulled
into the individual SoC cpu init functions.
Signed-off-by: Lucas Stach l.st...@pengutronix.de
---
arch/arm/include/asm/errata.h | 67 +++
1 file changed, 67 insertions(+)
create mode 100644 arch/arm/include/asm/errata.h
diff --git a/arch/arm/include/asm/errata.h b/arch/arm/include/asm/errata.h
new file mode 100644
index 000..e2ffd87
--- /dev/null
+++ b/arch/arm/include/asm/errata.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (C) 2014 Lucas Stach, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+static inline void enable_arm_errata_716044_war(void)
+{
+ __asm__ __volatile__ (
+ mrcp15, 0, r0, c1, c0, 0\n
+ orrr0, r0, #1 11\n
+ mcrp15, 0, r0, c1, c0, 0\n
+ );
+}
+
+static inline void enable_arm_errata_742230_war(void)
+{
+ __asm__ __volatile__ (
+ mrcp15, 0, r0, c15, c0, 1\n
+ orrr0, r0, #1 4\n
+ mcrp15, 0, r0, c15, c0, 1\n
+ );
+}
+
+static inline void enable_arm_errata_743622_war(void)
+{
+ __asm__ __volatile__ (
+ mrcp15, 0, r0, c15, c0, 1\n
+ orrr0, r0, #1 6\n
+ mcrp15, 0, r0, c15, c0, 1\n
+ );
+}
+
+static inline void enable_arm_errata_751472_war(void)
+{
+ __asm__ __volatile__ (
+ mrcp15, 0, r0, c15, c0, 1\n
+ orrr0, r0, #1 11\n
+ mcrp15, 0, r0, c15, c0, 1\n
+ );
+}
+
+static inline void enable_arm_errata_761320_war(void)
+{
+ __asm__ __volatile__ (
+ mrcp15, 0, r0, c15, c0, 1\n
+ orrr0, r0, #1 21\n
+ mcrp15, 0, r0, c15, c0, 1\n
+ );
+}
+
+static inline void enable_arm_errata_794072_war(void)
+{
+ __asm__ __volatile__ (
+ mrcp15, 0, r0, c15, c0, 1\n
+ orrr0, r0, #1 4\n
+ mcrp15, 0, r0, c15, c0, 1\n
+ );
+}
--
1.9.3
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Re: [PATCH v2] pinctrl: mvebu: add pinctrl drivers for Dove and Kirkwood
On 06/25/2014 08:56 AM, Sascha Hauer wrote:
On Tue, Jun 24, 2014 at 12:43:48PM +0200, Sebastian Hesselbarth wrote:
This adds pinctrl drivers for Marvell Dove and Kirkwood SoCs based
on a common driver stub. This design is based on the corresponding
Linux driver and should ease additional drivers for Marvell Armada
SoCs.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
Applied with a small change:
+static int kirkwood_pinctrl_probe(struct device_d *dev)
+{
+ const struct of_device_id *match =
+ of_match_node(kirkwood_pinctrl_of_match, dev-device_node);
+ struct mvebu_pinctrl_soc_info *soc =
+ (struct mvebu_pinctrl_soc_info *)match-data;
+
+ mpp_base = dev_request_mem_region(dev, 0);
I added a return value check here. Not checking it means that the driver
could do NULL pointer dereferences during runtime.
I should really fix the places where the check is missing in the tree.
Ok, thanks for catching it. Did you also apply the same fix
to Dove's pinctrl stub?
Sebastian
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Re: [PATCH v2] pinctrl: mvebu: add pinctrl drivers for Dove and Kirkwood
Hi,
I resend this mail. My last one was malformed, because I tried to
answert this mail via smartphone while boring lecture at university.
On Wed, Jun 25, 2014 at 08:56:15AM +0200, Sascha Hauer wrote:
On Tue, Jun 24, 2014 at 12:43:48PM +0200, Sebastian Hesselbarth wrote:
This adds pinctrl drivers for Marvell Dove and Kirkwood SoCs based
on a common driver stub. This design is based on the corresponding
Linux driver and should ease additional drivers for Marvell Armada
SoCs.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
Applied with a small change:
+static int kirkwood_pinctrl_probe(struct device_d *dev)
+{
+ const struct of_device_id *match =
+ of_match_node(kirkwood_pinctrl_of_match, dev-device_node);
+ struct mvebu_pinctrl_soc_info *soc =
+ (struct mvebu_pinctrl_soc_info *)match-data;
+
+ mpp_base = dev_request_mem_region(dev, 0);
I added a return value check here. Not checking it means that the driver
could do NULL pointer dereferences during runtime.
I should really fix the places where the check is missing in the tree.
I spotted this also at my last patch for print warning for resource
conflicts and I thought a zero base address is also valid for some
cases.
Thats why I didn't add checks on null.
What I mean is that the dev_request_mem_region API reference can return
NULL which is for example (void *)0x and is also valid. We
can't use this as error indicator.
Maybe we could change the API to:
int dev_request_mem_region_by_name(struct device_d *dev, void __iomem
**ptr, const char *name)
same for dev_request_mem_region. Then we can work with errno here and
set the old return via *ptr = foo. But would be a huge change in the API
or it's uncommon that somebody request iomem for NULL address... This
could happen for some memory locations.
- Alex
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Re: i.MX6 frame buffer inside barebox?
I just noticed that simplefb wouldn't work with i.MX6 anyway, even if I adapt it. When I setup the framebuffer from barebox and display a splash and then boot into Linux, then my framebuffer vanishes. Even when I don't have simplefb or ipu enabled. I think (!) the reason is the clock framework.The clocks for the IPU are turned off, and so I don't see anything anymore (this is, however, a wild assumption, I haven't checked it yet). However, I checked with an Oscillioscope that if I setup the backlight PWM (pwm0 in Barebox) and start Linux without CONFIG_PWM / CONFIG_PWM_IMX, then the PWM is turned off as soon as Linux has been started. Memory 0x208 shows in bit 0 that the PWM is still turned on. But as nothing comes out, it must be the clock. ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH FIXUP] pinctrl: mvebu: fixup mpp_base check
Sascha, unfortunately, your dev_request_mem_region fixup introduced a typo (map_base instead of mpp_base). I took the chance to also add a corresponding check for dove's pinctrl stub. Please squash into commmit 8d3f0c2496afe397667e35ff6b94153bcecdb6ad (pinctrl: mvebu: add pinctrl drivers for Dove and Kirkwood) Thanks! Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com --- Cc: Sascha Hauer s.ha...@pengutronix.de Cc: barebox@lists.infradead.org --- drivers/pinctrl/mvebu/dove.c | 2 ++ drivers/pinctrl/mvebu/kirkwood.c | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/mvebu/dove.c b/drivers/pinctrl/mvebu/dove.c index 420b573ad1b7..bd0a632f1fd4 100644 --- a/drivers/pinctrl/mvebu/dove.c +++ b/drivers/pinctrl/mvebu/dove.c @@ -708,6 +708,8 @@ static int dove_pinctrl_probe(struct device_d *dev) mpp_base = dev_request_mem_region(dev, 0); mpp4_base = dev_request_mem_region(dev, 1); + if (!mpp_base || !mpp4_base) + return -EBUSY; /* * Dove PMU does not have a stable binding, yet. diff --git a/drivers/pinctrl/mvebu/kirkwood.c b/drivers/pinctrl/mvebu/kirkwood.c index bde46acc0f4e..94ab10544279 100644 --- a/drivers/pinctrl/mvebu/kirkwood.c +++ b/drivers/pinctrl/mvebu/kirkwood.c @@ -437,7 +437,7 @@ static int kirkwood_pinctrl_probe(struct device_d *dev) (struct mvebu_pinctrl_soc_info *)match-data; mpp_base = dev_request_mem_region(dev, 0); - if (!map_base) + if (!mpp_base) return -EBUSY; return mvebu_pinctrl_probe(dev, soc); -- 2.0.0 ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH RFC 2/4] ARM: dts: add new USB nodes to Kirkwood Guruplug
Add new MVEBU usb controller nodes to Guruplug dts overlay to show
how it should be included upstream.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Cc: barebox@lists.infradead.org
Cc: Jason Cooper ja...@lakedaemon.net
Cc: Andrew Lunn and...@lunn.ch
Cc: Gregory Clement gregory.clem...@free-electrons.com
Cc: Thomas Petazzoni thomas.petazz...@free-electrons.com
Cc: Ezequiel Garcia ezequiel.gar...@free-electrons.com
---
arch/arm/dts/kirkwood-guruplug-server-plus-bb.dts | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm/dts/kirkwood-guruplug-server-plus-bb.dts
b/arch/arm/dts/kirkwood-guruplug-server-plus-bb.dts
index aba7c06160d0..eaf9869e9483 100644
--- a/arch/arm/dts/kirkwood-guruplug-server-plus-bb.dts
+++ b/arch/arm/dts/kirkwood-guruplug-server-plus-bb.dts
@@ -11,4 +11,24 @@
barebox,default-trigger = heartbeat;
};
};
+
+ ocp@f100 {
+ musb0: usb@5 {
+ compatible = marvell,mvebu-usb;
+ reg = 0x5 0x400;
+ interrupts = 19;
+ clocks = gate_clk 3;
+ usb-phy = usb_phy0;
+ dr_mode = host;
+ status = okay;
+ };
+
+ usb_phy0: phy@50400 {
+ compatible = marvell,mvebu-usb-phy-65nm;
+ reg = 0x50400 0x100;
+ clocks = gate_clk 3;
+ #phy-cells = 0;
+ status = okay;
+ };
+ };
};
--
2.0.0
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[PATCH RFC 4/4] ARM: dts: add new USB nodes to Armada 370 Mirabox
Add new MVEBU usb controller nodes to Mirabox dts overlay to show
how it should be included upstream.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Cc: barebox@lists.infradead.org
Cc: Jason Cooper ja...@lakedaemon.net
Cc: Andrew Lunn and...@lunn.ch
Cc: Gregory Clement gregory.clem...@free-electrons.com
Cc: Thomas Petazzoni thomas.petazz...@free-electrons.com
Cc: Ezequiel Garcia ezequiel.gar...@free-electrons.com
---
arch/arm/dts/armada-370-mirabox-bb.dts | 35 ++
1 file changed, 35 insertions(+)
diff --git a/arch/arm/dts/armada-370-mirabox-bb.dts
b/arch/arm/dts/armada-370-mirabox-bb.dts
index de37a75bb960..a1a5d48aefb2 100644
--- a/arch/arm/dts/armada-370-mirabox-bb.dts
+++ b/arch/arm/dts/armada-370-mirabox-bb.dts
@@ -20,6 +20,41 @@
barebox,default-trigger = heartbeat;
};
};
+
+ /* USB 2.0 Hub + uSD USB controllers */
+ usb0: usb@5 {
+ compatible = marvell,mvebu-usb;
+ reg = 0x5 0x400;
+ interrupts = 45;
+ clocks = coreclk 0;
+ usb-phy = usb_phy 0;
+ dr_mode = host;
+ status = okay;
+ };
+
+ usb_phy: phy@50800 {
+ compatible = marvell,mvebu-usb-phy-40nm;
+ reg = 0x50800 0x100;
+ clocks = coreclk 0;
+ #phy-cells = 1;
+ #address-cells = 1;
+ #size-cells = 0;
+ status = okay;
+
+ port@0 { reg = 0; };
+ port@1 { reg = 1; };
+ };
+
+ /* mini-PCIe slot */
+ usb1: usb@51000 {
+ compatible = marvell,mvebu-usb;
+ reg = 0x51000 0x400;
+ interrupts = 46;
+ clocks = coreclk 0;
+ usb-phy = usb_phy 1;
+ dr_mode = host;
+ status = okay;
+ };
};
};
};
--
2.0.0
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[PATCH RFC 1/4] usb: add Marvell MVEBU USB support
This adds support for Marvell specific implementation of ChipIdea dual role USB controllers found on Marvell MVEBU SoCs (Armada 370, XP, Dove, Kirkwood). Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com --- Cc: barebox@lists.infradead.org Cc: Jason Cooper ja...@lakedaemon.net Cc: Andrew Lunn and...@lunn.ch Cc: Gregory Clement gregory.clem...@free-electrons.com Cc: Thomas Petazzoni thomas.petazz...@free-electrons.com Cc: Ezequiel Garcia ezequiel.gar...@free-electrons.com --- drivers/usb/Kconfig| 1 + drivers/usb/Makefile | 1 + drivers/usb/gadget/Kconfig | 4 +- drivers/usb/mvebu/Kconfig | 35 ++ drivers/usb/mvebu/Makefile | 2 + drivers/usb/mvebu/core.c | 155 +++ drivers/usb/mvebu/phy.c| 301 + 7 files changed, 497 insertions(+), 2 deletions(-) create mode 100644 drivers/usb/mvebu/Kconfig create mode 100644 drivers/usb/mvebu/Makefile create mode 100644 drivers/usb/mvebu/core.c create mode 100644 drivers/usb/mvebu/phy.c diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 0b349bf619d3..a9275308eb80 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -4,6 +4,7 @@ menuconfig USB if USB source drivers/usb/imx/Kconfig +source drivers/usb/mvebu/Kconfig source drivers/usb/host/Kconfig diff --git a/drivers/usb/Makefile b/drivers/usb/Makefile index 3cefab7131a6..8e61f96eaa96 100644 --- a/drivers/usb/Makefile +++ b/drivers/usb/Makefile @@ -1,5 +1,6 @@ obj-$(CONFIG_USB) += core/ obj-$(CONFIG_USB_IMX_CHIPIDEA) += imx/ +obj-$(CONFIG_USB_MVEBU)+= mvebu/ obj-$(CONFIG_USB_GADGET) += gadget/ obj-$(CONFIG_USB_STORAGE) += storage/ obj-y += host/ diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index 97a7d215bc5b..a5151edb23d3 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -1,6 +1,6 @@ config USB_HAVE_GADGET_DRIVER bool - default y if ARCH_IMX || ARCH_MXS || ARCH_AT91 || ARCH_PXA + default y if ARCH_IMX || ARCH_MVEBU || ARCH_MXS || ARCH_AT91 || ARCH_PXA menuconfig USB_GADGET depends on USB_HAVE_GADGET_DRIVER @@ -17,7 +17,7 @@ choice config USB_GADGET_DRIVER_ARC bool prompt Arc OTG device core - depends on ARCH_IMX || ARCH_MXS + depends on ARCH_IMX || ARCH_MVEBU || ARCH_MXS select USB_GADGET_DUALSPEED select POLLER diff --git a/drivers/usb/mvebu/Kconfig b/drivers/usb/mvebu/Kconfig new file mode 100644 index ..ef452a9a1528 --- /dev/null +++ b/drivers/usb/mvebu/Kconfig @@ -0,0 +1,35 @@ +config USB_MVEBU_PHY_40NM + bool + +config USB_MVEBU_PHY_65NM + bool + +config USB_MVEBU_PHY + bool + depends on USB_MVEBU_HOST || USB_MVEBU_DEVICE + select USB_MVEBU_PHY_40NM if ARCH_ARMADA_370 + select USB_MVEBU_PHY_40NM if ARCH_ARMADA_XP + select USB_MVEBU_PHY_65NM if ARCH_DOVE + select USB_MVEBU_PHY_65NM if ARCH_KIRKWOOD + +config USB_MVEBU + select USB_MVEBU_PHY + bool + +config USB_MVEBU_HOST + bool Marvell MVEBU USB host support + depends on ARCH_MVEBU + select USB_MVEBU + select USB_EHCI + help + Enables USB host support for the ChipIdea USB controller found on + Marvell Orion5x, Kirkwood, Dove, Armada 370, and XP SoCs. + +config USB_MVEBU_DEVICE + bool Marvell MVEBU USB device support + depends on ARCH_MVEBU + select USB_MVEBU + select USB_GADGET_DRIVER_ARC + help + Enables USB device support for the ChipIdea USB controller found on + Marvell Orion5x, Kirkwood, Dove, Armada 370, and XP SoCs. diff --git a/drivers/usb/mvebu/Makefile b/drivers/usb/mvebu/Makefile new file mode 100644 index ..e2569bb2fd42 --- /dev/null +++ b/drivers/usb/mvebu/Makefile @@ -0,0 +1,2 @@ +obj-$(CONFIG_USB_MVEBU)+= core.o +obj-$(CONFIG_USB_MVEBU_PHY)+= phy.o diff --git a/drivers/usb/mvebu/core.c b/drivers/usb/mvebu/core.c new file mode 100644 index ..b8222d26d972 --- /dev/null +++ b/drivers/usb/mvebu/core.c @@ -0,0 +1,155 @@ +/* + * Marvell MVEBU USB PHY driver + * + * Sebastian Hesselbarth sebastian.hesselba...@gmail.com + * + * Based on BSP code (C) Marvell International Ltd. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed as is without any + * warranty of any kind, whether express or implied. + */ + +#include common.h +#include init.h +#include io.h +#include linux/clk.h +#include linux/mbus.h +#include mach/socid.h +#include regulator.h +#include usb/ehci.h +#include usb/fsl_usb2.h +#include usb/usb.h + +#define EHCI_REGS_OFFSET 0x100 + +#define BRIDGE_CTRL0x300 +#define BRIDGE_INTR_CAUSE 0x310 +#define BRIDGE_INTR_MASK 0x314 +#define BRIDGE_ERR_ACCESS 0x31c +#define WINDOW_CTRL(i) (0x320 + ((i) 4)) +#define
[PATCH RFC 0/4] MVEBU SoC full USB support
This *RFC* adds a driver stub for ChipIdea USB dual role controllers found on Marvell MVEBU SoCs. Although, I consider this driver quite finished, the corresponding DT binding is not. Also, we currently have no corresponding driver in Linux for both MVEBU CI stub and USB PHY. The reason I send it here and now, is to get some input from the (Linux) MVEBU guys on the binding and functional tests on Armada XP. While we happily lived some years with ehci-orion ignoring usb-phys and no usb device support at all on Linux, the situation for barebox is different, of course. For a boot loader, we desperately need usb-phy setup (and fixup) and proper DT bindings. I decided to just add the new binding style to the three board dts overlays we have for barebox. If we are all happy with it, I'd start implementing the required Linux driver for usb-phy and CI stub with mbus setup. As usual, binding docs are missing but I think it is straight forward from what we know of other SoCs/PHYs already. I also pushed a branch on barebox/next + a fixup for pinctrl and the USB patches to https://github.com/shesselba/barebox-dove.git mvebu/usb USB host has been tested on all three board obviously, I plan to test USB device on Dove D3Plug which has an USB device jack, but similar patches for Marvell Berlin (also CI) worked fine. Comments? Sebastian Hesselbarth (4): usb: add Marvell MVEBU USB support ARM: dts: add new USB nodes to Kirkwood Guruplug ARM: dts: add new USB nodes to Dove CuBox ARM: dts: add new USB nodes to Armada 370 Mirabox arch/arm/dts/armada-370-mirabox-bb.dts| 35 +++ arch/arm/dts/dove-cubox-bb.dts| 42 +++ arch/arm/dts/kirkwood-guruplug-server-plus-bb.dts | 20 ++ drivers/usb/Kconfig | 1 + drivers/usb/Makefile | 1 + drivers/usb/gadget/Kconfig| 4 +- drivers/usb/mvebu/Kconfig | 35 +++ drivers/usb/mvebu/Makefile| 2 + drivers/usb/mvebu/core.c | 155 +++ drivers/usb/mvebu/phy.c | 301 ++ 10 files changed, 594 insertions(+), 2 deletions(-) create mode 100644 drivers/usb/mvebu/Kconfig create mode 100644 drivers/usb/mvebu/Makefile create mode 100644 drivers/usb/mvebu/core.c create mode 100644 drivers/usb/mvebu/phy.c --- Cc: barebox@lists.infradead.org Cc: Jason Cooper ja...@lakedaemon.net Cc: Andrew Lunn and...@lunn.ch Cc: Gregory Clement gregory.clem...@free-electrons.com Cc: Thomas Petazzoni thomas.petazz...@free-electrons.com Cc: Ezequiel Garcia ezequiel.gar...@free-electrons.com -- 2.0.0 ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH RFC 0/4] MVEBU SoC full USB support
On Wed, Jun 25, 2014 at 04:08:44PM +0200, Sebastian Hesselbarth wrote: This *RFC* adds a driver stub for ChipIdea USB dual role controllers found on Marvell MVEBU SoCs. Although, I consider this driver quite finished, the corresponding DT binding is not. Also, we currently have no corresponding driver in Linux for both MVEBU CI stub and USB PHY. The reason I send it here and now, is to get some input from the (Linux) MVEBU guys on the binding and functional tests on Armada XP. My first thought is if this chipidea IP is used beyond the mvebu ecosystem. Shouldn't we name it and it's compatible strings with 'chipidea' instead of 'marvell'? Also, is there any other way to differentiate between the two versions other that manufacturing process resolution? Perhaps the free-electrons guys could get us some IP revision numbers? thx, Jason. ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH RFC 0/4] MVEBU SoC full USB support
On 06/25/2014 09:18 PM, Jason Cooper wrote: On Wed, Jun 25, 2014 at 04:08:44PM +0200, Sebastian Hesselbarth wrote: This *RFC* adds a driver stub for ChipIdea USB dual role controllers found on Marvell MVEBU SoCs. Although, I consider this driver quite finished, the corresponding DT binding is not. Also, we currently have no corresponding driver in Linux for both MVEBU CI stub and USB PHY. The reason I send it here and now, is to get some input from the (Linux) MVEBU guys on the binding and functional tests on Armada XP. My first thought is if this chipidea IP is used beyond the mvebu ecosystem. Shouldn't we name it and it's compatible strings with 'chipidea' instead of 'marvell'? While the IP core is CI, you remember the mbus upstream registers? That registers are very special to MVEBU SoCs and make the IP itself marvell. But I agree, that we could add chipidea, although spec itself names it ARC already. ARC aquired CI and was later bought by Synopsys, but at that time it must have been ARC. Also, is there any other way to differentiate between the two versions other that manufacturing process resolution? Perhaps the free-electrons guys could get us some IP revision numbers? I just followed how Marvell's BSP differentiates USB PHYs. In addition to 40nm and 65nm, there will be 90nm and 130nm for the older SoCs. If there is a way for free-electron to get more information about a better naming, that would be nice. Sebastian ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH RFC 0/4] MVEBU SoC full USB support
Dear Sebastian Hesselbarth, On Wed, 25 Jun 2014 16:08:44 +0200, Sebastian Hesselbarth wrote: This *RFC* adds a driver stub for ChipIdea USB dual role controllers found on Marvell MVEBU SoCs. Although, I consider this driver quite finished, the corresponding DT binding is not. Also, we currently have no corresponding driver in Linux for both MVEBU CI stub and USB PHY. Very nice! Definitely great to see some work being done on the USB support, including the PHY initialization. The reason I send it here and now, is to get some input from the (Linux) MVEBU guys on the binding and functional tests on Armada XP. I'll try to have a look when time permits. While we happily lived some years with ehci-orion ignoring usb-phys and no usb device support at all on Linux, the situation for barebox is different, of course. For a boot loader, we desperately need usb-phy setup (and fixup) and proper DT bindings. Generally speaking, the Linux support for Armada 370/XP relies a lot on specific initialization done by the Marvell U-Boot, especially in terms of USB PHY, PCIe link initialization or SERDES configuration. One of my goal when starting Armada 370/XP support in Barebox was to start with a pristine state, and see what is missing in Linux. I decided to just add the new binding style to the three board dts overlays we have for barebox. If we are all happy with it, I'd start implementing the required Linux driver for usb-phy and CI stub with mbus setup. As usual, binding docs are missing but I think it is straight forward from what we know of other SoCs/PHYs already. Indeed, Linux support for the USB gadget side would be useful. USB host has been tested on all three board obviously, I plan to test USB device on Dove D3Plug which has an USB device jack, but similar patches for Marvell Berlin (also CI) worked fine. I think I should be able to test USB device on some of the development boards, I'll have to check. Thanks! Thomas -- Thomas Petazzoni, CTO, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[RFC v3 3/5] net: add RealTek RTL-8139 PCI Ethernet driver
This driver is based on Linux 2.6.39 8139too driver.
Signed-off-by: Antony Pavlov antonynpav...@gmail.com
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com
---
drivers/net/Kconfig | 8 +
drivers/net/Makefile| 1 +
drivers/net/rtl8139.c | 621
include/linux/pci_ids.h | 5 +
4 files changed, 635 insertions(+)
create mode 100644 drivers/net/rtl8139.c
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 7a0d5e1..975c927 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -130,6 +130,14 @@ config DRIVER_NET_ORION
select PHYLIB
select MDIO_MVEBU
+config DRIVER_NET_RTL8139
+ bool RealTek RTL-8139 PCI Ethernet driver
+ depends on PCI
+ select PHYLIB
+ help
+ This is a driver for the Fast Ethernet PCI network cards based on
+ the RTL 8139 chips.
+
config DRIVER_NET_SMC911X
bool smc911x ethernet driver
select PHYLIB
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 65f0d8b..d907061 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_DRIVER_NET_MICREL) += ksz8864rmn.o
obj-$(CONFIG_DRIVER_NET_MPC5200) += fec_mpc5200.o
obj-$(CONFIG_DRIVER_NET_NETX) += netx_eth.o
obj-$(CONFIG_DRIVER_NET_ORION) += orion-gbe.o
+obj-$(CONFIG_DRIVER_NET_RTL8139) += rtl8139.o
obj-$(CONFIG_DRIVER_NET_SMC911X) += smc911x.o
obj-$(CONFIG_DRIVER_NET_SMC9) += smc9.o
obj-$(CONFIG_DRIVER_NET_TAP) += tap.o
diff --git a/drivers/net/rtl8139.c b/drivers/net/rtl8139.c
new file mode 100644
index 000..e5d1291
--- /dev/null
+++ b/drivers/net/rtl8139.c
@@ -0,0 +1,621 @@
+#include common.h
+#include net.h
+#include malloc.h
+#include init.h
+#include xfuncs.h
+#include errno.h
+#include io.h
+#include linux/phy.h
+#include linux/pci.h
+
+#define RTL8139_DEBUG
+#undef RTL8139_DEBUG
+
+/*
+ * Receive ring size
+ * Warning: 64K ring has hardware issues and may lock up.
+ */
+#define RX_BUF_IDX 0 /* 8K ring */
+#define RX_BUF_LEN (8192 RX_BUF_IDX)
+#define RX_BUF_PAD 16
+#define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
+
+#if RX_BUF_LEN == 65536
+#define RX_BUF_TOT_LEN RX_BUF_LEN
+#else
+#define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
+#endif
+
+/* Number of Tx descriptor registers. */
+#define NUM_TX_DESC4
+
+/* max supported ethernet frame size -- must be at least (dev-mtu+14+4).*/
+#define MAX_ETH_FRAME_SIZE 1536
+
+/* Size of the Tx bounce buffers -- must be at least (dev-mtu+14+4). */
+#define TX_BUF_SIZEMAX_ETH_FRAME_SIZE
+#define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
+
+/* PCI Tuning Parameters
+ Threshold is bytes transferred to chip before transmission starts. */
+#define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
+
+/* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024,
7==end of packet. */
+#define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
+#define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */
+#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
+#define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */
+
+struct rtl8139_priv {
+ struct eth_device edev;
+ void __iomem*base;
+ struct pci_dev *pci_dev;
+ unsigned char *rx_ring;
+ unsigned intcur_rx; /* RX buf index of next pkt */
+ dma_addr_t rx_ring_dma;
+
+ u32 rx_config;
+ unsigned inttx_flag;
+ unsigned long cur_tx;
+ unsigned long dirty_tx;
+ unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
+ unsigned char *tx_bufs; /* Tx bounce buffer region. */
+ dma_addr_t tx_bufs_dma;
+
+ struct mii_bus miibus;
+};
+
+#define ETH_ZLEN60 /* Min. octets in frame sans FCS */
+
+/* Registers */
+#define MAC0 0x00
+#define MAR0 0x08
+#define TxStatus0 0x10
+
+enum TxStatusBits {
+ TxHostOwns = 0x2000,
+ TxUnderrun = 0x4000,
+ TxStatOK= 0x8000,
+ TxOutOfWindow = 0x2000,
+ TxAborted = 0x4000,
+ TxCarrierLost = 0x8000,
+};
+
+#define TxAddr00x20
+#define RxBuf 0x30
+#define ChipCmd0x37
+#define CmdReset 0x10
+#define CmdRxEnb 0x08
+#define CmdTxEnb 0x04
+#define RxBufEmpty0x01
+#define RxBufPtr 0x38
+#define RxBufAddr 0x3A
+#define IntrMask 0x3C
+#define IntrStatus 0x3E
+#define PCIErr0x8000
+#define PCSTimeout0x4000
+#define RxFIFOOver0x0040
+#define RxUnderrun0x0020
+#define RxOverflow0x0010
+#define TxErr
[RFC v3 5/5] MIPS: qemu-malta_defconfig: enable PCI network stuff
qemu usage: # ifconfig br0:1 172.20.0.1 # qemu-system-mips -nodefaults -nographic -M malta -m 256 \ -serial stdio -monitor null \ -bios ./barebox-flash-image \ -net nic,vlan=0,model=rtl8139 \ -net tap,vlan=0,script=net_br0.sh ... barebox:/ eth0.ipaddr=172.20.0.2 barebox:/ eth0.serverip=172.20.0.1 barebox:/ ping 172.20.0.1 phy0: Link is up - 100/Full host 172.20.0.1 is alive barebox:/ Sample net_br0.sh (for connecting to br0 interface, so you can connect barebox to your real network): #!/bin/sh brctl addif br0 $1 ifconfig $1 up Signed-off-by: Antony Pavlov antonynpav...@gmail.com --- arch/mips/configs/qemu-malta_defconfig | 4 1 file changed, 4 insertions(+) diff --git a/arch/mips/configs/qemu-malta_defconfig b/arch/mips/configs/qemu-malta_defconfig index 78f175d..4fee70e 100644 --- a/arch/mips/configs/qemu-malta_defconfig +++ b/arch/mips/configs/qemu-malta_defconfig @@ -1,5 +1,7 @@ CONFIG_BUILTIN_DTB=y CONFIG_BUILTIN_DTB_NAME=qemu-malta +CONFIG_PCI=y +CONFIG_PCI_DEBUG=y CONFIG_PBL_IMAGE=y CONFIG_STACK_SIZE=0x7000 CONFIG_BROKEN=y @@ -32,6 +34,7 @@ CONFIG_CMD_UNCOMPRESS=y CONFIG_CMD_GETOPT=y CONFIG_CMD_SLEEP=y CONFIG_CMD_DHCP=y +CONFIG_CMD_MIITOOL=y CONFIG_CMD_PING=y CONFIG_CMD_TFTP=y CONFIG_CMD_ECHO_E=y @@ -56,6 +59,7 @@ CONFIG_NET_NETCONSOLE=y CONFIG_NET_RESOLV=y CONFIG_OFDEVICE=y CONFIG_OF_BAREBOX_DRIVERS=y +CONFIG_DRIVER_NET_RTL8139=y # CONFIG_SPI is not set CONFIG_I2C=y CONFIG_I2C_GPIO=y -- 1.9.2 ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[RFC v3 1/5] PCI: initial commit
used shorten version of linux-2.6.39 pci_ids.h
Signed-off-by: Antony Pavlov antonynpav...@gmail.com
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com
---
drivers/Makefile| 1 +
drivers/pci/Kconfig | 12 ++
drivers/pci/Makefile| 8 ++
drivers/pci/bus.c | 110
drivers/pci/pci.c | 282
include/linux/mod_devicetable.h | 20 +++
include/linux/pci.h | 241 ++
include/linux/pci_ids.h | 136 +++
include/linux/pci_regs.h| 118 +
9 files changed, 928 insertions(+)
create mode 100644 drivers/pci/Kconfig
create mode 100644 drivers/pci/Makefile
create mode 100644 drivers/pci/bus.c
create mode 100644 drivers/pci/pci.c
create mode 100644 include/linux/mod_devicetable.h
create mode 100644 include/linux/pci.h
create mode 100644 include/linux/pci_ids.h
create mode 100644 include/linux/pci_regs.h
diff --git a/drivers/Makefile b/drivers/Makefile
index ef3604f..1990e86 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -26,3 +26,4 @@ obj-y += pinctrl/
obj-y += bus/
obj-$(CONFIG_REGULATOR) += regulator/
obj-$(CONFIG_RESET_CONTROLLER) += reset/
+obj-$(CONFIG_PCI) += pci/
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
new file mode 100644
index 000..88b8dfb
--- /dev/null
+++ b/drivers/pci/Kconfig
@@ -0,0 +1,12 @@
+#
+# PCI configuration
+#
+config PCI_DEBUG
+ bool PCI Debugging
+ depends on PCI
+ help
+ Say Y here if you want the PCI core to produce a bunch of debug
+ messages to the system log. Select this if you are having a
+ problem with PCI support and want to see more of what is going on.
+
+ When in doubt, say N.
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
new file mode 100644
index 000..c7d43c3
--- /dev/null
+++ b/drivers/pci/Makefile
@@ -0,0 +1,8 @@
+#
+# Makefile for the PCI bus specific drivers.
+#
+obj-y += pci.o bus.o
+
+ccflags-$(CONFIG_PCI_DEBUG) := -DDEBUG
+
+CPPFLAGS += $(ccflags-y)
diff --git a/drivers/pci/bus.c b/drivers/pci/bus.c
new file mode 100644
index 000..8215ee5
--- /dev/null
+++ b/drivers/pci/bus.c
@@ -0,0 +1,110 @@
+#include common.h
+#include init.h
+#include driver.h
+#include linux/pci.h
+
+/**
+ * pci_match_one_device - Tell if a PCI device structure has a matching
+ *PCI device id structure
+ * @id: single PCI device id structure to match
+ * @dev: the PCI device structure to match against
+ *
+ * Returns the matching pci_device_id structure or %NULL if there is no match.
+ */
+static inline const struct pci_device_id *
+pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
+{
+ if ((id-vendor == PCI_ANY_ID || id-vendor == dev-vendor)
+ (id-device == PCI_ANY_ID || id-device == dev-device)
+ (id-subvendor == PCI_ANY_ID || id-subvendor ==
dev-subsystem_vendor)
+ (id-subdevice == PCI_ANY_ID || id-subdevice ==
dev-subsystem_device)
+ !((id-class ^ dev-class) id-class_mask))
+ return id;
+ return NULL;
+}
+
+static int pci_match(struct device_d *dev, struct driver_d *drv)
+{
+ struct pci_dev *pdev = to_pci_dev(dev);
+ struct pci_driver *pdrv = to_pci_driver(drv);
+ struct pci_device_id *id;
+
+ for (id = (struct pci_device_id *)pdrv-id_table; id-vendor; id++)
+ if (pci_match_one_device(id, pdev)) {
+ dev-priv = id;
+ return 0;
+ }
+
+ return -1;
+}
+
+static int pci_probe(struct device_d *dev)
+{
+ struct pci_dev *pdev = to_pci_dev(dev);
+ struct pci_driver *pdrv = to_pci_driver(dev-driver);
+
+ return pdrv-probe(pdev, dev-priv);
+}
+
+static void pci_remove(struct device_d *dev)
+{
+ struct pci_dev *pdev = to_pci_dev(dev);
+ struct pci_driver *pdrv = to_pci_driver(dev-driver);
+
+ pdrv-remove(pdev);
+}
+
+struct bus_type pci_bus = {
+ .name = pci,
+ .match = pci_match,
+ .probe = pci_probe,
+ .remove = pci_remove,
+};
+
+static int pci_bus_init(void)
+{
+ return bus_register(pci_bus);
+}
+pure_initcall(pci_bus_init);
+
+int pci_register_driver(struct pci_driver *pdrv)
+{
+ struct driver_d *drv = pdrv-driver;
+
+ if (!pdrv-id_table)
+ return -EIO;
+
+ drv-name = pdrv-name;
+ drv-bus = pci_bus;
+
+ return register_driver(drv);
+}
+
+int pci_register_device(struct pci_dev *pdev)
+{
+ char str[6];
+ struct device_d *dev = pdev-dev;
+ int ret;
+
+ strcpy(dev-name, pci);
+ dev-bus = pci_bus;
+ dev-id = DEVICE_ID_DYNAMIC;
+
+ ret = register_device(dev);
+
+ if (ret)
+ return ret;
+
+ sprintf(str, %02x, pdev-devfn);
+ dev_add_param_fixed(dev, devfn, str);
+
[RFC v3 4/5] MIPS: add PCI support for GT64120-based Malta board
Signed-off-by: Antony Pavlov antonynpav...@gmail.com
---
arch/mips/Kconfig| 22 ++
arch/mips/include/asm/gt64120.h | 53 +
arch/mips/mach-malta/Makefile| 1 +
arch/mips/mach-malta/include/mach/mach-gt64120.h | 2 +
arch/mips/mach-malta/pci.c | 246 +++
5 files changed, 324 insertions(+)
create mode 100644 arch/mips/mach-malta/pci.c
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index f6b9765..603ce6e 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -45,6 +45,7 @@ config MACH_MIPS_MALTA
select SYS_SUPPORTS_BIG_ENDIAN
select HAS_DEBUG_LL
select GPIOLIB
+ select HW_HAS_PCI
config MACH_MIPS_AR231X
bool Atheros ar231x-based boards
@@ -330,6 +331,27 @@ config NMON_HELP
endmenu
+menu Bus options (PCI)
+
+config HW_HAS_PCI
+ bool
+
+config PCI
+ bool Support for PCI controller
+ depends on HW_HAS_PCI
+ select PCI_DOMAINS
+ help
+ Find out whether you have a PCI motherboard. PCI is the name of a
+ bus system, i.e. the way the CPU talks to the other stuff inside
+ your box. If you have PCI, say Y, otherwise N.
+
+config PCI_DOMAINS
+ bool
+
+source drivers/pci/Kconfig
+
+endmenu
+
source common/Kconfig
source commands/Kconfig
source net/Kconfig
diff --git a/arch/mips/include/asm/gt64120.h b/arch/mips/include/asm/gt64120.h
index 6b2ad0f..7e783c8 100644
--- a/arch/mips/include/asm/gt64120.h
+++ b/arch/mips/include/asm/gt64120.h
@@ -18,6 +18,8 @@
#ifndef _ASM_GT64120_H
#define _ASM_GT64120_H
+#define MSK(n) ((1 (n)) - 1)
+
#define GT_DEF_BASE0x1400
/*
@@ -34,4 +36,55 @@
#define GT_PCI0M1LD_OFS0x080
#define GT_PCI0M1HD_OFS0x088
+#define GT_PCI0IOREMAP_OFS 0x0f0
+#define GT_PCI0M0REMAP_OFS 0x0f8
+#define GT_PCI0M1REMAP_OFS 0x100
+
+/* Interrupts. */
+#define GT_INTRCAUSE_OFS 0xc18
+
+/* PCI Internal. */
+#define GT_PCI0_CMD_OFS0xc00
+#define GT_PCI0_CFGADDR_OFS0xcf8
+#define GT_PCI0_CFGDATA_OFS0xcfc
+
+#define GT_PCI_DCRM_SHF21
+#define GT_PCI_LD_SHF 0
+#define GT_PCI_LD_MSK (MSK(15) GT_PCI_LD_SHF)
+#define GT_PCI_HD_SHF 0
+#define GT_PCI_HD_MSK (MSK(7) GT_PCI_HD_SHF)
+#define GT_PCI_REMAP_SHF 0
+#define GT_PCI_REMAP_MSK (MSK(11) GT_PCI_REMAP_SHF)
+
+#define GT_INTRCAUSE_MASABORT0_SHF 18
+#define GT_INTRCAUSE_MASABORT0_MSK (MSK(1) GT_INTRCAUSE_MASABORT0_SHF)
+#define GT_INTRCAUSE_MASABORT0_BIT GT_INTRCAUSE_MASABORT0_MSK
+
+#define GT_INTRCAUSE_TARABORT0_SHF 19
+#define GT_INTRCAUSE_TARABORT0_MSK (MSK(1) GT_INTRCAUSE_TARABORT0_SHF)
+#define GT_INTRCAUSE_TARABORT0_BIT GT_INTRCAUSE_TARABORT0_MSK
+
+#define GT_PCI0_CFGADDR_REGNUM_SHF 2
+#define GT_PCI0_CFGADDR_REGNUM_MSK (MSK(6) GT_PCI0_CFGADDR_REGNUM_SHF)
+#define GT_PCI0_CFGADDR_FUNCTNUM_SHF 8
+#define GT_PCI0_CFGADDR_FUNCTNUM_MSK (MSK(3) GT_PCI0_CFGADDR_FUNCTNUM_SHF)
+#define GT_PCI0_CFGADDR_DEVNUM_SHF 11
+#define GT_PCI0_CFGADDR_DEVNUM_MSK (MSK(5) GT_PCI0_CFGADDR_DEVNUM_SHF)
+#define GT_PCI0_CFGADDR_BUSNUM_SHF 16
+#define GT_PCI0_CFGADDR_BUSNUM_MSK (MSK(8) GT_PCI0_CFGADDR_BUSNUM_SHF)
+#define GT_PCI0_CFGADDR_CONFIGEN_SHF 31
+#define GT_PCI0_CFGADDR_CONFIGEN_MSK (MSK(1) GT_PCI0_CFGADDR_CONFIGEN_SHF)
+#define GT_PCI0_CFGADDR_CONFIGEN_BIT GT_PCI0_CFGADDR_CONFIGEN_MSK
+
+/*
+ * Because of an error/peculiarity in the Galileo chip, we need to swap the
+ * bytes when running bigendian. We also provide non-swapping versions.
+ */
+#define __GT_READ(ofs) \
+ (*(volatile u32 *)(GT64120_BASE+(ofs)))
+#define __GT_WRITE(ofs, data) \
+ do { *(volatile u32 *)(GT64120_BASE+(ofs)) = (data); } while (0)
+#define GT_READ(ofs) le32_to_cpu(__GT_READ(ofs))
+#define GT_WRITE(ofs, data)__GT_WRITE(ofs, cpu_to_le32(data))
+
#endif /* _ASM_GT64120_H */
diff --git a/arch/mips/mach-malta/Makefile b/arch/mips/mach-malta/Makefile
index f3cc668..0c5a701 100644
--- a/arch/mips/mach-malta/Makefile
+++ b/arch/mips/mach-malta/Makefile
@@ -1 +1,2 @@
obj-y += reset.o
+obj-$(CONFIG_PCI) += pci.o
diff --git a/arch/mips/mach-malta/include/mach/mach-gt64120.h
b/arch/mips/mach-malta/include/mach/mach-gt64120.h
index ed1e23e..8f20fcf 100644
--- a/arch/mips/mach-malta/include/mach/mach-gt64120.h
+++ b/arch/mips/mach-malta/include/mach/mach-gt64120.h
@@ -10,4 +10,6 @@
#define MIPS_GT_BASE 0x1be0
+#define GT64120_BASE0xbbe0
+
#endif /* _ASM_MACH_MIPS_MACH_GT64120_DEP_H */
diff --git a/arch/mips/mach-malta/pci.c b/arch/mips/mach-malta/pci.c
new file mode 100644
index 000..15fd9ed
--- /dev/null
+++ b/arch/mips/mach-malta/pci.c
@@ -0,0 +1,246 @@
+#include common.h
+#include types.h
[RFC v3 0/5] barebox PCI support
This patchseries introduce simple PCI bus support for barebox. Previous (RFC v2) version can be found here: http://lists.infradead.org/pipermail/barebox/2012-March/006327.html TODOs for RFC v3: * no PCI bridges support; * introduce dma_alloc_coherent(); * introduce pci_resource_start(); * introduce pci_iomap(); * introduce pci_set_master() pci_clear_master(); * clean '#if 0'. This patchseries can be found on github: https://github.com/frantony/barebox/tree/pci.20140626 Antony Pavlov (5): PCI: initial commit commands: add 'lspci' command net: add RealTek RTL-8139 PCI Ethernet driver MIPS: add PCI support for GT64120-based Malta board MIPS: qemu-malta_defconfig: enable PCI network stuff arch/mips/Kconfig| 22 + arch/mips/configs/qemu-malta_defconfig | 4 + arch/mips/include/asm/gt64120.h | 53 ++ arch/mips/mach-malta/Makefile| 1 + arch/mips/mach-malta/include/mach/mach-gt64120.h | 2 + arch/mips/mach-malta/pci.c | 246 + commands/Kconfig | 8 + commands/Makefile| 1 + commands/lspci.c | 49 ++ drivers/Makefile | 1 + drivers/net/Kconfig | 8 + drivers/net/Makefile | 1 + drivers/net/rtl8139.c| 621 +++ drivers/pci/Kconfig | 12 + drivers/pci/Makefile | 8 + drivers/pci/bus.c| 110 drivers/pci/pci.c| 282 ++ include/linux/mod_devicetable.h | 20 + include/linux/pci.h | 241 + include/linux/pci_ids.h | 141 + include/linux/pci_regs.h | 118 + 21 files changed, 1949 insertions(+) create mode 100644 arch/mips/mach-malta/pci.c create mode 100644 commands/lspci.c create mode 100644 drivers/net/rtl8139.c create mode 100644 drivers/pci/Kconfig create mode 100644 drivers/pci/Makefile create mode 100644 drivers/pci/bus.c create mode 100644 drivers/pci/pci.c create mode 100644 include/linux/mod_devicetable.h create mode 100644 include/linux/pci.h create mode 100644 include/linux/pci_ids.h create mode 100644 include/linux/pci_regs.h -- 1.9.2 ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[RFC v3 2/5] commands: add 'lspci' command
Signed-off-by: Antony Pavlov antonynpav...@gmail.com
---
commands/Kconfig | 8
commands/Makefile | 1 +
commands/lspci.c | 49 +
3 files changed, 58 insertions(+)
create mode 100644 commands/lspci.c
diff --git a/commands/Kconfig b/commands/Kconfig
index eed6fbd..c98dbc5 100644
--- a/commands/Kconfig
+++ b/commands/Kconfig
@@ -207,6 +207,14 @@ config CMD_REGULATOR
the regulator command lists the currently registered regulators and
their current state.
+config CMD_LSPCI
+ bool
+ depends on PCI
+ prompt lspci command
+ default y
+ help
+ The lspci command allows to list all PCI devices.
+
config CMD_VERSION
tristate
default y
diff --git a/commands/Makefile b/commands/Makefile
index a84d333..d42aca5 100644
--- a/commands/Makefile
+++ b/commands/Makefile
@@ -99,3 +99,4 @@ obj-$(CONFIG_CMD_READF) += readf.o
obj-$(CONFIG_CMD_MENUTREE) += menutree.o
obj-$(CONFIG_CMD_2048) += 2048.o
obj-$(CONFIG_CMD_REGULATOR)+= regulator.o
+obj-$(CONFIG_CMD_LSPCI)+= lspci.o
diff --git a/commands/lspci.c b/commands/lspci.c
new file mode 100644
index 000..5e1f6dd
--- /dev/null
+++ b/commands/lspci.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2011-2014 Antony Pavlov antonynpav...@gmail.com
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include common.h
+#include command.h
+#include complete.h
+#include linux/pci.h
+
+static int do_lspci(int argc, char *argv[])
+{
+ struct pci_dev *dev;
+
+ if (!pci_root) {
+ printf(no pci!\n);
+ return 1;
+ }
+
+ list_for_each_entry(dev, pci_root-devices, bus_list) {
+ printf(%02x: %04x: %04x:%04x (rev %02x)\n,
+ dev-devfn,
+ (dev-class 8) 0x,
+ dev-vendor,
+ dev-device,
+ dev-revision);
+ }
+
+ return 0;
+}
+
+BAREBOX_CMD_START(lspci)
+ .cmd= do_lspci,
+ BAREBOX_CMD_DESC(Show PCI info)
+ BAREBOX_CMD_GROUP(CMD_GRP_INFO)
+ BAREBOX_CMD_COMPLETE(empty_complete)
+BAREBOX_CMD_END
--
1.9.2
___
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Re: [RFC 2/2] dns325: initial support for D-Link DNS-325
Hi,
On Sun, Jun 22, 2014 at 11:50:56PM +0200, Sebastian Hesselbarth wrote:
On 06/22/2014 10:34 PM, Alexander Aring wrote:
This patch add a basic support for the D-Link DNS-325.
Currently only booting via uart with kwboot is supported. The barebox
kwboot utility doesn't work at the moment. Use kwboot utility from u-boot
instead.
Why does kwboot does not work? There is an issue with early Kirkwood's
BootROM and UART boot mode. Just try over and over again. I also recall
modifying the timeouts may help.
I tried to change the timeouts and it works now. I take these timings from
u-boot. Is there any reason why these timings differs?
Datasheet says nothing about any delay while loop for sending bootmsg.
Here is my diff with the very small change:
diff --git a/scripts/kwboot.c b/scripts/kwboot.c
index e068660..bcb5972 100644
--- a/scripts/kwboot.c
+++ b/scripts/kwboot.c
@@ -34,8 +34,8 @@ static unsigned char kwboot_msg_debug[] = {
0xDD, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77
};
-#define KWBOOT_MSG_REQ_DELAY 1000 /* ms */
-#define KWBOOT_MSG_RSP_TIMEO 1000 /* ms */
+#define KWBOOT_MSG_REQ_DELAY 10 /* ms */
+#define KWBOOT_MSG_RSP_TIMEO 50 /* ms */
/*
* Xmodem Transfers
btw.:
Now I see that the internal ROM bootloader could also boot from SATA
device - this sounds interesting. I will try that next weekend.
Thanks for your great help Sebastian!
- Alex
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Re: How to disable console late?
On Wed, Jun 25, 2014 at 06:22:04PM +0200, Holger Schurig wrote: On my i.MX6 I have CONFIG_CONSOLE_FULL and CONSOLE_ACTIVATE_NONE defined. But still my serial is automatically activated as a console. barebox:/ devinfo cs0 Bus: platform Parameters: baudrate: 115200 active: ioe I'd rather active the serial port as a console only if a key is pressed during power on. Based on the help text of CONFIG_ACTIVATE_NONE, I actually thought that this would happen. Any hints? I could remove chosen/stdout-path from my DTS and put it in on-the-fly? This sounds a bit ugly ... Indeed you have to remove the stdout-path property from DTS. You don't have to add it back, 'cs0.active=ioe' should do it. Note we currently don't have persistent names for the console devices which means that cs0 is whatever is probed first. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
