Re: [PATCH v3 0/3] Add device tree support of Atmel NAND driver
On Mon, Sep 01, 2014 at 02:27:32PM +0200, Raphaël Poggi wrote: Change since v2: * Combine in one patch the creation and initialisation of has_pmecc structure member * Combine patch [PATCH 3/5] mtd: atmel_nand: retrieve ecc_mode from pdata and [PATCH 4/5] board: atmel: initialise ecc_mode * Let NAND_ATMEL_PMECC config, but change the test in atmel_nand Change since v1: * Reorder patchs * Fix some clean style issue. This patchset adds the device tree support for the Atmel NAND driver. The first patch add the has_pmecc structure member to be able to retrieve pmecc from device tree and adds the has_pmecc on boards which need it. The second patch retrieves the ecc_mode from the plateform data, and remove this code: nand_chip-ecc.mode = NAND_ECC_SOFT; which arbitrary sets the ecc.mode to NAND_ECC_SOFT and changes the value depending of the config and plateform data. With this, we can use the same logics for device tree and non device tree probing of the driver. It also adds the ecc_mode on boards which are missing it (boards which use NAND_ECC_SOFT). The third patch adds the device tree in the atmel_nand driver. Raphaël Poggi (4): (1) mtd: nand: add has_pmecc member (2) mtd: atmel_nand: retrieve ecc_mode from pdata (3) mtd: atmel_nand: add support for device tree Applied, thanks Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH] ARM: dts: Use local version of rk3188-clocks.dtsi
As of 3.17-rc1 the upstream dts sources for the rockchip rk3188 use
incompatible clock bindings. We currently do not have the resources
to update the clock driver to this new binding, so we use local copies
of the Linux 3.16 dtsi files. Due to the incompatible change the
internal device tree won't work with kernels newer than 3.17-rc1.
Signed-off-by: Sascha Hauer s.ha...@pengutronix.de
---
arch/arm/dts/rk3188-clocks.dtsi | 289
arch/arm/dts/rk3188.dtsi| 256 ++-
arch/arm/dts/rk3xxx.dtsi| 139 +++
3 files changed, 681 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/dts/rk3188-clocks.dtsi
create mode 100644 arch/arm/dts/rk3xxx.dtsi
diff --git a/arch/arm/dts/rk3188-clocks.dtsi b/arch/arm/dts/rk3188-clocks.dtsi
new file mode 100644
index 000..b1b92dc
--- /dev/null
+++ b/arch/arm/dts/rk3188-clocks.dtsi
@@ -0,0 +1,289 @@
+/*
+ * Copyright (c) 2013 MundoReader S.L.
+ * Author: Heiko Stuebner he...@sntech.de
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/ {
+ clocks {
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges;
+
+ /*
+* This is a dummy clock, to be used as placeholder on
+* other mux clocks when a specific parent clock is not
+* yet implemented. It should be dropped when the driver
+* is complete.
+*/
+ dummy: dummy {
+ compatible = fixed-clock;
+ clock-frequency = 0;
+ #clock-cells = 0;
+ };
+
+ xin24m: xin24m {
+ compatible = fixed-clock;
+ clock-frequency = 2400;
+ #clock-cells = 0;
+ };
+
+ dummy48m: dummy48m {
+ compatible = fixed-clock;
+ clock-frequency = 4800;
+ #clock-cells = 0;
+ };
+
+ dummy150m: dummy150m {
+ compatible = fixed-clock;
+ clock-frequency = 15000;
+ #clock-cells = 0;
+ };
+
+ clk_gates0: gate-clk@20d0 {
+ compatible = rockchip,rk2928-gate-clk;
+ reg = 0x20d0 0x4;
+ clocks = dummy150m, dummy,
+dummy, dummy,
+dummy, dummy,
+dummy, dummy,
+dummy, dummy,
+dummy, dummy,
+dummy, dummy,
+dummy, dummy;
+
+ clock-output-names =
+ gate_core_periph, gate_cpu_gpll,
+ gate_ddrphy, gate_aclk_cpu,
+ gate_hclk_cpu, gate_pclk_cpu,
+ gate_atclk_cpu, gate_aclk_core,
+ reserved, gate_i2s0,
+ gate_i2s0_frac, reserved,
+ reserved, gate_spdif,
+ gate_spdif_frac, gate_testclk;
+
+ #clock-cells = 1;
+ };
+
+ clk_gates1: gate-clk@20d4 {
+ compatible = rockchip,rk2928-gate-clk;
+ reg = 0x20d4 0x4;
+ clocks = xin24m, xin24m,
+xin24m, dummy,
+dummy, xin24m,
+xin24m, dummy,
+xin24m, dummy,
+xin24m, dummy,
+xin24m, dummy,
+xin24m, dummy;
+
+ clock-output-names =
+ gate_timer0, gate_timer1,
+ gate_timer3, gate_jtag,
+ gate_aclk_lcdc1_src, gate_otgphy0,
+ gate_otgphy1, gate_ddr_gpll,
+ gate_uart0, gate_frac_uart0,
+ gate_uart1, gate_frac_uart1,
+ gate_uart2, gate_frac_uart2,
+ gate_uart3, gate_frac_uart3;
+
+ #clock-cells
Re: [PATCH v2 1/2] pinctrl: at91: add pinctrl driver
Hi,
I can add all the functions from mach-at91/gpio.h in
mach-at91/include/gpio.h and remove mach-at91/gpio.h. Is this a valid
solution ?
2014-09-01 12:08 GMT+02:00 Sascha Hauer s.ha...@pengutronix.de:
On Tue, Aug 05, 2014 at 01:09:16PM -0700, Raphaël Poggi wrote:
diff --git a/drivers/pinctrl/pinctrl-at91.h b/drivers/pinctrl/pinctrl-at91.h
new file mode 100644
index 000..e719fb8
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-at91.h
@@ -0,0 +1,148 @@
+/*
+ * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD
plagn...@jcrosoft.com
+ *
+ * Under GPLv2 only
+ */
+
+#ifndef __AT91_GPIO_H__
+#define __AT91_GPIO_H__
+
+#ifndef __gpio_init
+#define __gpio_init
+#endif
+
+#define MAX_NB_GPIO_PER_BANK 32
+
+static inline unsigned pin_to_bank(unsigned pin)
+{
+ return pin / MAX_NB_GPIO_PER_BANK;
+}
+
+static inline unsigned pin_to_bank_offset(unsigned pin)
+{
+ return pin % MAX_NB_GPIO_PER_BANK;
+}
+
+static inline unsigned pin_to_mask(unsigned pin)
+{
+ return 1 pin_to_bank_offset(pin);
+}
+
+static inline void at91_mux_disable_interrupt(void __iomem *pio, unsigned
mask)
+{
+ __raw_writel(mask, pio + PIO_IDR);
+}
+
+static inline void at91_mux_set_pullup(void __iomem *pio, unsigned mask,
bool on)
+{
+ __raw_writel(mask, pio + (on ? PIO_PUER : PIO_PUDR));
+}
+
+static inline void at91_mux_set_multidrive(void __iomem *pio, unsigned
mask, bool on)
+{
+ __raw_writel(mask, pio + (on ? PIO_MDER : PIO_MDDR));
+}
+
+static inline void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
+{
+ __raw_writel(mask, pio + PIO_ASR);
+}
+
+static inline void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
+{
+ __raw_writel(mask, pio + PIO_BSR);
+}
+
+static inline void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned
mask)
+{
+
+ __raw_writel(__raw_readl(pio + PIO_ABCDSR1) ~mask,
+ pio + PIO_ABCDSR1);
+ __raw_writel(__raw_readl(pio + PIO_ABCDSR2) ~mask,
+ pio + PIO_ABCDSR2);
+}
+
+static inline void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned
mask)
+{
+ __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask,
+ pio + PIO_ABCDSR1);
+ __raw_writel(__raw_readl(pio + PIO_ABCDSR2) ~mask,
+ pio + PIO_ABCDSR2);
+}
+
+static inline void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned
mask)
+{
+ __raw_writel(__raw_readl(pio + PIO_ABCDSR1) ~mask, pio +
PIO_ABCDSR1);
+ __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
+}
+
+static inline void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned
mask)
+{
+ __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
+ __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
+}
+
+static inline void at91_mux_set_deglitch(void __iomem *pio, unsigned mask,
bool is_on)
+{
+ __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
+}
+
+static inline void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned
mask, bool is_on)
+{
+ if (is_on)
+ __raw_writel(mask, pio + PIO_IFSCDR);
+ at91_mux_set_deglitch(pio, mask, is_on);
+}
+
+static inline void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned
mask,
+ bool is_on, u32 div)
+{
+ if (is_on) {
+ __raw_writel(mask, pio + PIO_IFSCER);
+ __raw_writel(div PIO_SCDR_DIV, pio + PIO_SCDR);
+ __raw_writel(mask, pio + PIO_IFER);
+ } else {
+ __raw_writel(mask, pio + PIO_IFDR);
+ }
+}
+
+static inline void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned
mask, bool is_on)
+{
+ __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
+}
+
+static inline void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio,
unsigned mask)
+{
+ __raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
+}
+
+static inline void at91_mux_gpio_disable(void __iomem *pio, unsigned mask)
+{
+ __raw_writel(mask, pio + PIO_PDR);
+}
+
+static inline void at91_mux_gpio_enable(void __iomem *pio, unsigned mask)
+{
+ __raw_writel(mask, pio + PIO_PER);
+}
+
+static inline void at91_mux_gpio_input(void __iomem *pio, unsigned mask,
bool input)
+{
+ __raw_writel(mask, pio + (input ? PIO_ODR : PIO_OER));
+}
+
+static inline void at91_mux_gpio_set(void __iomem *pio, unsigned mask,
+int value)
+{
+ __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
+}
+
+static inline int at91_mux_gpio_get(void __iomem *pio, unsigned mask)
+{
+ u32 pdsr;
+
+ pdsr = __raw_readl(pio + PIO_PDSR);
+ return (pdsr mask) != 0;
+}
We already have all these functions in arch/arm/mach-at91/gpio.h. Do we
really need them
[PATCH] ARM: dts: move imx6q-embedsky-e9.dtsi to arch/arm/dts/boot
dts/ is for upstream dts files only. Move barebox specific file
to arch/arm/dts/ so that it doesn't get removed by the next
dts update.
Signed-off-by: Sascha Hauer s.ha...@pengutronix.de
---
arch/arm/dts/imx6q-embedsky-e9.dts | 2 +-
arch/arm/dts/imx6q-embedsky-e9.dtsi | 395
dts/src/arm/imx6q-embedsky-e9.dtsi | 395
3 files changed, 396 insertions(+), 396 deletions(-)
create mode 100644 arch/arm/dts/imx6q-embedsky-e9.dtsi
delete mode 100644 dts/src/arm/imx6q-embedsky-e9.dtsi
diff --git a/arch/arm/dts/imx6q-embedsky-e9.dts
b/arch/arm/dts/imx6q-embedsky-e9.dts
index 14f6d5f..d8a606a 100644
--- a/arch/arm/dts/imx6q-embedsky-e9.dts
+++ b/arch/arm/dts/imx6q-embedsky-e9.dts
@@ -13,7 +13,7 @@
/dts-v1/;
#include imx6q.dtsi
-#include arm/imx6q-embedsky-e9.dtsi
+#include imx6q-embedsky-e9.dtsi
/ {
chosen {
diff --git a/arch/arm/dts/imx6q-embedsky-e9.dtsi
b/arch/arm/dts/imx6q-embedsky-e9.dtsi
new file mode 100644
index 000..a29de9f
--- /dev/null
+++ b/arch/arm/dts/imx6q-embedsky-e9.dtsi
@@ -0,0 +1,395 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include dt-bindings/gpio/gpio.h
+#include dt-bindings/input/input.h
+
+/ {
+ model = Embedsky E9;
+ compatible = embedsky,e9, fsl,imx6q;
+
+ regulators {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ reg_2p5v: regulator@0 {
+ compatible = regulator-fixed;
+ reg = 0;
+ regulator-name = 2P5V;
+ regulator-min-microvolt = 250;
+ regulator-max-microvolt = 250;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator@1 {
+ compatible = regulator-fixed;
+ reg = 1;
+ regulator-name = 3P3V;
+ regulator-min-microvolt = 330;
+ regulator-max-microvolt = 330;
+ regulator-always-on;
+ };
+
+ reg_usb_otg_vbus: regulator@2 {
+ compatible = regulator-fixed;
+ reg = 2;
+ regulator-name = usb_otg_vbus;
+ regulator-min-microvolt = 500;
+ regulator-max-microvolt = 500;
+ gpio = gpio3 22 0;
+ enable-active-high;
+ };
+
+ reg_usb_h1_vbus: regulator@3 {
+ compatible = regulator-fixed;
+ reg = 3;
+ regulator-name = usb_h1_vbus;
+ regulator-min-microvolt = 500;
+ regulator-max-microvolt = 500;
+ gpio = gpio1 29 0;
+ enable-active-high;
+ };
+
+ };
+
+ gpio-keys {
+ compatible = gpio-keys;
+ pinctrl-names = default;
+ pinctrl-0 = pinctrl_gpio_keys;
+
+ power {
+ label = Power Button;
+ gpios = gpio6 31 GPIO_ACTIVE_LOW;
+ gpio-key,wakeup;
+ linux,code = KEY_POWER;
+ };
+
+ volume-up {
+ label = Volume Up;
+ gpios = gpio4 8 GPIO_ACTIVE_LOW;
+ gpio-key,wakeup;
+ linux,code = KEY_VOLUMEUP;
+ };
+
+ volume-down {
+ label = Volume Down;
+ gpios = gpio4 9 GPIO_ACTIVE_LOW;
+ gpio-key,wakeup;
+ linux,code = KEY_VOLUMEDOWN;
+ };
+ };
+
+};
+
+audmux {
+ pinctrl-names = default;
+ pinctrl-0 = pinctrl_audmux;
+ status = okay;
+};
+
+fec {
+ pinctrl-names = default;
+ pinctrl-0 = pinctrl_enet;
+ phy-mode = rgmii;
+ phy-supply=reg_3p3v;
+ status = okay;
+};
+
+i2c1 {
+ clock-frequency = 10;
+ pinctrl-names = default;
+ pinctrl-0 = pinctrl_i2c1;
+ status = okay;
+
+};
+
+i2c2 {
+ clock-frequency = 10;
+ pinctrl-names = default;
+ pinctrl-0 = pinctrl_i2c2;
+ status = okay;
+};
+
+i2c3 {
+ clock-frequency = 10;
+ pinctrl-names = default;
+ pinctrl-0 = pinctrl_i2c3;
+ status = okay;
+};
+
+iomuxc {
+ pinctrl-names = default;
+ pinctrl-0 = pinctrl_hog;
+
Re: [PATCH v2 1/2] pinctrl: at91: add pinctrl driver
On Tue, Sep 02, 2014 at 11:01:17AM +0200, Raphaël Poggi wrote: Hi, I can add all the functions from mach-at91/gpio.h in mach-at91/include/gpio.h and remove mach-at91/gpio.h. Is this a valid solution ? Sounds good. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH v3 0/3] Add atmel pinctrl driver
Change since v2: * Move all functions from mach-at91/gpio.h to match-at91/include/gpio.h * Remove pinctrl-at91.h file in patch Change since v1: * Fix coding style issue * Register gpio clocks with CLKDEV_DEV_ID instead of CLKDEV_CON_DEV_ID This patchset add atmel pinctrl/gpio driver and the corresponding clocks for the at91sam9g45 device. The pinctrl driver also include the gpio driver (like in linux) because the gpio and pinctrl parts share same structures. Raphaël Poggi (3): (1) arm: mach-at91: move gpio.h to include folder (2) pinctrl: at91: add pinctrl driver (3) at91sam9g45: add device tree gpio clocks arch/arm/mach-at91/at91sam9g45.c |5 + arch/arm/mach-at91/gpio.c |2 +- arch/arm/mach-at91/gpio.h | 148 - arch/arm/mach-at91/include/mach/gpio.h | 149 + drivers/pinctrl/Kconfig|6 + drivers/pinctrl/Makefile |1 + drivers/pinctrl/pinctrl-at91.c | 527 7 files changed, 689 insertions(+), 149 deletions(-) ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH v3 3/3] at91sam9g45: add device tree gpio clocks
Signed-off-by: Raphaël Poggi poggi.r...@gmail.com
---
arch/arm/mach-at91/at91sam9g45.c |5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index d19d26a..8c020fa 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -201,6 +201,11 @@ static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_DEV_ID(at91rm9200-gpio2, pioC_clk),
CLKDEV_DEV_ID(at91rm9200-gpio3, pioDE_clk),
CLKDEV_DEV_ID(at91rm9200-gpio4, pioDE_clk),
+ CLKDEV_DEV_ID(f200.gpio, pioA_clk),
+ CLKDEV_DEV_ID(f400.gpio, pioB_clk),
+ CLKDEV_DEV_ID(f600.gpio, pioC_clk),
+ CLKDEV_DEV_ID(f800.gpio, pioDE_clk),
+ CLKDEV_DEV_ID(fa00.gpio, pioDE_clk),
CLKDEV_DEV_ID(at91-pit, mck),
CLKDEV_CON_DEV_ID(hck1, atmel_lcdfb, lcdc_clk),
};
--
1.7.9.5
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[PATCH v3 1/3] arm: mach-at91: move gpio.h to include folder
This commit add functions from mach-at91/gpio.h in include/mach/gpio.h.
This allow to use these functions outside the mach-at91 folder.
Signed-off-by: Raphaël Poggi poggi.r...@gmail.com
---
arch/arm/mach-at91/gpio.c |2 +-
arch/arm/mach-at91/gpio.h | 148 ---
arch/arm/mach-at91/include/mach/gpio.h | 149
3 files changed, 150 insertions(+), 149 deletions(-)
delete mode 100644 arch/arm/mach-at91/gpio.h
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index 4f2c76e..402634b 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -32,7 +32,7 @@
#include driver.h
#include getopt.h
-#include gpio.h
+#include mach/gpio.h
#define MAX_GPIO_BANKS 5
diff --git a/arch/arm/mach-at91/gpio.h b/arch/arm/mach-at91/gpio.h
deleted file mode 100644
index d40628b..000
--- a/arch/arm/mach-at91/gpio.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD
plagn...@jcrosoft.com
- *
- * Under GPLv2 only
- */
-
-#ifndef __AT91_GPIO_H__
-#define __AT91_GPIO_H__
-
-#ifndef __gpio_init
-#define __gpio_init
-#endif
-
-#define MAX_NB_GPIO_PER_BANK 32
-
-static inline unsigned pin_to_bank(unsigned pin)
-{
- return pin / MAX_NB_GPIO_PER_BANK;
-}
-
-static inline unsigned pin_to_bank_offset(unsigned pin)
-{
- return pin % MAX_NB_GPIO_PER_BANK;
-}
-
-static inline unsigned pin_to_mask(unsigned pin)
-{
- return 1 pin_to_bank_offset(pin);
-}
-
-static __gpio_init void at91_mux_disable_interrupt(void __iomem *pio, unsigned
mask)
-{
- __raw_writel(mask, pio + PIO_IDR);
-}
-
-static __gpio_init void at91_mux_set_pullup(void __iomem *pio, unsigned mask,
bool on)
-{
- __raw_writel(mask, pio + (on ? PIO_PUER : PIO_PUDR));
-}
-
-static __gpio_init void at91_mux_set_multidrive(void __iomem *pio, unsigned
mask, bool on)
-{
- __raw_writel(mask, pio + (on ? PIO_MDER : PIO_MDDR));
-}
-
-static __gpio_init void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
-{
- __raw_writel(mask, pio + PIO_ASR);
-}
-
-static __gpio_init void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
-{
- __raw_writel(mask, pio + PIO_BSR);
-}
-
-static __gpio_init void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned
mask)
-{
-
- __raw_writel(__raw_readl(pio + PIO_ABCDSR1) ~mask,
- pio + PIO_ABCDSR1);
- __raw_writel(__raw_readl(pio + PIO_ABCDSR2) ~mask,
- pio + PIO_ABCDSR2);
-}
-
-static __gpio_init void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned
mask)
-{
- __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask,
- pio + PIO_ABCDSR1);
- __raw_writel(__raw_readl(pio + PIO_ABCDSR2) ~mask,
- pio + PIO_ABCDSR2);
-}
-
-static __gpio_init void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned
mask)
-{
- __raw_writel(__raw_readl(pio + PIO_ABCDSR1) ~mask, pio + PIO_ABCDSR1);
- __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
-}
-
-static __gpio_init void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned
mask)
-{
- __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
- __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
-}
-
-static __gpio_init void at91_mux_set_deglitch(void __iomem *pio, unsigned
mask, bool is_on)
-{
- __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
-}
-
-static __gpio_init void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned
mask, bool is_on)
-{
- if (is_on)
- __raw_writel(mask, pio + PIO_IFSCDR);
- at91_mux_set_deglitch(pio, mask, is_on);
-}
-
-static __gpio_init void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned
mask,
- bool is_on, u32 div)
-{
- if (is_on) {
- __raw_writel(mask, pio + PIO_IFSCER);
- __raw_writel(div PIO_SCDR_DIV, pio + PIO_SCDR);
- __raw_writel(mask, pio + PIO_IFER);
- } else {
- __raw_writel(mask, pio + PIO_IFDR);
- }
-}
-
-static __gpio_init void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned
mask, bool is_on)
-{
- __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
-}
-
-static __gpio_init void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio,
unsigned mask)
-{
- __raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
-}
-
-static __gpio_init void at91_mux_gpio_disable(void __iomem *pio, unsigned mask)
-{
- __raw_writel(mask, pio + PIO_PDR);
-}
-
-static __gpio_init void at91_mux_gpio_enable(void __iomem *pio, unsigned mask)
-{
- __raw_writel(mask, pio + PIO_PER);
-}
-
-static __gpio_init void at91_mux_gpio_input(void __iomem *pio, unsigned mask,
[PATCH v3 2/3] pinctrl: at91: add pinctrl driver
This driver is based on mach-at91/gpio.c and linux pinctrl driver.
The driver contains the gpio and pinctrl parts (like in linux) because the two
parts
share some structures and logics.
Signed-off-by: Raphaël Poggi poggi.r...@gmail.com
---
drivers/pinctrl/Kconfig|6 +
drivers/pinctrl/Makefile |1 +
drivers/pinctrl/pinctrl-at91.c | 527
3 files changed, 534 insertions(+)
create mode 100644 drivers/pinctrl/pinctrl-at91.c
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index dffaa4e..ce55c7b 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -7,6 +7,12 @@ config PINCTRL
from the devicetree. Legacy drivers here may not need this core
support but instead provide their own SoC specific APIs
+config PINCTRL_AT91
+ select PINCTRL
+ bool
+ help
+ The pinmux controller found on AT91 SoCs.
+
config PINCTRL_IMX_IOMUX_V1
select PINCTRL if OFDEVICE
bool
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 566ba11..3ea8649 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -1,4 +1,5 @@
obj-$(CONFIG_PINCTRL) += pinctrl.o
+obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
obj-$(CONFIG_PINCTRL_IMX_IOMUX_V1) += imx-iomux-v1.o
obj-$(CONFIG_PINCTRL_IMX_IOMUX_V2) += imx-iomux-v2.o
obj-$(CONFIG_PINCTRL_IMX_IOMUX_V3) += imx-iomux-v3.o
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
new file mode 100644
index 000..433862a
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -0,0 +1,527 @@
+/*
+ * Copyright (C) 2005 HP Labs
+ * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD
plagn...@jcrosoft.com
+ * Copyright (C) 2014 Raphaël Poggi
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include common.h
+#include command.h
+#include complete.h
+#include linux/clk.h
+#include linux/err.h
+#include errno.h
+#include io.h
+#include gpio.h
+#include init.h
+#include driver.h
+#include getopt.h
+
+#include mach/at91_pio.h
+#include mach/gpio.h
+
+#include pinctrl.h
+
+struct at91_pinctrl {
+ struct pinctrl_device pctl;
+ struct at91_pinctrl_mux_ops *ops;
+};
+
+struct at91_gpio_chip {
+ struct gpio_chipchip;
+ void __iomem*regbase; /* PIO bank virtual address */
+ struct at91_pinctrl_mux_ops *ops; /* ops */
+};
+
+enum at91_mux {
+ AT91_MUX_GPIO = 0,
+ AT91_MUX_PERIPH_A = 1,
+ AT91_MUX_PERIPH_B = 2,
+ AT91_MUX_PERIPH_C = 3,
+ AT91_MUX_PERIPH_D = 4,
+};
+
+#define MAX_GPIO_BANKS 5
+#define to_at91_pinctrl(c) container_of(c, struct at91_pinctrl, pctl);
+#define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
+
+#define PULL_UP (1 0)
+#define MULTI_DRIVE (1 1)
+#define DEGLITCH(1 2)
+#define PULL_DOWN (1 3)
+#define DIS_SCHMIT (1 4)
+#define DEBOUNCE(1 16)
+#define DEBOUNCE_VAL_SHIFT 17
+#define DEBOUNCE_VAL(0x3fff DEBOUNCE_VAL_SHIFT)
+
+static int gpio_banks;
+
+static struct at91_gpio_chip gpio_chip[MAX_GPIO_BANKS];
+
+static inline void __iomem *pin_to_controller(struct at91_pinctrl *info,
unsigned pin)
+{
+ pin /= MAX_NB_GPIO_PER_BANK;
+ if (likely(pin gpio_banks))
+ return gpio_chip[pin].regbase;
+
+ return NULL;
+}
+
+/**
+ * struct at91_pinctrl_mux_ops - describes an At91 mux ops group
+ * on new IP with support for periph C and D the way to mux in
+ * periph A and B has changed
+ * So provide the right call back
+ * if not present means the IP does not support it
+ * @get_periph: return the periph mode configured
+ * @mux_A_periph: mux as periph A
+ * @mux_B_periph: mux as periph B
+ * @mux_C_periph: mux as periph C
+ * @mux_D_periph: mux as periph D
+ * @set_deglitch: enable/disable deglitch
+ * @set_debounce: enable/disable debounce
+ * @set_pulldown: enable/disable pulldown
+ * @disable_schmitt_trig: disable schmitt trigger
+ */
+struct at91_pinctrl_mux_ops {
+ enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask);
+ void (*mux_A_periph)(void __iomem *pio, unsigned mask);
+ void (*mux_B_periph)(void __iomem *pio, unsigned mask);
+ void (*mux_C_periph)(void __iomem *pio, unsigned mask);
+ void (*mux_D_periph)(void __iomem *pio, unsigned mask);
+ bool (*get_deglitch)(void __iomem *pio,
[PATCH] mtd: atmel_nand: fix null pointer dereference
We need to allocate pdata for device tree and non device tree probe.
In device tree probe we use pdata to fill structure member with dts data.
In non device tree probe we use the pdata to handle platform_data.
Signed-off-by: Raphaël Poggi poggi.r...@gmail.com
---
drivers/mtd/nand/atmel_nand.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 910ecc3..1e7c6c6 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -1194,6 +1194,10 @@ static int __init atmel_nand_probe(struct device_d *dev)
if (!host)
return -ENOMEM;
+ pdata = kzalloc(sizeof(struct atmel_nand_data), GFP_KERNEL);
+ if (!pdata)
+ return -ENOMEM;
+
host-io_base = dev_request_mem_region(dev, 0);
mtd = host-mtd;
@@ -1206,10 +1210,6 @@ static int __init atmel_nand_probe(struct device_d *dev)
if (res)
goto err_no_card;
} else {
- pdata = kzalloc(sizeof(struct atmel_nand_data), GFP_KERNEL);
- if (!pdata)
- return -ENOMEM;
-
memcpy(host-board, dev-platform_data, sizeof(struct
atmel_nand_data));
}
--
1.8.3.2
___
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Re: [PATCH] mtd: atmel_nand: fix null pointer dereference
I think this patch could be squash in [PATCH v3 3/3] mtd: atmel_nand:
add support for device tree
2014-09-02 21:02 GMT+02:00 Raphaël Poggi poggi.r...@gmail.com:
We need to allocate pdata for device tree and non device tree probe.
In device tree probe we use pdata to fill structure member with dts data.
In non device tree probe we use the pdata to handle platform_data.
Signed-off-by: Raphaël Poggi poggi.r...@gmail.com
---
drivers/mtd/nand/atmel_nand.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 910ecc3..1e7c6c6 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -1194,6 +1194,10 @@ static int __init atmel_nand_probe(struct device_d
*dev)
if (!host)
return -ENOMEM;
+ pdata = kzalloc(sizeof(struct atmel_nand_data), GFP_KERNEL);
+ if (!pdata)
+ return -ENOMEM;
+
host-io_base = dev_request_mem_region(dev, 0);
mtd = host-mtd;
@@ -1206,10 +1210,6 @@ static int __init atmel_nand_probe(struct device_d
*dev)
if (res)
goto err_no_card;
} else {
- pdata = kzalloc(sizeof(struct atmel_nand_data), GFP_KERNEL);
- if (!pdata)
- return -ENOMEM;
-
memcpy(host-board, dev-platform_data, sizeof(struct
atmel_nand_data));
}
--
1.8.3.2
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