Re: [PATCH] pinctrl: at91: add driver data

2014-09-08 Thread Sascha Hauer 
On Mon, Sep 08, 2014 at 03:07:55PM +0200, Raphaël Poggi wrote:
> This commit adds the driver data for the gpio-at91 driver.


Could you explain what exactly this patch fixes? It seems without this
patch the pinctrl part is non functional. Is this correct?

Sascha

> 
> Signed-off-by: Raphaël Poggi 
> ---
>  drivers/pinctrl/pinctrl-at91.c | 10 ++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
> index d3423d0..29e54cf 100644
> --- a/drivers/pinctrl/pinctrl-at91.c
> +++ b/drivers/pinctrl/pinctrl-at91.c
> @@ -606,8 +606,10 @@ static struct gpio_ops at91_gpio_ops = {
>  static struct of_device_id at91_gpio_dt_ids[] = {
>   {
>   .compatible = "atmel,at91rm9200-gpio",
> +.data = (unsigned long)&at91rm9200_ops,
>   }, {
>   .compatible = "atmel,at91sam9x5-gpio",
> + .data = (unsigned long)&at91sam9x5_ops,
>   }, {
>   /* sentinel */
>   },
> @@ -629,6 +631,12 @@ static int at91_gpio_probe(struct device_d *dev)
>  
>   at91_gpio = &gpio_chip[alias_idx];
>  
> + ret = dev_get_drvdata(dev, (unsigned long *)&at91_gpio->ops);
> +if (ret) {
> +dev_err(dev, "dev_get_drvdata failed: %d\n", ret);
> +return ret;
> +}
> +
>   clk = clk_get(dev, NULL);
>   if (IS_ERR(clk)) {
>   ret = PTR_ERR(clk);
> @@ -667,8 +675,10 @@ static int at91_gpio_probe(struct device_d *dev)
>  static struct platform_device_id at91_gpio_ids[] = {
>   {
>   .name = "at91rm9200-gpio",
> +.driver_data = (unsigned long)&at91rm9200_ops,
>   }, {
>   .name = "at91sam9x5-gpio",
> + .driver_data = (unsigned long)&at91sam9x5_ops,
>   }, {
>   /* sentinel */
>   },
> -- 
> 2.1.0
> 
> 
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Re: [PATCH] mach-at91: declare device tree clock

2014-09-08 Thread Sascha Hauer 
On Mon, Sep 08, 2014 at 03:07:54PM +0200, Raphaël Poggi wrote:
> This commit use the clkdev_add_physbase function, to declare device tree and 
> non device tree gpio clocks.
> 
> Signed-off-by: Raphaël Poggi 
> ---
>  arch/arm/mach-at91/at91sam9g45.c | 13 -
>  1 file changed, 8 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/mach-at91/at91sam9g45.c 
> b/arch/arm/mach-at91/at91sam9g45.c
> index 9a50deb..f8d069f 100644
> --- a/arch/arm/mach-at91/at91sam9g45.c
> +++ b/arch/arm/mach-at91/at91sam9g45.c
> @@ -192,11 +192,6 @@ static struct clk_lookup periph_clocks_lookups[] = {
>   CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci1", &mmc1_clk),
>   CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi0", &spi0_clk),
>   CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi1", &spi1_clk),
> - CLKDEV_DEV_ID("at91rm9200-gpio0", &pioA_clk),
> - CLKDEV_DEV_ID("at91rm9200-gpio1", &pioB_clk),
> - CLKDEV_DEV_ID("at91rm9200-gpio2", &pioC_clk),
> - CLKDEV_DEV_ID("at91rm9200-gpio3", &pioDE_clk),
> - CLKDEV_DEV_ID("at91rm9200-gpio4", &pioDE_clk),
>   CLKDEV_DEV_ID("at91-pit", &mck),
>   CLKDEV_CON_DEV_ID("hck1", "atmel_lcdfb", &lcdc_clk),
>  };
> @@ -238,6 +233,14 @@ static void __init at91sam9g45_register_clocks(void)
>   clkdev_add_table(usart_clocks_lookups,
>ARRAY_SIZE(usart_clocks_lookups));
>  
> + clkdev_add_physbase(&twi0_clk, 0xfff84000, NULL);
> + clkdev_add_physbase(&twi1_clk, 0xfff88000, NULL);
> +clkdev_add_physbase(&pioA_clk, 0xf200, NULL);
> +clkdev_add_physbase(&pioB_clk, 0xf400, NULL);
> +clkdev_add_physbase(&pioC_clk, 0xf600, NULL);
> +clkdev_add_physbase(&pioDE_clk, 0xf800, NULL);
> +clkdev_add_physbase(&pioDE_clk, 0xfa00, NULL);
> +

Indentation is done with tabs here, please fix. Also the other patches
contain spaces for indentation.

Sascha

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[PATCH v2] pinctrl: at91: add driver data

2014-09-08 Thread Raphaël Poggi 
This commit adds the driver data for the gpio-at91 driver.

Signed-off-by: Raphaël Poggi 
---
 drivers/pinctrl/pinctrl-at91.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index d3423d0..3c6b38c 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -606,8 +606,10 @@ static struct gpio_ops at91_gpio_ops = {
 static struct of_device_id at91_gpio_dt_ids[] = {
{
.compatible = "atmel,at91rm9200-gpio",
+   .data = (unsigned long)&at91rm9200_ops,
}, {
.compatible = "atmel,at91sam9x5-gpio",
+   .data = (unsigned long)&at91sam9x5_ops,
}, {
/* sentinel */
},
@@ -629,6 +631,12 @@ static int at91_gpio_probe(struct device_d *dev)
 
at91_gpio = &gpio_chip[alias_idx];
 
+   ret = dev_get_drvdata(dev, (unsigned long *)&at91_gpio->ops);
+   if (ret) {
+   dev_err(dev, "dev_get_drvdata failed: %d\n", ret);
+   return ret;
+   }
+
clk = clk_get(dev, NULL);
if (IS_ERR(clk)) {
ret = PTR_ERR(clk);
@@ -667,8 +675,10 @@ static int at91_gpio_probe(struct device_d *dev)
 static struct platform_device_id at91_gpio_ids[] = {
{
.name = "at91rm9200-gpio",
+   .driver_data = (unsigned long)&at91rm9200_ops,
}, {
.name = "at91sam9x5-gpio",
+   .driver_data = (unsigned long)&at91sam9x5_ops,
}, {
/* sentinel */
},
-- 
2.1.0


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[PATCH v2] mach-at91: declare device tree clock

2014-09-08 Thread Raphaël Poggi 
This commit use the clkdev_add_physbase function, to declare device tree and 
non device tree gpio clocks.

Signed-off-by: Raphaël Poggi 
---
 arch/arm/mach-at91/at91sam9g45.c | 13 -
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 9a50deb..584ef9d 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -192,11 +192,6 @@ static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci1", &mmc1_clk),
CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi0", &spi0_clk),
CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi1", &spi1_clk),
-   CLKDEV_DEV_ID("at91rm9200-gpio0", &pioA_clk),
-   CLKDEV_DEV_ID("at91rm9200-gpio1", &pioB_clk),
-   CLKDEV_DEV_ID("at91rm9200-gpio2", &pioC_clk),
-   CLKDEV_DEV_ID("at91rm9200-gpio3", &pioDE_clk),
-   CLKDEV_DEV_ID("at91rm9200-gpio4", &pioDE_clk),
CLKDEV_DEV_ID("at91-pit", &mck),
CLKDEV_CON_DEV_ID("hck1", "atmel_lcdfb", &lcdc_clk),
 };
@@ -238,6 +233,14 @@ static void __init at91sam9g45_register_clocks(void)
clkdev_add_table(usart_clocks_lookups,
 ARRAY_SIZE(usart_clocks_lookups));
 
+   clkdev_add_physbase(&twi0_clk, 0xfff84000, NULL);
+   clkdev_add_physbase(&twi1_clk, 0xfff88000, NULL);
+   clkdev_add_physbase(&pioA_clk, 0xf200, NULL);
+   clkdev_add_physbase(&pioB_clk, 0xf400, NULL);
+   clkdev_add_physbase(&pioC_clk, 0xf600, NULL);
+   clkdev_add_physbase(&pioDE_clk, 0xf800, NULL);
+   clkdev_add_physbase(&pioDE_clk, 0xfa00, NULL);
+
if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11())
clk_register(&vdec_clk);
 
-- 
2.1.0


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Re: AT91 pinctrl/gpio fixes

2014-09-08 Thread Raphaël Poggi 
Hello, I just send patchs, to fix all this issues.

2014-09-08 15:23 GMT+02:00 Sascha Hauer :
> Unfortunately the transition to pinctrl for AT91 caused some damage.
> The 926x do not compile anymore. Even when this is fixed the boards
> won't work since the new pinctrl driver uses of_alias_get_id() even
> for the platform case to translate the device into a gpio chip.
>
> Sascha
>
> 
> Sascha Hauer (4):
>   ARM: AT91: Add missing include
>   ARM: AT91: Make gpio mux functions inline
>   pinctrl: AT91: Only use of_alias_get_id when probed from devicetree
>   pinctrl: AT91: use alias_idx to calculate the base gpio number
>
>  arch/arm/mach-at91/at91sam926x_lowlevel_init.c |  2 +-
>  arch/arm/mach-at91/include/mach/gpio.h | 42 
> --
>  drivers/pinctrl/pinctrl-at91.c |  9 --
>  3 files changed, 27 insertions(+), 26 deletions(-)
>
>
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[PATCH 3/4] pinctrl: AT91: Only use of_alias_get_id when probed from devicetree

2014-09-08 Thread Sascha Hauer 
If probed from platform data we have to use dev->id instead.

Signed-off-by: Sascha Hauer 
---
 drivers/pinctrl/pinctrl-at91.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index e212f7a..3c194df 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -618,10 +618,15 @@ static int at91_gpio_probe(struct device_d *dev)
struct at91_gpio_chip *at91_gpio;
struct clk *clk;
int ret;
-   int alias_idx = of_alias_get_id(dev->device_node, "gpio");
+   int alias_idx;
 
BUG_ON(dev->id > MAX_GPIO_BANKS);
 
+   if (dev->device_node)
+   alias_idx = of_alias_get_id(dev->device_node, "gpio");
+   else
+   alias_idx = dev->id;
+
at91_gpio = &gpio_chip[alias_idx];
 
clk = clk_get(dev, NULL);
-- 
2.1.0


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[PATCH 1/4] ARM: AT91: Add missing include

2014-09-08 Thread Sascha Hauer 
the gpio mux functions were moved to mach/gpio.h. Add the missing
include.

Signed-off-by: Sascha Hauer 
---
 arch/arm/mach-at91/at91sam926x_lowlevel_init.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-at91/at91sam926x_lowlevel_init.c 
b/arch/arm/mach-at91/at91sam926x_lowlevel_init.c
index e69e4a8..59ea83e 100644
--- a/arch/arm/mach-at91/at91sam926x_lowlevel_init.c
+++ b/arch/arm/mach-at91/at91sam926x_lowlevel_init.c
@@ -20,6 +20,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
-- 
2.1.0


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AT91 pinctrl/gpio fixes

2014-09-08 Thread Sascha Hauer 
Unfortunately the transition to pinctrl for AT91 caused some damage.
The 926x do not compile anymore. Even when this is fixed the boards
won't work since the new pinctrl driver uses of_alias_get_id() even
for the platform case to translate the device into a gpio chip.

Sascha


Sascha Hauer (4):
  ARM: AT91: Add missing include
  ARM: AT91: Make gpio mux functions inline
  pinctrl: AT91: Only use of_alias_get_id when probed from devicetree
  pinctrl: AT91: use alias_idx to calculate the base gpio number

 arch/arm/mach-at91/at91sam926x_lowlevel_init.c |  2 +-
 arch/arm/mach-at91/include/mach/gpio.h | 42 --
 drivers/pinctrl/pinctrl-at91.c |  9 --
 3 files changed, 27 insertions(+), 26 deletions(-)


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[PATCH 2/4] ARM: AT91: Make gpio mux functions inline

2014-09-08 Thread Sascha Hauer 
Otherwise we get a unused function warning each time mach/gpio.h
is included.

Signed-off-by: Sascha Hauer 
---
 arch/arm/mach-at91/at91sam926x_lowlevel_init.c |  1 -
 arch/arm/mach-at91/include/mach/gpio.h | 42 --
 2 files changed, 19 insertions(+), 24 deletions(-)

diff --git a/arch/arm/mach-at91/at91sam926x_lowlevel_init.c 
b/arch/arm/mach-at91/at91sam926x_lowlevel_init.c
index 59ea83e..6452bdd 100644
--- a/arch/arm/mach-at91/at91sam926x_lowlevel_init.c
+++ b/arch/arm/mach-at91/at91sam926x_lowlevel_init.c
@@ -25,7 +25,6 @@
 #include 
 #include 
 
-#define __gpio_init inline
 #include "gpio.h"
 
 static void inline access_sdram(void)
diff --git a/arch/arm/mach-at91/include/mach/gpio.h 
b/arch/arm/mach-at91/include/mach/gpio.h
index 6a6b9cd..4e9d686 100644
--- a/arch/arm/mach-at91/include/mach/gpio.h
+++ b/arch/arm/mach-at91/include/mach/gpio.h
@@ -9,10 +9,6 @@
 
 #include 
 
-#ifndef __gpio_init
-#define __gpio_init
-#endif
-
 #define MAX_NB_GPIO_PER_BANK   32
 
 static inline unsigned pin_to_bank(unsigned pin)
@@ -30,32 +26,32 @@ static inline unsigned pin_to_mask(unsigned pin)
return 1 << pin_to_bank_offset(pin);
 }
 
-static __gpio_init void at91_mux_disable_interrupt(void __iomem *pio, unsigned 
mask)
+static inline void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
 {
__raw_writel(mask, pio + PIO_IDR);
 }
 
-static __gpio_init void at91_mux_set_pullup(void __iomem *pio, unsigned mask, 
bool on)
+static inline void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool 
on)
 {
__raw_writel(mask, pio + (on ? PIO_PUER : PIO_PUDR));
 }
 
-static __gpio_init void at91_mux_set_multidrive(void __iomem *pio, unsigned 
mask, bool on)
+static inline void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, 
bool on)
 {
__raw_writel(mask, pio + (on ? PIO_MDER : PIO_MDDR));
 }
 
-static __gpio_init void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
+static inline void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
 {
__raw_writel(mask, pio + PIO_ASR);
 }
 
-static __gpio_init void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
+static inline void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
 {
__raw_writel(mask, pio + PIO_BSR);
 }
 
-static __gpio_init void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned 
mask)
+static inline void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask)
 {
 
__raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask,
@@ -64,7 +60,7 @@ static __gpio_init void at91_mux_pio3_set_A_periph(void 
__iomem *pio, unsigned m
pio + PIO_ABCDSR2);
 }
 
-static __gpio_init void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned 
mask)
+static inline void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask)
 {
__raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask,
pio + PIO_ABCDSR1);
@@ -72,31 +68,31 @@ static __gpio_init void at91_mux_pio3_set_B_periph(void 
__iomem *pio, unsigned m
pio + PIO_ABCDSR2);
 }
 
-static __gpio_init void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned 
mask)
+static inline void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask)
 {
__raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
__raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
 }
 
-static __gpio_init void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned 
mask)
+static inline void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask)
 {
__raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
__raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
 }
 
-static __gpio_init void at91_mux_set_deglitch(void __iomem *pio, unsigned 
mask, bool is_on)
+static inline void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, 
bool is_on)
 {
__raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
 }
 
-static __gpio_init void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned 
mask, bool is_on)
+static inline void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned 
mask, bool is_on)
 {
if (is_on)
__raw_writel(mask, pio + PIO_IFSCDR);
at91_mux_set_deglitch(pio, mask, is_on);
 }
 
-static __gpio_init void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned 
mask,
+static inline void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask,
bool is_on, u32 div)
 {
if (is_on) {
@@ -108,38 +104,38 @@ static __gpio_init void at91_mux_pio3_set_debounce(void 
__iomem *pio, unsigned m
}
 }
 
-static __gpio_init void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned 
mask, bool is_on)
+static inline void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned 
mask, bool is_on)

[PATCH 4/4] pinctrl: AT91: use alias_idx to calculate the base gpio number

2014-09-08 Thread Sascha Hauer 
For the devicetree case alias_idx contains the gpio bank number.
dev->id has no meaning in this case.

Signed-off-by: Sascha Hauer 
---
 drivers/pinctrl/pinctrl-at91.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 3c194df..e77c8c4 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -651,7 +651,7 @@ static int at91_gpio_probe(struct device_d *dev)
at91_gpio->chip.ops = &at91_gpio_ops;
at91_gpio->chip.ngpio = MAX_NB_GPIO_PER_BANK;
at91_gpio->chip.dev = dev;
-   at91_gpio->chip.base = dev->id * MAX_NB_GPIO_PER_BANK;
+   at91_gpio->chip.base = alias_idx * MAX_NB_GPIO_PER_BANK;
 
ret = gpiochip_add(&at91_gpio->chip);
if (ret) {
-- 
2.1.0


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[PATCH] mach-at91: declare device tree clock

2014-09-08 Thread Raphaël Poggi 
This commit use the clkdev_add_physbase function, to declare device tree and 
non device tree gpio clocks.

Signed-off-by: Raphaël Poggi 
---
 arch/arm/mach-at91/at91sam9g45.c | 13 -
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 9a50deb..f8d069f 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -192,11 +192,6 @@ static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci1", &mmc1_clk),
CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi0", &spi0_clk),
CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi1", &spi1_clk),
-   CLKDEV_DEV_ID("at91rm9200-gpio0", &pioA_clk),
-   CLKDEV_DEV_ID("at91rm9200-gpio1", &pioB_clk),
-   CLKDEV_DEV_ID("at91rm9200-gpio2", &pioC_clk),
-   CLKDEV_DEV_ID("at91rm9200-gpio3", &pioDE_clk),
-   CLKDEV_DEV_ID("at91rm9200-gpio4", &pioDE_clk),
CLKDEV_DEV_ID("at91-pit", &mck),
CLKDEV_CON_DEV_ID("hck1", "atmel_lcdfb", &lcdc_clk),
 };
@@ -238,6 +233,14 @@ static void __init at91sam9g45_register_clocks(void)
clkdev_add_table(usart_clocks_lookups,
 ARRAY_SIZE(usart_clocks_lookups));
 
+   clkdev_add_physbase(&twi0_clk, 0xfff84000, NULL);
+   clkdev_add_physbase(&twi1_clk, 0xfff88000, NULL);
+clkdev_add_physbase(&pioA_clk, 0xf200, NULL);
+clkdev_add_physbase(&pioB_clk, 0xf400, NULL);
+clkdev_add_physbase(&pioC_clk, 0xf600, NULL);
+clkdev_add_physbase(&pioDE_clk, 0xf800, NULL);
+clkdev_add_physbase(&pioDE_clk, 0xfa00, NULL);
+
if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11())
clk_register(&vdec_clk);
 
-- 
2.1.0


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[PATCH] pinctrl: at91: add driver data

2014-09-08 Thread Raphaël Poggi 
This commit adds the driver data for the gpio-at91 driver.

Signed-off-by: Raphaël Poggi 
---
 drivers/pinctrl/pinctrl-at91.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index d3423d0..29e54cf 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -606,8 +606,10 @@ static struct gpio_ops at91_gpio_ops = {
 static struct of_device_id at91_gpio_dt_ids[] = {
{
.compatible = "atmel,at91rm9200-gpio",
+.data = (unsigned long)&at91rm9200_ops,
}, {
.compatible = "atmel,at91sam9x5-gpio",
+   .data = (unsigned long)&at91sam9x5_ops,
}, {
/* sentinel */
},
@@ -629,6 +631,12 @@ static int at91_gpio_probe(struct device_d *dev)
 
at91_gpio = &gpio_chip[alias_idx];
 
+   ret = dev_get_drvdata(dev, (unsigned long *)&at91_gpio->ops);
+if (ret) {
+dev_err(dev, "dev_get_drvdata failed: %d\n", ret);
+return ret;
+}
+
clk = clk_get(dev, NULL);
if (IS_ERR(clk)) {
ret = PTR_ERR(clk);
@@ -667,8 +675,10 @@ static int at91_gpio_probe(struct device_d *dev)
 static struct platform_device_id at91_gpio_ids[] = {
{
.name = "at91rm9200-gpio",
+.driver_data = (unsigned long)&at91rm9200_ops,
}, {
.name = "at91sam9x5-gpio",
+   .driver_data = (unsigned long)&at91sam9x5_ops,
}, {
/* sentinel */
},
-- 
2.1.0


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[PATCH] pinctrl: at91: fix the pin_to_controller function

2014-09-08 Thread Raphaël Poggi 
Other functions use pin_to_controller to retrieve a at91_gpio_chip structure,
so fix pin_to_controller to return the correct value.

Signed-off-by: Raphaël Poggi 
---
 drivers/pinctrl/pinctrl-at91.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index e212f7a..3dc81c7 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -71,11 +71,11 @@ static int gpio_banks;
 
 static struct at91_gpio_chip gpio_chip[MAX_GPIO_BANKS];
 
-static inline void __iomem *pin_to_controller(unsigned pin)
+static inline struct at91_gpio_chip *pin_to_controller(unsigned pin)
 {
pin /= MAX_NB_GPIO_PER_BANK;
if (likely(pin < gpio_banks))
-   return gpio_chip[pin].regbase;
+   return &gpio_chip[pin];
 
return NULL;
 }
-- 
2.1.0


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[PATCH] pinctrl: at91: retrieve device id in non dtb probe

2014-09-08 Thread Raphaël Poggi 
We need to retrieve the device id in device tree/non device tree case.

Signed-off-by: Raphaël Poggi 
---
 drivers/pinctrl/pinctrl-at91.c | 11 ---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 3dc81c7..d3423d0 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -618,9 +618,14 @@ static int at91_gpio_probe(struct device_d *dev)
struct at91_gpio_chip *at91_gpio;
struct clk *clk;
int ret;
-   int alias_idx = of_alias_get_id(dev->device_node, "gpio");
+   int alias_idx;
 
-   BUG_ON(dev->id > MAX_GPIO_BANKS);
+   if (dev->device_node)
+   alias_idx = of_alias_get_id(dev->device_node, "gpio");
+   else
+   alias_idx = dev->id;
+
+   BUG_ON(alias_idx > MAX_GPIO_BANKS);
 
at91_gpio = &gpio_chip[alias_idx];
 
@@ -646,7 +651,7 @@ static int at91_gpio_probe(struct device_d *dev)
at91_gpio->chip.ops = &at91_gpio_ops;
at91_gpio->chip.ngpio = MAX_NB_GPIO_PER_BANK;
at91_gpio->chip.dev = dev;
-   at91_gpio->chip.base = dev->id * MAX_NB_GPIO_PER_BANK;
+   at91_gpio->chip.base = alias_idx * MAX_NB_GPIO_PER_BANK;
 
ret = gpiochip_add(&at91_gpio->chip);
if (ret) {
-- 
2.1.0


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[PATCH v4 0/5] firmware programming interface

2014-09-08 Thread Steffen Trumtrar 
Hi!

Changes since v3:
- minor clean up
- add binding documentation in 5/5
- rebase to v2014.09.0

The interface was tested on a Socfpga SoCkit board with v2014.09.0.

Regards,
Steffen


Juergen Beisert (2):
  Add a Firmware programming framework
  Firmware: provide a handler to program Altera FPGAs

Sascha Hauer (2):
  DT: Add binding for Altera FPGAs in passive-serial mode
  Firmware: socfpga: Add SoCFPGA FPGA program support

Steffen Trumtrar (1):
  DT: Add binding for Altera SOCFPGA FPGA Manager

 .../bindings/firmware/altr,passive-serial.txt  |  24 ++
 .../bindings/firmware/altr,socfpga-fpga-mgr.txt|  19 +
 arch/arm/dts/socfpga.dtsi  |   6 +
 arch/arm/mach-socfpga/Makefile |   1 +
 arch/arm/mach-socfpga/include/mach/socfpga-regs.h  |   2 +
 commands/Kconfig   |   9 +
 commands/Makefile  |   1 +
 commands/firmwareload.c|  66 
 common/Kconfig |   3 +
 common/Makefile|   1 +
 common/firmware.c  | 211 ++
 drivers/Kconfig|   1 +
 drivers/Makefile   |   1 +
 drivers/firmware/Kconfig   |  14 +
 drivers/firmware/Makefile  |   2 +
 drivers/firmware/altera_serial.c   | 315 +++
 drivers/firmware/socfpga.c | 440 +
 include/firmware.h |  42 ++
 18 files changed, 1158 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/firmware/altr,passive-serial.txt
 create mode 100644 
Documentation/devicetree/bindings/firmware/altr,socfpga-fpga-mgr.txt
 create mode 100644 commands/firmwareload.c
 create mode 100644 common/firmware.c
 create mode 100644 drivers/firmware/Kconfig
 create mode 100644 drivers/firmware/Makefile
 create mode 100644 drivers/firmware/altera_serial.c
 create mode 100644 drivers/firmware/socfpga.c
 create mode 100644 include/firmware.h

-- 
2.1.0


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[PATCH v4 3/5] DT: Add binding for Altera FPGAs in passive-serial mode

2014-09-08 Thread Steffen Trumtrar 
From: Sascha Hauer 

Altera FPGAs that are programmed via SPI use the passive serial protocol.
Add a simple binding that describes the setup for this usecase.

Cc: devicet...@vger.kernel.org
Signed-off-by: Sascha Hauer 
Signed-off-by: Steffen Trumtrar 
---
 .../bindings/firmware/altr,passive-serial.txt  | 24 ++
 1 file changed, 24 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/firmware/altr,passive-serial.txt

diff --git a/Documentation/devicetree/bindings/firmware/altr,passive-serial.txt 
b/Documentation/devicetree/bindings/firmware/altr,passive-serial.txt
new file mode 100644
index ..d357dd39cf67
--- /dev/null
+++ b/Documentation/devicetree/bindings/firmware/altr,passive-serial.txt
@@ -0,0 +1,24 @@
+Altera FPGAs in passive serial mode
+---
+
+This binding defines the control interface to Altera FPGAs in
+passive serial mode. This is used to upload the firmware and
+to start the FPGA.
+
+Required properties:
+- compatible: shall be "altr,fpga-passive-serial"
+- reg: SPI chip select
+- nstat-gpios: Specify GPIO for controlling the nstat pin
+- confd-gpios: Specify GPIO for controlling the confd pin
+- nconfig-gpios: Specify GPIO for controlling the nconfig pin
+
+Example:
+
+   fpga@0 {
+   compatible = "altr,fpga-passive-serial";
+   nstat-gpios = <&gpio4 18 0>;
+   confd-gpios = <&gpio4 19 0>;
+   nconfig-gpios = <&gpio4 20 0>;
+   spi-max-frequency = <1000>;
+   reg = <0>;
+   };
-- 
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[PATCH v4 5/5] DT: Add binding for Altera SOCFPGA FPGA Manager

2014-09-08 Thread Steffen Trumtrar 
Altera SOCFPGA have a FPGA Manager, that manages and monitors the FPGA portion
of the SoC.

Cc: devicet...@vger.kernel.org
Signed-off-by: Steffen Trumtrar 
---
 .../bindings/firmware/altr,socfpga-fpga-mgr.txt   | 19 +++
 1 file changed, 19 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/firmware/altr,socfpga-fpga-mgr.txt

diff --git 
a/Documentation/devicetree/bindings/firmware/altr,socfpga-fpga-mgr.txt 
b/Documentation/devicetree/bindings/firmware/altr,socfpga-fpga-mgr.txt
new file mode 100644
index ..70ec4abf25b4
--- /dev/null
+++ b/Documentation/devicetree/bindings/firmware/altr,socfpga-fpga-mgr.txt
@@ -0,0 +1,19 @@
+Altera SOCFPGA FPGA Manager
+---
+
+This binding defines the FPGA Manager on Altera SOCFPGAs. This is used to 
upload
+the firmware to the FPGA part of the SoC.
+
+Required properties:
+- compatible: shall be "altr,socfpga-fpga-mgr"
+- reg: Must contain 2 register ranges:
+   1. The control address space of the FPGA manager.
+   2. The configuration data address space where the firmware data is 
written to.
+
+Example:
+
+   fpgamgr@ff706000 {
+   compatible = "altr,socfpga-fpga-mgr";
+   reg = <0xff706000 0x1000>,
+ <0xffb9 0x1000>;
+   };
-- 
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[PATCH v4 4/5] Firmware: socfpga: Add SoCFPGA FPGA program support

2014-09-08 Thread Steffen Trumtrar 
From: Sascha Hauer 

Signed-off-by: Sascha Hauer 
---
 arch/arm/dts/socfpga.dtsi |   6 +
 arch/arm/mach-socfpga/Makefile|   1 +
 arch/arm/mach-socfpga/include/mach/socfpga-regs.h |   2 +
 drivers/firmware/Kconfig  |   3 +
 drivers/firmware/Makefile |   1 +
 drivers/firmware/socfpga.c| 440 ++
 6 files changed, 453 insertions(+)
 create mode 100644 drivers/firmware/socfpga.c

diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index 3368b459d030..afac867c991d 100644
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -465,6 +465,12 @@
status = "disabled";
};
 
+   fpgamgr@ff706000 {
+   compatible = "altr,socfpga-fpga-mgr";
+   reg = <0xff706000 0x1000>,
+ <0xffb9 0x1000>;
+   };
+
gpio0: gpio@ff708000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff708000 0x1000>;
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index d8bf0674306e..12585c547673 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -2,3 +2,4 @@ obj-y += generic.o nic301.o bootsource.o reset-manager.o
 pbl-y += init.o freeze-controller.o scan-manager.o system-manager.o
 pbl-y += clock-manager.o iocsr-config-cyclone5.o
 obj-$(CONFIG_ARCH_SOCFPGA_XLOAD) += xload.o
+obj-$(CONFIG_ARCH_SOCFPGA_FPGA) += fpga.o
diff --git a/arch/arm/mach-socfpga/include/mach/socfpga-regs.h 
b/arch/arm/mach-socfpga/include/mach/socfpga-regs.h
index 9d1e677cb736..b124ed675cfc 100644
--- a/arch/arm/mach-socfpga/include/mach/socfpga-regs.h
+++ b/arch/arm/mach-socfpga/include/mach/socfpga-regs.h
@@ -2,10 +2,12 @@
 #define __MACH_SOCFPGA_REGS_H
 
 #define CYCLONE5_SDMMC_ADDRESS 0xff704000
+#define CYCLONE5_FPGAMGRREGS_ADDRESS   0xff706000
 #define CYCLONE5_GPIO0_BASE0xff708000
 #define CYCLONE5_GPIO1_BASE0xff709000
 #define CYCLONE5_GPIO2_BASE0xff70A000
 #define CYCLONE5_L3REGS_ADDRESS0xff80
+#define CYCLONE5_FPGAMGRDATA_ADDRESS   0xffb9
 #define CYCLONE5_UART0_ADDRESS 0xffc02000
 #define CYCLONE5_UART1_ADDRESS 0xffc03000
 #define CYCLONE5_SDR_ADDRESS   0xffc2
diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig
index 28a173b63f2a..58660632519e 100644
--- a/drivers/firmware/Kconfig
+++ b/drivers/firmware/Kconfig
@@ -8,4 +8,7 @@ config FIRMWARE_ALTERA_SERIAL
  Programming an Altera FPGA via a few GPIOs for the control lines and
  MOSI, MISO and clock from an SPI interface for the data lines
 
+config FIRMWARE_ALTERA_SOCFPGA
+   bool "Altera SoCFPGA fpga loader"
+
 endmenu
diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
index ec6a5a17083d..c3a3c3400485 100644
--- a/drivers/firmware/Makefile
+++ b/drivers/firmware/Makefile
@@ -1 +1,2 @@
 obj-$(CONFIG_FIRMWARE_ALTERA_SERIAL) += altera_serial.o
+obj-$(CONFIG_FIRMWARE_ALTERA_SOCFPGA) += socfpga.o
diff --git a/drivers/firmware/socfpga.c b/drivers/firmware/socfpga.c
new file mode 100644
index ..a5dc6072aab4
--- /dev/null
+++ b/drivers/firmware/socfpga.c
@@ -0,0 +1,440 @@
+/*
+ *
+ * Copyright (C) 2012 Altera Corporation 
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *  - Neither the name of the Altera Corporation nor the
+ *names of its contributors may be used to endorse or promote products
+ *derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+#include 
+#in

[PATCH v4 1/5] Add a Firmware programming framework

2014-09-08 Thread Steffen Trumtrar 
From: Juergen Beisert 

This framework handles a list of registered Firmware programming handlers
to unify a firmware programming interface by hiding the details how
to program a specific Firmware in its handler. This is created with FPGAs
in mind but should be usable for other devices aswell.
A user has two possibilities to load a firmware. A device file is create
under /dev/ which can be used to copy a firmware to. Additionally a
firmwareload command is introduced which can list the registered firmware
handlers and also to upload a firmware.

Signed-off-by: Juergen Beisert 
Signed-off-by: Sascha Hauer 
Signed-off-by: Steffen Trumtrar 
---

Notes:
Changes since v3:
- change list_handlers formatting

 commands/Kconfig|   9 +++
 commands/Makefile   |   1 +
 commands/firmwareload.c |  66 +++
 common/Kconfig  |   3 +
 common/Makefile |   1 +
 common/firmware.c   | 211 
 include/firmware.h  |  42 ++
 7 files changed, 333 insertions(+)
 create mode 100644 commands/firmwareload.c
 create mode 100644 common/firmware.c
 create mode 100644 include/firmware.h

diff --git a/commands/Kconfig b/commands/Kconfig
index 3a49bafd27a7..0b1939ef5718 100644
--- a/commands/Kconfig
+++ b/commands/Kconfig
@@ -1905,6 +1905,15 @@ config CMD_BAREBOX_UPDATE
  -yautom. use 'yes' when asking confirmations
  -f LEVEL  set force level
 
+config CMD_FIRMWARELOAD
+   bool
+   select FIRMWARE
+   prompt "firmwareload"
+   help
+ Provides the "firmwareload" command which deals with devices which 
need
+ firmware to work. It is also used to upload firmware to FPGA devices.
+
+
 config CMD_LINUX_EXEC
bool "linux exec"
depends on LINUX
diff --git a/commands/Makefile b/commands/Makefile
index 52b6137c01ab..d6a6f822a8da 100644
--- a/commands/Makefile
+++ b/commands/Makefile
@@ -103,3 +103,4 @@ obj-$(CONFIG_CMD_LSPCI) += lspci.o
 obj-$(CONFIG_CMD_IMD)  += imd.o
 obj-$(CONFIG_CMD_HWCLOCK)  += hwclock.o
 obj-$(CONFIG_CMD_USBGADGET)+= usbgadget.o
+obj-$(CONFIG_CMD_FIRMWARELOAD) += firmwareload.o
diff --git a/commands/firmwareload.c b/commands/firmwareload.c
new file mode 100644
index ..a2596951a795
--- /dev/null
+++ b/commands/firmwareload.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2013 Juergen Beisert , Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+static int do_firmwareload(int argc, char *argv[])
+{
+   int ret, opt;
+   const char *name = NULL, *firmware;
+   struct firmware_mgr *mgr;
+
+   while ((opt = getopt(argc, argv, "t:l")) > 0) {
+   switch (opt) {
+   case 't':
+   name = optarg;
+   break;
+   case 'l':
+   firmwaremgr_list_handlers();
+   return 0;
+   default:
+   return COMMAND_ERROR_USAGE;
+   }
+   }
+
+   if (!(argc - optind))
+   return COMMAND_ERROR_USAGE;
+
+   firmware = argv[optind];
+
+   mgr = firmwaremgr_find(name);
+
+   if (!mgr) {
+   printf("No such programming handler found: %s\n",
+   name ? name : "default");
+   return 1;
+   }
+
+   ret = firmwaremgr_load_file(mgr, firmware);
+
+   return ret;
+}
+
+BAREBOX_CMD_HELP_START(firmwareload)
+BAREBOX_CMD_HELP_TEXT("Options:")
+BAREBOX_CMD_HELP_OPT("-t ", "define the firmware handler by name\n")
+BAREBOX_CMD_HELP_OPT("-l\t", "list devices capable of firmware loading\n")
+BAREBOX_CMD_HELP_END
+
+BAREBOX_CMD_START(firmwareload)
+   .cmd = do_firmwareload,
+   BAREBOX_CMD_DESC("Program a firmware file into a device")
+   BAREBOX_CMD_HELP(cmd_firmwareload_help)
+BAREBOX_CMD_END
diff --git a/common/Kconfig b/common/Kconfig
index 9cc96b776deb..8c8f840c23b9 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -328,6 +328,9 @@ config CBSIZE
prompt "Buffer size for input from the Console"
default 1024
 
+config FIRMWARE
+   bool
+
 choice
prompt "Select your shell"
 
diff --git a/common/Makefile b/common/Makefile
index 51b7d4ea85ad..282ddbca256d 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -49,6 +49,7 @@ obj-$(CONFIG_EFI_DEVICEPATH)  += efi-devicepath.o
 lwl-$(CONFIG_IMD)  += imd-barebox.o
 obj-$(CONFIG_IMD)  += imd.o
 obj-$(CONFIG_FILE_

[PATCH v4 2/5] Firmware: provide a handler to program Altera FPGAs

2014-09-08 Thread Steffen Trumtrar 
From: Juergen Beisert 

This handler uses a regular SPI master and a few GPIOs to program an
Altera FPGA in serial mode.

Signed-off-by: Juergen Beisert 
Signed-off-by: Sascha Hauer 
Signed-off-by: Steffen Trumtrar 
---

Notes:
Changes since v3:
- fix some typos
- use USECOND instead of 1000
- replace printf with dev_dbg

 drivers/Kconfig  |   1 +
 drivers/Makefile |   1 +
 drivers/firmware/Kconfig |  11 ++
 drivers/firmware/Makefile|   1 +
 drivers/firmware/altera_serial.c | 315 +++
 5 files changed, 329 insertions(+)
 create mode 100644 drivers/firmware/Kconfig
 create mode 100644 drivers/firmware/Makefile
 create mode 100644 drivers/firmware/altera_serial.c

diff --git a/drivers/Kconfig b/drivers/Kconfig
index d38032c0e606..e126f62c8f93 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -29,5 +29,6 @@ source "drivers/regulator/Kconfig"
 source "drivers/reset/Kconfig"
 source "drivers/pci/Kconfig"
 source "drivers/rtc/Kconfig"
+source "drivers/firmware/Kconfig"
 
 endmenu
diff --git a/drivers/Makefile b/drivers/Makefile
index 4591f9a4086f..cf42190b7bef 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -28,3 +28,4 @@ obj-$(CONFIG_REGULATOR) += regulator/
 obj-$(CONFIG_RESET_CONTROLLER) += reset/
 obj-$(CONFIG_PCI) += pci/
 obj-y += rtc/
+obj-$(CONFIG_FIRMWARE) += firmware/
diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig
new file mode 100644
index ..28a173b63f2a
--- /dev/null
+++ b/drivers/firmware/Kconfig
@@ -0,0 +1,11 @@
+menu "Firmware Drivers"
+
+config FIRMWARE_ALTERA_SERIAL
+   bool "Altera SPI programming"
+   depends on OFDEVICE
+   select FIRMWARE
+   help
+ Programming an Altera FPGA via a few GPIOs for the control lines and
+ MOSI, MISO and clock from an SPI interface for the data lines
+
+endmenu
diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
new file mode 100644
index ..ec6a5a17083d
--- /dev/null
+++ b/drivers/firmware/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_FIRMWARE_ALTERA_SERIAL) += altera_serial.o
diff --git a/drivers/firmware/altera_serial.c b/drivers/firmware/altera_serial.c
new file mode 100644
index ..23ba3b00a478
--- /dev/null
+++ b/drivers/firmware/altera_serial.c
@@ -0,0 +1,315 @@
+/*
+ * Copyright (c) 2013 Juergen Beisert , Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+/*
+ * Physical requirements:
+ * - three free GPIOs for the signals nCONFIG, CONFIGURE_DONE, nSTATUS
+ * - 32 bit per word, LSB first capable SPI master (MOSI + clock)
+ *
+ * Example how to configure this driver via device tree
+ *
+ * fpga@0 {
+ * compatible = "altr,fpga-passive-serial";
+ * nstat-gpio = <&gpio4 18 0>;
+ * confd-gpio = <&gpio4 19 0>;
+ * nconfig-gpio = <&gpio4 20 0>;
+ * spi-max-frequency = <1000>;
+ * reg = <0>;
+ * };
+ */
+
+struct fpga_spi {
+   struct firmware_handler fh;
+   int nstat_gpio; /* input GPIO to read the status line */
+   int confd_gpio; /* input GPIO to read the config done line */
+   int nconfig_gpio; /* output GPIO to start the FPGA's config */
+   struct device_d *dev;
+   struct spi_device *spi;
+   bool padding_done;
+};
+
+static int altera_spi_open(struct firmware_handler *fh)
+{
+   struct fpga_spi *this = container_of(fh, struct fpga_spi, fh);
+   struct device_d *dev = this->dev;
+   int ret;
+
+   dev_dbg(dev, "Initiating programming\n");
+
+   /* initiate an FPGA programming */
+   gpio_set_value(this->nconfig_gpio, 0);
+
+   /*
+* after about 2 µs the FPGA must acknowledge with
+* STATUS and CONFIG DONE lines at low level
+*/
+   ret = wait_on_timeout(2 * USECOND,
+   (gpio_get_value(this->nstat_gpio) == 0) &&
+   (gpio_get_value(this->confd_gpio) == 0));
+
+   if (ret != 0) {
+   dev_err(dev, "FPGA does not acknowledge the programming 
initiation\n");
+   if (gpio_get_value(this->nstat_gpio))
+   dev_err(dev, "STATUS is still high!\n");
+   if (gpio_get_value(this->confd_gpio))
+   dev_err(dev, "CONFIG DONE is still high!\n");
+   return ret;
+   }
+
+   /* arm the FPGA to await i

Re: [PATCH v2 7/7] Documentation: add OpenRISC or1ksim emulator section

2014-09-08 Thread Franck Jullien 
Hi Antony,

2014-09-08 8:53 GMT+02:00 Antony Pavlov :
> Signed-off-by: Antony Pavlov 
> Cc: Franck Jullien 
> ---
>  Documentation/boards/openrisc.rst | 51 
> +++
>  1 file changed, 51 insertions(+)
>
> diff --git a/Documentation/boards/openrisc.rst 
> b/Documentation/boards/openrisc.rst
> new file mode 100644
> index 000..0b36712
> --- /dev/null
> +++ b/Documentation/boards/openrisc.rst
> @@ -0,0 +1,51 @@
> +OpenRISC
> +
> +
> +or1ksim
> +---
> +
> +Compile or1ksim emulator::
> +
> + $ cd ~/
> + $ git clone https://github.com/fjullien/or1ksim

You should use this repo: https://github.com/openrisc/or1ksim

> + $ cd or1ksim
> + $ ./configure
> + $ make
> +
> +Create minimal or1ksim.cfg file::
> +
> + section cpu
> +   ver = 0x12
> +   cfgr = 0x20
> +   rev = 0x0001
> + end
> +
> + section memory
> +   name = "RAM"
> +   type = unknown
> +   baseaddr = 0x
> +   size = 0x0200
> +   delayr = 1
> +   delayw = 2
> + end
> +
> + section uart
> +   enabled = 1
> +   baseaddr = 0x9000
> +   irq = 2
> +   16550 = 1
> +   /* channel = "tcp:10084" */
> +   channel = "xterm:"
> + end
> +
> + section ethernet
> +   enabled = 1
> +   baseaddr = 0x9200
> +   irq = 4
> +   rtx_type = "tap"
> +   tap_dev = "tap0"
> + end
> +
> +Run or1ksim::
> +
> + $ ~/or1ksim/sim -f or1ksim.cfg barebox
> --
> 2.1.0
>

Franck.

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