[PATCH] common: fix mbr filetype detection

2014-11-03 Thread Zahari Doychev 
Sometimes mbr is erroneously recocognised as FAT partion. Due to this the mbr
partition parser is not being called and the partitions on the media are not
detected. This patch should  fix the problem. The checking is done as in the
linux kernel.

I have seen the problem using usb sticks. Although partitioning and formatting
them under linux. The file system type field in the mbr remains there which
causes the wrong detections as FAT32 type and not as mbr.

Signed-off-by: Zahari Doychev 
---
 common/filetype.c   | 48 
 common/partitions.c |  2 ++
 include/filetype.h  |  1 +
 3 files changed, 51 insertions(+)

diff --git a/common/filetype.c b/common/filetype.c
index c8f3582..810d9a5 100644
--- a/common/filetype.c
+++ b/common/filetype.c
@@ -24,6 +24,7 @@
 #include 
 #include 
 #include 
+#include 
 
 struct filetype_str {
const char *name;   /* human readable filetype */
@@ -87,6 +88,10 @@ const char *file_type_to_short_string(enum filetype f)
 #define MBR_PART_start_sect8
 #define MBR_OSTYPE_EFI_GPT 0xee
 
+#define FAT_BS_reserved14
+#define FAT_BS_fats16
+#define FAT_BS_media   21
+
 static inline int pmbr_part_valid(const uint8_t *buf)
 {
if (buf[MBR_PART_sys_ind] == MBR_OSTYPE_EFI_GPT &&
@@ -126,6 +131,49 @@ static int is_gpt_valid(const uint8_t *buf)
return 0;
 }
 
+static inline int fat_valid_media(u8 media)
+{
+   return (0xf8 <= media || media == 0xf0);
+}
+
+static int is_fat_with_no_mbr(const unsigned char  *sect)
+{
+   if (!get_unaligned_le16(§[FAT_BS_reserved]))
+   return 0;
+
+   if (!sect[FAT_BS_fats])
+   return 0;
+
+   if (!fat_valid_media(sect[FAT_BS_media]))
+   return 0;
+
+   return 1;
+}
+
+int is_fat_boot_sector(const void *sect)
+{
+   struct partition_entry *p;
+   int slot;
+
+   p = (struct partition_entry *) (sect + MBR_Table);
+   /* max 4 partitions */
+   for (slot = 1; slot <= 4; slot++, p++) {
+   if (p->boot_indicator && p->boot_indicator != 0x80) {
+   /*
+* Even without a valid boot inidicator value
+* its still possible this is valid FAT filesystem
+* without a partition table.
+*/
+   if (slot == 1 && is_fat_with_no_mbr(sect))
+   return 1;
+else
+   return -EINVAL;
+   }
+   }
+
+   return 0;
+}
+
 enum filetype is_fat_or_mbr(const unsigned char *sector, unsigned long 
*bootsec)
 {
/*
diff --git a/common/partitions.c b/common/partitions.c
index 694c6f6..37d9cb7 100644
--- a/common/partitions.c
+++ b/common/partitions.c
@@ -107,6 +107,8 @@ static struct partition_parser 
*partition_parser_get_by_filetype(uint8_t *buf)
 * useful for compatibility
 */
type = file_detect_partition_table(buf, SECTOR_SIZE);
+   if (type == filetype_fat && !is_fat_boot_sector(buf))
+   type = filetype_mbr;
 
list_for_each_entry(parser, &partition_parser_list, list) {
if (parser->type == type)
diff --git a/include/filetype.h b/include/filetype.h
index eedf4b4..2c3c38d 100644
--- a/include/filetype.h
+++ b/include/filetype.h
@@ -44,6 +44,7 @@ enum filetype file_detect_partition_table(const void *_buf, 
size_t bufsize);
 enum filetype file_detect_type(const void *_buf, size_t bufsize);
 enum filetype file_name_detect_type(const char *filename);
 enum filetype is_fat_or_mbr(const unsigned char *sector, unsigned long 
*bootsec);
+int is_fat_boot_sector(const void *_buf);
 
 #define ARM_HEAD_SIZE  0x30
 #define ARM_HEAD_MAGICWORD_OFFSET  0x20
-- 
2.0.4


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[PATCH] fix mbr detection

2014-11-03 Thread Zahari Doychev 
I have a strange problem using usb sticks in barebox. After formatting some
previously FAT sticks they still have file system type set to FAT32 in the mbr.
In this way there are detected as FAT fs partitions instead of MBRs and the usb
media partitons can not be parsed.

This patch should resolve this problem. Please review it and check if it is
fine and not causing any side effects.

Regards,
Zahari

Zahari Doychev (1):
  common: fix mbr filetype detection

 common/filetype.c   | 48 
 common/partitions.c |  2 ++
 include/filetype.h  |  1 +
 3 files changed, 51 insertions(+)

-- 
2.0.4


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[PATCH 04/12] tegra: beaver: switch to upstream Tegra30 dtsi

2014-11-03 Thread Lucas Stach 
It's the same as our version, so no need to carry it
around any longer.

Signed-off-by: Lucas Stach 
---
 arch/arm/dts/tegra30-beaver.dts |   2 +-
 arch/arm/dts/tegra30.dtsi   | 892 
 2 files changed, 1 insertion(+), 893 deletions(-)
 delete mode 100644 arch/arm/dts/tegra30.dtsi

diff --git a/arch/arm/dts/tegra30-beaver.dts b/arch/arm/dts/tegra30-beaver.dts
index 94955f9..d2809bb 100644
--- a/arch/arm/dts/tegra30-beaver.dts
+++ b/arch/arm/dts/tegra30-beaver.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-#include "tegra30.dtsi"
+#include 
 
 / {
model = "NVIDIA Tegra30 Beaver evaluation board";
diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi
deleted file mode 100644
index 19a84e9..000
--- a/arch/arm/dts/tegra30.dtsi
+++ /dev/null
@@ -1,892 +0,0 @@
-#include 
-#include 
-#include 
-#include 
-
-#include "skeleton.dtsi"
-
-/ {
-   compatible = "nvidia,tegra30";
-   interrupt-parent = <&intc>;
-
-   aliases {
-   serial0 = &uarta;
-   serial1 = &uartb;
-   serial2 = &uartc;
-   serial3 = &uartd;
-   serial4 = &uarte;
-   };
-
-   pcie-controller@3000 {
-   compatible = "nvidia,tegra30-pcie";
-   device_type = "pci";
-   reg = <0x3000 0x0800   /* PADS registers */
-  0x3800 0x0200   /* AFI registers */
-  0x1000 0x1000>; /* configuration space */
-   reg-names = "pads", "afi", "cs";
-   interrupts = ; /* MSI interrupt 
*/
-   interrupt-names = "intr", "msi";
-
-   bus-range = <0x00 0xff>;
-   #address-cells = <3>;
-   #size-cells = <2>;
-
-   ranges = <0x8200 0 0x 0x 0 0x1000   /* 
port 0 configuration space */
- 0x8200 0 0x1000 0x1000 0 0x1000   /* 
port 1 configuration space */
- 0x8200 0 0x4000 0x4000 0 0x1000   /* 
port 2 configuration space */
- 0x8100 0 0  0x0200 0 0x0001   /* 
downstream I/O */
- 0x8200 0 0x2000 0x2000 0 0x0800   /* 
non-prefetchable memory */
- 0xc200 0 0x2800 0x2800 0 0x1800>; /* 
prefetchable memory */
-
-   clocks = <&tegra_car TEGRA30_CLK_PCIE>,
-<&tegra_car TEGRA30_CLK_AFI>,
-<&tegra_car TEGRA30_CLK_PLL_E>,
-<&tegra_car TEGRA30_CLK_CML0>;
-   clock-names = "pex", "afi", "pll_e", "cml";
-   resets = <&tegra_car 70>,
-<&tegra_car 72>,
-<&tegra_car 74>;
-   reset-names = "pex", "afi", "pcie_x";
-   status = "disabled";
-
-   pci@1,0 {
-   device_type = "pci";
-   assigned-addresses = <0x82000800 0 0x 0 0x1000>;
-   reg = <0x000800 0 0 0 0>;
-   status = "disabled";
-
-   #address-cells = <3>;
-   #size-cells = <2>;
-   ranges;
-
-   nvidia,num-lanes = <2>;
-   };
-
-   pci@2,0 {
-   device_type = "pci";
-   assigned-addresses = <0x82001000 0 0x1000 0 0x1000>;
-   reg = <0x001000 0 0 0 0>;
-   status = "disabled";
-
-   #address-cells = <3>;
-   #size-cells = <2>;
-   ranges;
-
-   nvidia,num-lanes = <2>;
-   };
-
-   pci@3,0 {
-   device_type = "pci";
-   assigned-addresses = <0x82001800 0 0x4000 0 0x1000>;
-   reg = <0x001800 0 0 0 0>;
-   status = "disabled";
-
-   #address-cells = <3>;
-   #size-cells = <2>;
-   ranges;
-
-   nvidia,num-lanes = <2>;
-   };
-   };
-
-   host1x@5000 {
-   compatible = "nvidia,tegra30-host1x", "simple-bus";
-   reg = <0x5000 0x00024000>;
-   interrupts = , /* syncpt */
-; /* general */
-   clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
-   resets = <&tegra_car 28>;
-   reset-names = "host1x";
-
-   #address-cells = <1>;
-   #size-cells = <1>;
-
-   ranges = <0x5400 0x5400 0x0400>;
-
-   mpe@5404 {
-   compatible = "nvidia,tegra30-mpe";
-   reg = <0x5404 0x0004>;
-   interrupts = ;
-   clocks = <&tegra_car TEGRA30

[PATCH 11/12] tegra: remove custom UART setup

2014-11-03 Thread Lucas Stach 
The config option doesn't make any sense anymore
when building a multiimage barebox. With a proper
DT built into the image we don't need the ODMdata
mechanism to find the debug UART anymore.

Signed-off-by: Lucas Stach 
---
 arch/arm/mach-tegra/Kconfig | 33 -
 arch/arm/mach-tegra/include/mach/lowlevel.h | 45 -
 arch/arm/mach-tegra/tegra20.c   | 41 --
 3 files changed, 119 deletions(-)

diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 1bdea8e..160732f 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -7,39 +7,6 @@ config ARCH_TEXT_BASE
 config BOARDINFO
default ""
 
-choice
-   prompt "Tegra debug UART"
-   help
- This is the first serial console that gets activated by barebox.
- Normally each board vendor should program a valid debug UART into
- the ODMdata section of the boot configuration table, so it's a
- reasonably good bet to use that.
- If you know your ODMdata is broken, or you don't wish to activate
- any serial console at all you can override the default here.
-
-config TEGRA_UART_ODMDATA
-   bool "ODMdata defined UART"
-
-config TEGRA_UART_A
-   bool "UART A"
-
-config TEGRA_UART_B
-   bool "UART B"
-
-config TEGRA_UART_C
-   bool "UART C"
-
-config TEGRA_UART_D
-   bool "UART D"
-
-config TEGRA_UART_E
-   bool "UART E"
-
-config TEGRA_UART_NONE
-   bool "None"
-
-endchoice
-
 # -
 
 config ARCH_TEGRA_2x_SOC
diff --git a/arch/arm/mach-tegra/include/mach/lowlevel.h 
b/arch/arm/mach-tegra/include/mach/lowlevel.h
index c65be0b..3e7e41b 100644
--- a/arch/arm/mach-tegra/include/mach/lowlevel.h
+++ b/arch/arm/mach-tegra/include/mach/lowlevel.h
@@ -176,37 +176,6 @@ uint32_t tegra30_get_ramsize(void)
}
 }
 
-static long uart_id_to_base[] = {
-   TEGRA_UARTA_BASE,
-   TEGRA_UARTB_BASE,
-   TEGRA_UARTC_BASE,
-   TEGRA_UARTD_BASE,
-   TEGRA_UARTE_BASE,
-};
-
-static __always_inline
-long tegra20_get_debuguart_base(void)
-{
-   u32 odmdata;
-   int id;
-
-   odmdata = tegra_get_odmdata();
-
-   /*
-* Get type, we accept both "2" and "3", as they both demark a UART,
-* depending on the board type.
-*/
-   if (!(((odmdata & T20_ODMDATA_UARTTYPE_MASK) >>
- T20_ODMDATA_UARTTYPE_SHIFT) & 0x2))
-   return 0;
-
-   id = (odmdata & T20_ODMDATA_UARTID_MASK) >> T20_ODMDATA_UARTID_SHIFT;
-   if (id > ARRAY_SIZE(uart_id_to_base))
-   return 0;
-
-   return uart_id_to_base[id];
-}
-
 #define CRC_OSC_CTRL   0x050
 #define CRC_OSC_CTRL_OSC_FREQ_SHIFT30
 #define CRC_OSC_CTRL_OSC_FREQ_MASK (0x3 << CRC_OSC_CTRL_OSC_FREQ_SHIFT)
@@ -231,20 +200,6 @@ int tegra_get_osc_clock(void)
}
 }
 
-static __always_inline
-int tegra_get_pllp_rate(void)
-{
-   switch (tegra_get_chiptype()) {
-   case TEGRA20:
-   return 21600;
-   case TEGRA30:
-   case TEGRA124:
-   return 40800;
-   default:
-   return 0;
-   }
-}
-
 #define TIMER_CNTR_1US 0x00
 #define TIMER_USEC_CFG 0x04
 
diff --git a/arch/arm/mach-tegra/tegra20.c b/arch/arm/mach-tegra/tegra20.c
index dcc55ae..8d1cd5b 100644
--- a/arch/arm/mach-tegra/tegra20.c
+++ b/arch/arm/mach-tegra/tegra20.c
@@ -22,47 +22,6 @@
 #include 
 #include 
 
-static struct NS16550_plat debug_uart = {
-   .shift = 2,
-};
-
-static int tegra_add_debug_console(void)
-{
-   unsigned long base = 0;
-
-   if (!of_machine_is_compatible("nvidia,tegra20") &&
-   !of_machine_is_compatible("nvidia,tegra30") &&
-   !of_machine_is_compatible("nvidia,tegra124"))
-   return 0;
-
-   /* figure out which UART to use */
-   if (IS_ENABLED(CONFIG_TEGRA_UART_NONE))
-   return 0;
-   if (IS_ENABLED(CONFIG_TEGRA_UART_ODMDATA))
-   base = tegra20_get_debuguart_base();
-   if (IS_ENABLED(CONFIG_TEGRA_UART_A))
-   base = TEGRA_UARTA_BASE;
-   if (IS_ENABLED(CONFIG_TEGRA_UART_B))
-   base = TEGRA_UARTB_BASE;
-   if (IS_ENABLED(CONFIG_TEGRA_UART_C))
-   base = TEGRA_UARTC_BASE;
-   if (IS_ENABLED(CONFIG_TEGRA_UART_D))
-   base = TEGRA_UARTD_BASE;
-   if (IS_ENABLED(CONFIG_TEGRA_UART_E))
-   base = TEGRA_UARTE_BASE;
-
-   if (!base)
-   return -ENODEV;
-
-   debug_uart.clock = tegra_get_pllp_rate();
-
-   add_ns16550_device(DEVICE_ID_DYNAMIC, base, 8 << debug_uart.shift,
-  IORESOURCE_MEM | IORESOURCE_MEM_8BIT, &debug_uart);
-
-   return 0;
-}
-console_initcall(tegra_add_debug_console);
-
 static int tegra20_mem_init(void)
 {
if (!of_machine_is_compatible("nvidia,tegra20"))
-- 
1.9.3


__

[PATCH 05/12] tegra: beaver: add stdout-path

2014-11-03 Thread Lucas Stach 
Signed-off-by: Lucas Stach 
---
 arch/arm/dts/tegra30-beaver.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/dts/tegra30-beaver.dts b/arch/arm/dts/tegra30-beaver.dts
index d2809bb..5879353 100644
--- a/arch/arm/dts/tegra30-beaver.dts
+++ b/arch/arm/dts/tegra30-beaver.dts
@@ -12,6 +12,8 @@
};
 
chosen {
+   stdout-path = &uarta;
+
environment@0 {
compatible = "barebox,environment";
device-path = &emmc, "partname:boot1";
-- 
1.9.3


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[PATCH 10/12] serial: ns16550: add Tegra support

2014-11-03 Thread Lucas Stach 
Signed-off-by: Lucas Stach 
---
 drivers/serial/serial_ns16550.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c
index 07dedf7..8f2e93f 100644
--- a/drivers/serial/serial_ns16550.c
+++ b/drivers/serial/serial_ns16550.c
@@ -311,6 +311,11 @@ static __maybe_unused struct ns16550_drvdata jz_drvdata = {
.init_port = ns16550_jz_init_port,
 };
 
+static __maybe_unused struct ns16550_drvdata tegra_drvdata = {
+   .init_port = ns16550_serial_init_port,
+   .linux_console_name = "ttyS",
+};
+
 static int ns16550_init_iomem(struct device_d *dev, struct ns16550_priv *priv)
 {
struct resource *res;
@@ -477,6 +482,12 @@ static struct of_device_id ns16550_serial_dt_ids[] = {
.data = (unsigned long)&omap_drvdata,
},
 #endif
+#if IS_ENABLED(CONFIG_ARCH_TEGRA)
+   {
+   .compatible = "nvidia,tegra20-uart",
+   .data = (unsigned long)&tegra_drvdata,
+   },
+#endif
 #if IS_ENABLED(CONFIG_MACH_MIPS_XBURST)
{
.compatible = "ingenic,jz4740-uart",
-- 
1.9.3


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[PATCH 08/12] tegra: jetson-tk1: add stdout-path

2014-11-03 Thread Lucas Stach 
Signed-off-by: Lucas Stach 
---
 arch/arm/dts/tegra124-jetson-tk1.dts | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/dts/tegra124-jetson-tk1.dts 
b/arch/arm/dts/tegra124-jetson-tk1.dts
index d2933bd..26f405c 100644
--- a/arch/arm/dts/tegra124-jetson-tk1.dts
+++ b/arch/arm/dts/tegra124-jetson-tk1.dts
@@ -1,7 +1,10 @@
 #include 
+#include "tegra124.dtsi"
 
 / {
chosen {
+   stdout-path = "/serial@0,70006300/";
+
environment@0 {
compatible = "barebox,environment";
device-path = &emmc, "partname:boot1";
-- 
1.9.3


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[PATCH 07/12] tegra: tegra124: add serial alias nodes

2014-11-03 Thread Lucas Stach 
They are missing in the upstream DT. Add them
locally for now.

Signed-off-by: Lucas Stach 
---
 arch/arm/dts/tegra124.dtsi | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/tegra124.dtsi b/arch/arm/dts/tegra124.dtsi
index 7d0fafa..c795811 100644
--- a/arch/arm/dts/tegra124.dtsi
+++ b/arch/arm/dts/tegra124.dtsi
@@ -1 +1,8 @@
-#include 
+/ {
+   aliases {
+   serial0 = "/serial@0,70006000/";
+   serial1 = "/serial@0,70006040/";
+   serial2 = "/serial@0,70006200/";
+   serial3 = "/serial@0,70006300/";
+   };
+};
-- 
1.9.3


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[PATCH 09/12] serial: ns16550: enable clock if available

2014-11-03 Thread Lucas Stach 
Signed-off-by: Lucas Stach 
---
 drivers/serial/serial_ns16550.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c
index 53d48a0..07dedf7 100644
--- a/drivers/serial/serial_ns16550.c
+++ b/drivers/serial/serial_ns16550.c
@@ -418,6 +418,7 @@ static int ns16550_probe(struct device_d *dev)
ret = PTR_ERR(priv->clk);
goto err;
}
+   clk_enable(priv->clk);
priv->plat.clock = clk_get_rate(priv->clk);
}
 
-- 
1.9.3


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[PATCH 12/12] clk: tegra: don't enable UART clocks by default

2014-11-03 Thread Lucas Stach 
Now that we are registering a proper driver for the
UARTs we no longer need to enable the clocks unconditionally.

Signed-off-by: Lucas Stach 
---
 drivers/clk/tegra/clk-tegra124.c |  8 
 drivers/clk/tegra/clk-tegra20.c  | 10 +-
 drivers/clk/tegra/clk-tegra30.c  | 10 +-
 3 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index d597a23..7a2f7c0 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -322,10 +322,10 @@ static struct tegra_clk_init_table init_table[] = {
{TEGRA124_CLK_PLL_P_OUT3,   TEGRA124_CLK_CLK_MAX,   10200,  
1},
{TEGRA124_CLK_PLL_P_OUT4,   TEGRA124_CLK_CLK_MAX,   20400,  
1},
{TEGRA124_CLK_MSELECT,  TEGRA124_CLK_PLL_P, 10200,  
1},
-   {TEGRA124_CLK_UARTA,TEGRA124_CLK_PLL_P, 0,  
1},
-   {TEGRA124_CLK_UARTB,TEGRA124_CLK_PLL_P, 0,  
1},
-   {TEGRA124_CLK_UARTC,TEGRA124_CLK_PLL_P, 0,  
1},
-   {TEGRA124_CLK_UARTD,TEGRA124_CLK_PLL_P, 0,  
1},
+   {TEGRA124_CLK_UARTA,TEGRA124_CLK_PLL_P, 0,  
0},
+   {TEGRA124_CLK_UARTB,TEGRA124_CLK_PLL_P, 0,  
0},
+   {TEGRA124_CLK_UARTC,TEGRA124_CLK_PLL_P, 0,  
0},
+   {TEGRA124_CLK_UARTD,TEGRA124_CLK_PLL_P, 0,  
0},
{TEGRA124_CLK_SDMMC1,   TEGRA124_CLK_PLL_P, 4800,   
0},
{TEGRA124_CLK_SDMMC2,   TEGRA124_CLK_PLL_P, 4800,   
0},
{TEGRA124_CLK_SDMMC3,   TEGRA124_CLK_PLL_P, 4800,   
0},
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 5b4365d..2ff42d8 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -324,11 +324,11 @@ static struct tegra_clk_init_table init_table[] = {
{TEGRA20_CLK_PLL_P_OUT4,TEGRA20_CLK_CLK_MAX,2400,   
1},
{TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX,6,  
1},
{TEGRA20_CLK_PLL_C_OUT1,TEGRA20_CLK_CLK_MAX,12000,  
1},
-   {TEGRA20_CLK_UARTA, TEGRA20_CLK_PLL_P,  0,  
1},
-   {TEGRA20_CLK_UARTB, TEGRA20_CLK_PLL_P,  0,  
1},
-   {TEGRA20_CLK_UARTC, TEGRA20_CLK_PLL_P,  0,  
1},
-   {TEGRA20_CLK_UARTD, TEGRA20_CLK_PLL_P,  0,  
1},
-   {TEGRA20_CLK_UARTE, TEGRA20_CLK_PLL_P,  0,  
1},
+   {TEGRA20_CLK_UARTA, TEGRA20_CLK_PLL_P,  0,  
0},
+   {TEGRA20_CLK_UARTB, TEGRA20_CLK_PLL_P,  0,  
0},
+   {TEGRA20_CLK_UARTC, TEGRA20_CLK_PLL_P,  0,  
0},
+   {TEGRA20_CLK_UARTD, TEGRA20_CLK_PLL_P,  0,  
0},
+   {TEGRA20_CLK_UARTE, TEGRA20_CLK_PLL_P,  0,  
0},
{TEGRA20_CLK_SDMMC1,TEGRA20_CLK_PLL_P,  4800,   
0},
{TEGRA20_CLK_SDMMC2,TEGRA20_CLK_PLL_P,  4800,   
0},
{TEGRA20_CLK_SDMMC3,TEGRA20_CLK_PLL_P,  4800,   
0},
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 7210053..46fd6dd 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -352,11 +352,11 @@ static struct tegra_clk_init_table init_table[] = {
{TEGRA30_CLK_PLL_P_OUT3,TEGRA30_CLK_CLK_MAX,10200,  
1},
{TEGRA30_CLK_PLL_P_OUT4,TEGRA30_CLK_CLK_MAX,20400,  
1},
{TEGRA30_CLK_MSELECT,   TEGRA30_CLK_PLL_P,  10200,  
1},
-   {TEGRA30_CLK_UARTA, TEGRA30_CLK_PLL_P,  0,  
1},
-   {TEGRA30_CLK_UARTB, TEGRA30_CLK_PLL_P,  0,  
1},
-   {TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P,  0,  
1},
-   {TEGRA30_CLK_UARTD, TEGRA30_CLK_PLL_P,  0,  
1},
-   {TEGRA30_CLK_UARTE, TEGRA30_CLK_PLL_P,  0,  
1},
+   {TEGRA30_CLK_UARTA, TEGRA30_CLK_PLL_P,  0,  
0},
+   {TEGRA30_CLK_UARTB, TEGRA30_CLK_PLL_P,  0,  
0},
+   {TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P,  0,  
0},
+   {TEGRA30_CLK_UARTD, TEGRA30_CLK_PLL_P,  0,  
0},
+   {TEGRA30_CLK_UARTE, TEGRA30_CLK_PLL_P,  0,  
0},
{TEGRA30_CLK_SDMMC1,TEGRA30_CLK_PLL_P,  4800,   
0},
{TEGRA30_CLK_SDMMC2,TEGRA30_CLK_PLL_P,  4800,   
0},
{TEGRA30_CLK_SDMMC3,TEGRA

[PATCH 06/12] tegra: colibri-t20: add stdout-path

2014-11-03 Thread Lucas Stach 
Signed-off-by: Lucas Stach 
---
 arch/arm/dts/tegra20-colibri-iris.dts | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/dts/tegra20-colibri-iris.dts 
b/arch/arm/dts/tegra20-colibri-iris.dts
index adfa917..9c61581 100644
--- a/arch/arm/dts/tegra20-colibri-iris.dts
+++ b/arch/arm/dts/tegra20-colibri-iris.dts
@@ -6,6 +6,10 @@
model = "Toradex Colibri T20 on Iris";
compatible = "toradex,iris", "toradex,colibri_t20", "nvidia,tegra20";
 
+   chosen {
+   stdout-path = &uarta;
+   };
+
host1x@5000 {
hdmi@5428 {
status = "okay";
-- 
1.9.3


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[PATCH 01/12] tegra: beaver: set hostname in board init

2014-11-03 Thread Lucas Stach 
Signed-off-by: Lucas Stach 
---
 arch/arm/boards/nvidia-beaver/board.c | 15 +--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boards/nvidia-beaver/board.c 
b/arch/arm/boards/nvidia-beaver/board.c
index 20707d8..d270301 100644
--- a/arch/arm/boards/nvidia-beaver/board.c
+++ b/arch/arm/boards/nvidia-beaver/board.c
@@ -20,7 +20,7 @@
 #include 
 #include 
 
-static int nvidia_beaver_devices_init(void)
+static int nvidia_beaver_fs_init(void)
 {
struct i2c_client client;
u8 data;
@@ -44,4 +44,15 @@ static int nvidia_beaver_devices_init(void)
 
return 0;
 }
-fs_initcall(nvidia_beaver_devices_init);
+fs_initcall(nvidia_beaver_fs_init);
+
+static int nvidia_beaver_device_init(void)
+{
+   if (!of_machine_is_compatible("nvidia,beaver"))
+   return 0;
+
+   barebox_set_hostname("beaver");
+
+   return 0;
+}
+device_initcall(nvidia_beaver_device_init);
-- 
1.9.3


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[PATCH 02/12] tegra: jetson-tk1: set hostname in board init

2014-11-03 Thread Lucas Stach 
Signed-off-by: Lucas Stach 
---
 arch/arm/boards/nvidia-jetson-tk1/board.c | 15 +--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boards/nvidia-jetson-tk1/board.c 
b/arch/arm/boards/nvidia-jetson-tk1/board.c
index c20f56a..564e6a0 100644
--- a/arch/arm/boards/nvidia-jetson-tk1/board.c
+++ b/arch/arm/boards/nvidia-jetson-tk1/board.c
@@ -26,7 +26,7 @@
 #define AS3722_GPIO_SIGNAL_OUT 0x20
 #define AS3722_SD_CONTROL  0x4d
 
-static int nvidia_jetson_tk1_devices_init(void)
+static int nvidia_jetson_tk1_fs_init(void)
 {
struct i2c_client client;
u8 data;
@@ -47,4 +47,15 @@ static int nvidia_jetson_tk1_devices_init(void)
 
return 0;
 }
-fs_initcall(nvidia_jetson_tk1_devices_init);
+fs_initcall(nvidia_jetson_tk1_fs_init);
+
+static int nvidia_jetson_tk1_device_init(void)
+{
+   if (!of_machine_is_compatible("nvidia,jetson-tk1"))
+   return 0;
+
+   barebox_set_hostname("jetson-tk1");
+
+   return 0;
+}
+device_initcall(nvidia_jetson_tk1_device_init);
-- 
1.9.3


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[PATCH 03/12] tegra: colibri-t20: set hostname in board init

2014-11-03 Thread Lucas Stach 
Signed-off-by: Lucas Stach 
---
 arch/arm/boards/toradex-colibri-t20/Makefile |  1 +
 arch/arm/boards/toradex-colibri-t20/board.c  | 29 
 2 files changed, 30 insertions(+)
 create mode 100644 arch/arm/boards/toradex-colibri-t20/board.c

diff --git a/arch/arm/boards/toradex-colibri-t20/Makefile 
b/arch/arm/boards/toradex-colibri-t20/Makefile
index 1f76732..d0347f2 100644
--- a/arch/arm/boards/toradex-colibri-t20/Makefile
+++ b/arch/arm/boards/toradex-colibri-t20/Makefile
@@ -3,6 +3,7 @@ CFLAGS_pbl-entry.o := \
-fno-tree-switch-conversion -fno-jump-tables
 soc := tegra20
 lwl-y += entry.o
+obj-y += board.o
 extra-y += colibri-t20_256_hsmmc.bct colibri-t20_256_v11_nand.bct \
colibri-t20_256_v12_nand.bct colibri-t20_512_hsmmc.bct \
colibri-t20_512_v11_nand.bct colibri-t20_512_v12_nand.bct
\ No newline at end of file
diff --git a/arch/arm/boards/toradex-colibri-t20/board.c 
b/arch/arm/boards/toradex-colibri-t20/board.c
new file mode 100644
index 000..7061981
--- /dev/null
+++ b/arch/arm/boards/toradex-colibri-t20/board.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2014 Lucas Stach 
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ */
+
+#include 
+#include 
+
+static int toradex_colibri_t20_device_init(void)
+{
+   if (!of_machine_is_compatible("toradex,colibri_t20-512"))
+   return 0;
+
+   barebox_set_hostname("colibri-t20");
+
+   return 0;
+}
+device_initcall(toradex_colibri_t20_device_init);
-- 
1.9.3


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[PATCH] fixup! tegra: jetson-tk1: enable 1.05V_RUN

2014-11-03 Thread Lucas Stach 
---
 arch/arm/mach-tegra/Kconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 62e5006..160732f 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -37,6 +37,8 @@ config MACH_NVIDIA_BEAVER
 config MACH_NVIDIA_JETSON
bool "NVIDIA Jetson TK1"
select ARCH_TEGRA_124_SOC
+   select I2C
+   select I2C_TEGRA
 
 endmenu
 
-- 
1.9.3


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Re: [PATCHv2 2/3] ARM: am335x: Add register of boot devices

2014-11-03 Thread Sascha Hauer 
On Mon, Nov 03, 2014 at 01:31:53PM +0100, Teresa Gámez wrote:
> Add support for registering disabled boot devices from oftree.
> Creating a device tree with all bootable devices disabled, makes
> it possible to only enable and register the devices needed to
> load the next stage bootloader.
> 
> Signed-off-by: Teresa Gámez 

Applied all, thanks

Sascha

> ---
> v2:
> - updated of funcion name
> 
>  arch/arm/mach-omap/am33xx_generic.c  | 31 
> 
>  arch/arm/mach-omap/include/mach/am33xx-generic.h |  1 +
>  2 files changed, 32 insertions(+)
> 
> diff --git a/arch/arm/mach-omap/am33xx_generic.c 
> b/arch/arm/mach-omap/am33xx_generic.c
> index f293134..b561575 100644
> --- a/arch/arm/mach-omap/am33xx_generic.c
> +++ b/arch/arm/mach-omap/am33xx_generic.c
> @@ -428,3 +428,34 @@ void am335x_sdram_init(int ioctrl, const struct 
> am33xx_cmd_control *cmd_ctrl,
>  
>   am33xx_config_sdram(emif_regs);
>  }
> +
> +int am33xx_of_register_bootdevice(void)
> +{
> + struct device_d *dev;
> +
> + switch (bootsource_get()) {
> + case BOOTSOURCE_MMC:
> + if (bootsource_get_instance() == 0)
> + dev = 
> of_device_enable_and_register_by_name("mmc@4806");
> + else
> + dev = 
> of_device_enable_and_register_by_name("mmc@481d8000");
> + break;
> + case BOOTSOURCE_NAND:
> + dev = of_device_enable_and_register_by_name("gpmc@5000");
> + break;
> + case BOOTSOURCE_SPI:
> + dev = of_device_enable_and_register_by_name("spi@4803");
> + break;
> + default:
> + /* Use nand fallback */
> + dev = of_device_enable_and_register_by_name("gpmc@5000");
> + break;
> + }
> +
> + if (!dev) {
> + printf("Unable to register boot device\n");
> + return -ENODEV;
> + }
> +
> + return 0;
> +}
> diff --git a/arch/arm/mach-omap/include/mach/am33xx-generic.h 
> b/arch/arm/mach-omap/include/mach/am33xx-generic.h
> index 6c85d51..7312061 100644
> --- a/arch/arm/mach-omap/include/mach/am33xx-generic.h
> +++ b/arch/arm/mach-omap/include/mach/am33xx-generic.h
> @@ -33,5 +33,6 @@ void __noreturn am33xx_reset_cpu(unsigned long addr);
>  void am33xx_enable_per_clocks(void);
>  int am33xx_init(void);
>  int am33xx_devices_init(void);
> +int am33xx_of_register_bootdevice(void);
>  
>  #endif /* __MACH_AM33XX_GENERIC_H */
> -- 
> 1.9.1
> 
> 
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Re: [PATCH] ARM: imx23-olinuxino: discover usb before ifup

2014-11-03 Thread Sascha Hauer 
On Thu, Oct 23, 2014 at 06:21:38PM +0400, Dmitry Voytik wrote:
> i.MX233 in OLinuXino uses LAN9512 for Ethernet connection.
> LAN9512 is connected to USB. Execute usb command before bringing
> network up.
> 
> This patch makes 'ifup eth0' workable.
> 
> Signed-off-by: Dmitry Voytik 

Applied, thanks

Sascha

> ---
>  arch/arm/boards/imx233-olinuxino/env/network/eth0-discover | 6 ++
>  1 file changed, 6 insertions(+)
>  create mode 100644 arch/arm/boards/imx233-olinuxino/env/network/eth0-discover
> 
> diff --git a/arch/arm/boards/imx233-olinuxino/env/network/eth0-discover 
> b/arch/arm/boards/imx233-olinuxino/env/network/eth0-discover
> new file mode 100644
> index 000..76494fe
> --- /dev/null
> +++ b/arch/arm/boards/imx233-olinuxino/env/network/eth0-discover
> @@ -0,0 +1,6 @@
> +#!/bin/sh
> +
> +#  In OLinuXino board i.MX233 SoC uses LAN9512 (attached to USB) to connect
> +#  to an Ethernet LAN.
> +
> +usb
> -- 
> 1.9.1
> 
> 

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Re: phy-addr via dt

2014-11-03 Thread Wjatscheslaw Stoljarski (Slawa) 
Hi Sascha,

It works! Thanks!

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[PATCHv2 1/3] of: Add of_device_enable_and_register functions

2014-11-03 Thread Teresa Gámez 
Function to enable and register a disabled device.
The devices can be registered using the
device node with of_device_enable_and_register() or
with the device node name/path by using the
of_device_enable_and_register_by_name() function.

Signed-off-by: Teresa Gámez 
---
v2:
- renamed functions

 drivers/of/platform.c | 43 +++
 include/of.h  | 14 ++
 2 files changed, 57 insertions(+)

diff --git a/drivers/of/platform.c b/drivers/of/platform.c
index c417cfd..92ef534 100644
--- a/drivers/of/platform.c
+++ b/drivers/of/platform.c
@@ -197,6 +197,49 @@ static struct device_d *of_platform_device_create(struct 
device_node *np,
return NULL;
 }
 
+/**
+ * of_device_enable_and_register - Enable and register device
+ * @np: pointer to node to enable create device for
+ *
+ * Returns pointer to created platform device, or NULL if a device was not
+ * registered. Unavailable devices will not get registered.
+ */
+struct device_d *of_device_enable_and_register(struct device_node *np)
+{
+   struct device_d *dev;
+
+   of_device_enable(np);
+
+   dev = of_platform_device_create(np, NULL);
+   if (!dev)
+   return NULL;
+
+   return dev;
+}
+EXPORT_SYMBOL(of_device_enable_and_register);
+
+/**
+ * of_device_enable_and_register_by_name - Enable and register device by name
+ * @name: name or path of the device node
+ *
+ * Returns pointer to created platform device, or NULL if a device was not
+ * registered. Unavailable devices will not get registered.
+ */
+struct device_d *of_device_enable_and_register_by_name(const char *name)
+{
+   struct device_node *node;
+
+   node = of_find_node_by_name(NULL, name);
+   if (!node)
+   node = of_find_node_by_path(name);
+
+   if (!node)
+   return NULL;
+
+   return of_device_enable_and_register(node);
+}
+EXPORT_SYMBOL(of_device_enable_and_register_by_name);
+
 #ifdef CONFIG_ARM_AMBA
 static struct device_d *of_amba_device_create(struct device_node *np)
 {
diff --git a/include/of.h b/include/of.h
index 29694a9..7b93c58 100644
--- a/include/of.h
+++ b/include/of.h
@@ -227,6 +227,8 @@ extern int of_platform_populate(struct device_node *root,
const struct of_device_id *matches,
struct device_d *parent);
 extern struct device_d *of_find_device_by_node(struct device_node *np);
+extern struct device_d *of_device_enable_and_register(struct device_node *np);
+extern struct device_d *of_device_enable_and_register_by_name(const char 
*name);
 
 struct cdev *of_parse_partition(struct cdev *cdev, struct device_node *node);
 int of_parse_partitions(struct cdev *cdev, struct device_node *node);
@@ -582,6 +584,18 @@ static inline struct device_d 
*of_find_device_by_node(struct device_node *np)
 {
return NULL;
 }
+
+static inline struct device_d *of_device_enable_and_register(
+   struct device_node *np)
+{
+   return NULL;
+}
+
+static inline struct device_d *of_device_enable_and_register_by_name(
+   const char *name)
+{
+   return NULL;
+}
 #endif
 
 #define for_each_node_by_name(dn, name) \
-- 
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[PATCHv2 3/3] ARM: am335x: phyCORE-AM335x: Create new dts for MLO

2014-11-03 Thread Teresa Gámez 
Use a mlo device tree with all bootable devices disabled.
The bootsource is checked in the board file and only the
needed device is enabled and registered.

Signed-off-by: Teresa Gámez 
---
 arch/arm/boards/phytec-phycore-am335x/board.c|  3 +++
 arch/arm/boards/phytec-phycore-am335x/lowlevel.c |  3 ++-
 arch/arm/dts/Makefile|  2 +-
 arch/arm/dts/am335x-phytec-phycore-som-mlo.dts   | 28 
 4 files changed, 34 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/dts/am335x-phytec-phycore-som-mlo.dts

diff --git a/arch/arm/boards/phytec-phycore-am335x/board.c 
b/arch/arm/boards/phytec-phycore-am335x/board.c
index 64e3904..a72cebd 100644
--- a/arch/arm/boards/phytec-phycore-am335x/board.c
+++ b/arch/arm/boards/phytec-phycore-am335x/board.c
@@ -83,6 +83,9 @@ static int pcm051_devices_init(void)
xloadslots, ARRAY_SIZE(xloadslots));
am33xx_bbu_nand_register_handler("nand", "/dev/nand0.barebox.bb");
 
+   if (IS_ENABLED(CONFIG_SHELL_NONE))
+   return am33xx_of_register_bootdevice();
+
return 0;
 }
 device_initcall(pcm051_devices_init);
diff --git a/arch/arm/boards/phytec-phycore-am335x/lowlevel.c 
b/arch/arm/boards/phytec-phycore-am335x/lowlevel.c
index 55cc667..5ab8b5b 100644
--- a/arch/arm/boards/phytec-phycore-am335x/lowlevel.c
+++ b/arch/arm/boards/phytec-phycore-am335x/lowlevel.c
@@ -118,6 +118,7 @@ struct pcm051_sdram_timings timings[] = {
 };
 
 extern char __dtb_am335x_phytec_phycore_som_start[];
+extern char __dtb_am335x_phytec_phycore_som_mlo_start[];
 extern char __dtb_am335x_phytec_phycore_som_no_spi_start[];
 
 /**
@@ -154,7 +155,7 @@ static noinline void pcm051_board_init(int sdram)
omap_uart_lowlevel_init((void *)AM33XX_UART0_BASE);
putc_ll('>');
 
-   fdt = __dtb_am335x_phytec_phycore_som_start - get_runtime_offset();
+   fdt = __dtb_am335x_phytec_phycore_som_mlo_start - get_runtime_offset();
 
am335x_barebox_entry(fdt);
 }
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a9e9ee7..d8160fe 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -26,7 +26,7 @@ pbl-dtb-$(CONFIG_MACH_NVIDIA_JETSON) += 
tegra124-jetson-tk1.dtb.o
 pbl-dtb-$(CONFIG_MACH_PCA100) += imx27-phytec-phycard-s-rdk-bb.dtb.o
 pbl-dtb-$(CONFIG_MACH_PCAAXL3) += imx6q-phytec-pbaa03.dtb.o
 pbl-dtb-$(CONFIG_MACH_PCM038) += imx27-phytec-phycore-rdk.dtb.o
-pbl-dtb-$(CONFIG_MACH_PCM051) += am335x-phytec-phycore-som.dtb.o 
am335x-phytec-phycore-som-no-spi.dtb.o
+pbl-dtb-$(CONFIG_MACH_PCM051) += am335x-phytec-phycore-som.dtb.o 
am335x-phytec-phycore-som-no-spi.dtb.o am335x-phytec-phycore-som-mlo.dtb.o
 pbl-dtb-$(CONFIG_MACH_PFLA03) += am335x-phytec-phyflex.dtb.o
 pbl-dtb-$(CONFIG_MACH_PHYTEC_PFLA02) += imx6s-phytec-pbab01.dtb.o 
imx6dl-phytec-pbab01.dtb.o imx6q-phytec-pbab01.dtb.o
 pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += 
armada-xp-openblocks-ax3-4-bb.dtb.o
diff --git a/arch/arm/dts/am335x-phytec-phycore-som-mlo.dts 
b/arch/arm/dts/am335x-phytec-phycore-som-mlo.dts
new file mode 100644
index 000..4117439
--- /dev/null
+++ b/arch/arm/dts/am335x-phytec-phycore-som-mlo.dts
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2014 Teresa Gámez  PHYTEC Messtechnik GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "am33xx.dtsi"
+#include "am335x-phytec-phycore-som.dtsi"
+
+/ {
+   model = "Phytec phyCORE AM335x";
+   compatible = "phytec,phycore-am335x-som", "ti,am33xx";
+};
+
+/* Keep all boosources disabled, we enable and register them
+ * later while booting.
+ */
+
+&mmc1 {
+   status = "disabled";
+};
+
+&gpmc {
+   status = "disabled";
+};
-- 
1.9.1


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[PATCHv2 2/3] ARM: am335x: Add register of boot devices

2014-11-03 Thread Teresa Gámez 
Add support for registering disabled boot devices from oftree.
Creating a device tree with all bootable devices disabled, makes
it possible to only enable and register the devices needed to
load the next stage bootloader.

Signed-off-by: Teresa Gámez 
---
v2:
- updated of funcion name

 arch/arm/mach-omap/am33xx_generic.c  | 31 
 arch/arm/mach-omap/include/mach/am33xx-generic.h |  1 +
 2 files changed, 32 insertions(+)

diff --git a/arch/arm/mach-omap/am33xx_generic.c 
b/arch/arm/mach-omap/am33xx_generic.c
index f293134..b561575 100644
--- a/arch/arm/mach-omap/am33xx_generic.c
+++ b/arch/arm/mach-omap/am33xx_generic.c
@@ -428,3 +428,34 @@ void am335x_sdram_init(int ioctrl, const struct 
am33xx_cmd_control *cmd_ctrl,
 
am33xx_config_sdram(emif_regs);
 }
+
+int am33xx_of_register_bootdevice(void)
+{
+   struct device_d *dev;
+
+   switch (bootsource_get()) {
+   case BOOTSOURCE_MMC:
+   if (bootsource_get_instance() == 0)
+   dev = 
of_device_enable_and_register_by_name("mmc@4806");
+   else
+   dev = 
of_device_enable_and_register_by_name("mmc@481d8000");
+   break;
+   case BOOTSOURCE_NAND:
+   dev = of_device_enable_and_register_by_name("gpmc@5000");
+   break;
+   case BOOTSOURCE_SPI:
+   dev = of_device_enable_and_register_by_name("spi@4803");
+   break;
+   default:
+   /* Use nand fallback */
+   dev = of_device_enable_and_register_by_name("gpmc@5000");
+   break;
+   }
+
+   if (!dev) {
+   printf("Unable to register boot device\n");
+   return -ENODEV;
+   }
+
+   return 0;
+}
diff --git a/arch/arm/mach-omap/include/mach/am33xx-generic.h 
b/arch/arm/mach-omap/include/mach/am33xx-generic.h
index 6c85d51..7312061 100644
--- a/arch/arm/mach-omap/include/mach/am33xx-generic.h
+++ b/arch/arm/mach-omap/include/mach/am33xx-generic.h
@@ -33,5 +33,6 @@ void __noreturn am33xx_reset_cpu(unsigned long addr);
 void am33xx_enable_per_clocks(void);
 int am33xx_init(void);
 int am33xx_devices_init(void);
+int am33xx_of_register_bootdevice(void);
 
 #endif /* __MACH_AM33XX_GENERIC_H */
-- 
1.9.1


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Re: [For next PATCH] ARM: dts: phyFLEX: Add SKEW clock delays to emac0 node

2014-11-03 Thread Sascha Hauer 
On Mon, Nov 03, 2014 at 11:12:15AM +0100, Wadim Egorov wrote:
> The KSZ9031 gigabit phy on the PBA-B-01 carrier board needs special settings
> for the RGMII skew control register.
> 
> Signed-off-by: Wadim Egorov 

Applied, thanks

Sascha

> ---
>  arch/arm/dts/am335x-phytec-phyflex.dts |   11 +++
>  1 files changed, 11 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/dts/am335x-phytec-phyflex.dts 
> b/arch/arm/dts/am335x-phytec-phyflex.dts
> index 4dde328..c4481f5 100644
> --- a/arch/arm/dts/am335x-phytec-phyflex.dts
> +++ b/arch/arm/dts/am335x-phytec-phyflex.dts
> @@ -212,6 +212,17 @@
>   phy_id = <&davinci_mdio>, <1>;
>   phy-mode = "rgmii";
>   dual_emac_res_vlan = <1>;
> +
> + /* clock skew correction, maximum possible on KSZ9031 is
> + 2^5 - 1 * 0,06ns = 1860ps, micrel datasheet M-081712-0.11 p.58*/
> + rxc-skew-ps = <1860>;
> + txc-skew-ps = <1860>;
> +
> + /* align tx signals to zero, leave rx to default */
> + txd0-skew-ps = <0>;
> + txd1-skew-ps = <0>;
> + txd2-skew-ps = <0>;
> + txd3-skew-ps = <0>;
>  };
>  
>  &cpsw_emac1 {
> -- 
> 1.7.0.4
> 
> 
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Re: [For next PATCH v2 1/2] arm: am33xx: Add rmii2_crs_dv mux selection in SMA2 register

2014-11-03 Thread Sascha Hauer 
On Mon, Nov 03, 2014 at 11:10:23AM +0100, Wadim Egorov wrote:
> "Silicon revision 1.0 devices only provide the MMC2_DAT7 signal when Mode3 is
> selected. Silicon revision 2.0 and newer devices implement another level of
> pin multiplexing which provides the original MMC2_DAT7 signal or RMII2_CRS_DV
> signal when Mode3 is selected. This new level of of pin multiplexing is
> selected with bit zero of the SMA2 register."
> 
> See AM335x Sitara Processors Manual.
> 
> Signed-off-by: Wadim Egorov 

Applied, thanks

Sascha

> ---
> v2: Added silicon revision check. SMA2 register does not exist in revision 1.0
> 
>  arch/arm/mach-omap/am33xx_generic.c  |   17 +
>  arch/arm/mach-omap/include/mach/am33xx-generic.h |1 +
>  2 files changed, 18 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-omap/am33xx_generic.c 
> b/arch/arm/mach-omap/am33xx_generic.c
> index f293134..7fe8881 100644
> --- a/arch/arm/mach-omap/am33xx_generic.c
> +++ b/arch/arm/mach-omap/am33xx_generic.c
> @@ -428,3 +428,20 @@ void am335x_sdram_init(int ioctrl, const struct 
> am33xx_cmd_control *cmd_ctrl,
>  
>   am33xx_config_sdram(emif_regs);
>  }
> +
> +#define AM33XX_CONTROL_SMA2_OFS  0x1320
> +
> +/**
> + * am33xx_select_rmii2_crs_dv - Select RMII2_CRS_DV on GPMC_A9 pin in MODE3
> + */
> +void am33xx_select_rmii2_crs_dv(void)
> +{
> + uint32_t val;
> +
> + if (am33xx_get_cpu_rev() == AM335X_ES1_0)
> + return;
> +
> + val = readl(AM33XX_CTRL_BASE + AM33XX_CONTROL_SMA2_OFS);
> + val |= 0x0001;
> + writel(val, AM33XX_CTRL_BASE + AM33XX_CONTROL_SMA2_OFS);
> +}
> diff --git a/arch/arm/mach-omap/include/mach/am33xx-generic.h 
> b/arch/arm/mach-omap/include/mach/am33xx-generic.h
> index 6c85d51..1264e7e 100644
> --- a/arch/arm/mach-omap/include/mach/am33xx-generic.h
> +++ b/arch/arm/mach-omap/include/mach/am33xx-generic.h
> @@ -33,5 +33,6 @@ void __noreturn am33xx_reset_cpu(unsigned long addr);
>  void am33xx_enable_per_clocks(void);
>  int am33xx_init(void);
>  int am33xx_devices_init(void);
> +void am33xx_select_rmii2_crs_dv(void);
>  
>  #endif /* __MACH_AM33XX_GENERIC_H */
> -- 
> 1.7.0.4
> 
> 
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Re: [PATCH] serial: ns16550: Remove unused fields from NS16550_plat structure

2014-11-03 Thread Sascha Hauer 
Hi Alexander,

On Thu, Oct 30, 2014 at 01:32:31PM +0300, Alexander Shiyan wrote:
> Signed-off-by: Alexander Shiyan 
> ---
>  include/ns16550.h | 3 ---
>  1 file changed, 3 deletions(-)
> 
> diff --git a/include/ns16550.h b/include/ns16550.h
> index 876bb04..ccf950b 100644
> --- a/include/ns16550.h
> +++ b/include/ns16550.h
> @@ -34,9 +34,6 @@ struct NS16550_plat {
>   /** Clock speed */
>   unsigned int clock;
>   int shift;
> - unsigned int flags;
> - int mmio;
> -#define NS16650_FLAG_DISABLE_FIFO1
>  };

This patch removes flags but not its usage in the driver itself.

Squashed this into the commit:


>From 668db8bea2c201c3cbdb096cac58287d7b38f396 Mon Sep 17 00:00:00 2001
From: Sascha Hauer 
Date: Mon, 3 Nov 2014 13:24:15 +0100
Subject: [PATCH] fixup! serial: ns16550: Remove unused fields from
 NS16550_plat structure

---
 drivers/serial/serial_ns16550.c | 5 +
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c
index 4ca7444..53d48a0 100644
--- a/drivers/serial/serial_ns16550.c
+++ b/drivers/serial/serial_ns16550.c
@@ -441,10 +441,7 @@ static int ns16550_probe(struct device_d *dev)
cdev->setbrg = ns16550_setbaudrate;
cdev->linux_console_name = devtype->linux_console_name;
 
-   if (plat && (plat->flags & NS16650_FLAG_DISABLE_FIFO))
-   priv->fcrval = FCRVAL & ~FCR_FIFO_EN;
-   else
-   priv->fcrval = FCRVAL;
+   priv->fcrval = FCRVAL;
 
devtype->init_port(cdev);
 
-- 
2.1.1

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Re: [PATCH 2/3] mxs: iomux-imx23/imx28: unify mode definition

2014-11-03 Thread Sascha Hauer 
On Fri, Oct 24, 2014 at 12:46:00AM +0200, Uwe Kleine-König wrote:
> i.MX23 and i.MX28 iomux mode definitions differ for no good reason.
> 
> Compared to the two previous definitions this introduces a few flags
> that are not used yet but this changes in the next commit to detect
> broken definitions.
> 
> Apart from different constants this commit intends to be a no-op. If
> there are changes in the register values there is either a bug in this
> patch or the used mode is broken (e.g. a pullup value is defined for a
> pin that has a bitkeeper).
> 
> Signed-off-by: Uwe Kleine-König 
> ---
>  arch/arm/mach-mxs/include/mach/iomux-imx23.h | 61 -
>  arch/arm/mach-mxs/include/mach/iomux-imx28.h | 60 
>  arch/arm/mach-mxs/include/mach/iomux.h   | 82 
> 
>  3 files changed, 82 insertions(+), 121 deletions(-)
> 
> diff --git a/arch/arm/mach-mxs/include/mach/iomux-imx23.h 
> b/arch/arm/mach-mxs/include/mach/iomux-imx23.h
> index 39d69810ef08..1e225f8fc51b 100644
> --- a/arch/arm/mach-mxs/include/mach/iomux-imx23.h
> +++ b/arch/arm/mach-mxs/include/mach/iomux-imx23.h
> @@ -9,72 +9,11 @@
>   * but WITHOUT ANY WARRANTY; without even the implied warranty of
>   * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>   * GNU General Public License for more details.
> - *
>   */
>  
> -/* 332211
> - * 10987654321098765432109876543210
> - *  ^^^_ Register Number
> - *   Bit offset
> - *^^ Function
> - *   ^__ Drive strength feature present
> - *  ^___ Pull up present
> - *^^ Drive strength setting
> - *   ^__ Pull up / bit keeper setting
> - *  ^___ Voltage select present
> - * ^ Voltage selection
> - * ^ direction if enabled as GPIO (1 = 
> output)
> - *^_ initial output value if enabled as GPIO 
> and configured as output
> - *   ^__ Bit keeper present
> - */
>  #ifndef __ASM_MACH_IOMUX_MX23_H
>  #define __ASM_MACH_IOMUX_MX23_H
>  
> -/* control pad's function */
> -#define FBIT_SHIFT (3)
> -#define PORTF(bank,bit)  (((bit) << FBIT_SHIFT) | (bank))
> -#define GET_PORTF(x) ((x) & 0x7)
> -#define GET_FBITPOS(x) (((x) >> FBIT_SHIFT) & 0xf)
> -#define GET_GPIO_NO(x) ((GET_PORTF(x) << 4) + GET_FBITPOS(m))
> -#define FUNC_SHIFT 7
> -#define FUNC(x)  ((x) << FUNC_SHIFT)
> -#define GET_FUNC(x) (((x) >> FUNC_SHIFT) & 3)
> -#define IS_GPIO (3)
> -
> -/* control pad's GPIO feature if enabled */
> -#define GPIO_OUT (1 << 19)
> -#define GPIO_VALUE(x) ((x) << 20)
> -#define GPIO_IN (0 << 19)
> -#define GET_GPIODIR(x) (!!((x) & (1 << 19)))
> -#define GET_GPIOVAL(x) (!!((x) & (1 << 20)))
> -
> -/* control pad's drive strength */
> -#define SE (1 << 9)
> -#define SE_PRESENT(x) (!!((x) & SE))
> -#define STRENGTH(x) ((x) << 11)
> -#define S4MA 0   /* used to define a 4 mA drive strength */
> -#define S8MA 1   /* used to define a 8 mA drive strength */
> -#define S12MA 2  /* used to define a 12 mA drive strength */
> -#define S16MA 3  /* used to define a 16 mA drive strength, not all pads 
> can drive this current! */
> -#define GET_STRENGTH(x) (((x) >> 11) & 0x3)
> -
> -/* control pad's pull up / bit keeper feature */
> -#define PE (1 << 10)
> -#define BK (1 << 21)
> -#define PE_PRESENT(x) (!!((x) & PE))
> -#define BK_PRESENT(x) (!!((x) & BK))
> -#define PULLUP(x) ((x) << 13)
> -#define BITKEEPER(x) ((x) << 14)
> -#define GET_PULLUP(x) (!!((x) & (1 << 13)))
> -#define GET_BITKEEPER(x) (!!((x) & BITKEEPER(1)))
> -
> -/* control pad's voltage feature */
> -#define VE (1 << 14)
> -#define VE_PRESENT(x) (!!((x) & VE))
> -#define VE_1_8V (0 << 15)
> -#define VE_2_5V (0 << 15) /* don't ask my why, RTFM */
> -#define GET_VOLTAGE(x) (!!((x) & (1 << 15)))
> -
>  /* Bank 0, pins 0 ... 15, GPIO pins 0 ... 15 */
>  #define GPMI_D15 (FUNC(0) | PORTF(0, 15) | SE | PE)
>  #define GPMI_D15_AUART2_TX   (FUNC(1) | PORTF(0, 15) | SE | PE)
> diff --git a/arch/arm/mach-mxs/include/mach/iomux-imx28.h 
> b/arch/arm/mach-mxs/include/mach/iomux-imx28.h
> index c9ab8a93aea2..6119f3caf98d 100644
> --- a/arch/arm/mach-mxs/include/mach/iomux-imx28.h
> +++ b/arch/arm/mach-mxs/include/mach/iomux-imx28.h
> @@ -10,69 +10,9 @@
>   * GNU General Public License for more details.
>   */
>  
> -/* 332211
> - * 10987654321098765432109876543210
> - *^_ Bit offset
> - * ^^^__ Register Number
> - *   ^^_ Function
> - *  ^___ Drive strength feature present
> - * ^ Pull up present
> - *   ^^_ Drive strength se

Re: phy-addr via dt

2014-11-03 Thread Sascha Hauer 
Hi Wjatscheslaw,

On Mon, Nov 03, 2014 at 11:53:06AM +0100, Wjatscheslaw Stoljarski (Slawa) wrote:
> Hi,
> 
> Is it possible to set default phy-addr for fec_imx driver via device tree or 
> in barebox environment?

It should be possible to add a mdio subnode to the fec device node
and then to add the phy-handle property to the fec node.
Something like:

fec {
phy-handle = <ðphy>;

mdio {
ethphy: phy@7 {
reg = <7>;
};
};
};

Sascha

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phy-addr via dt

2014-11-03 Thread Wjatscheslaw Stoljarski (Slawa) 
Hi,

Is it possible to set default phy-addr for fec_imx driver via device tree or in 
barebox environment?

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[For next PATCH] ARM: dts: phyFLEX: Add SKEW clock delays to emac0 node

2014-11-03 Thread Wadim Egorov 
The KSZ9031 gigabit phy on the PBA-B-01 carrier board needs special settings
for the RGMII skew control register.

Signed-off-by: Wadim Egorov 
---
 arch/arm/dts/am335x-phytec-phyflex.dts |   11 +++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/arch/arm/dts/am335x-phytec-phyflex.dts 
b/arch/arm/dts/am335x-phytec-phyflex.dts
index 4dde328..c4481f5 100644
--- a/arch/arm/dts/am335x-phytec-phyflex.dts
+++ b/arch/arm/dts/am335x-phytec-phyflex.dts
@@ -212,6 +212,17 @@
phy_id = <&davinci_mdio>, <1>;
phy-mode = "rgmii";
dual_emac_res_vlan = <1>;
+
+   /* clock skew correction, maximum possible on KSZ9031 is
+   2^5 - 1 * 0,06ns = 1860ps, micrel datasheet M-081712-0.11 p.58*/
+   rxc-skew-ps = <1860>;
+   txc-skew-ps = <1860>;
+
+   /* align tx signals to zero, leave rx to default */
+   txd0-skew-ps = <0>;
+   txd1-skew-ps = <0>;
+   txd2-skew-ps = <0>;
+   txd3-skew-ps = <0>;
 };
 
 &cpsw_emac1 {
-- 
1.7.0.4


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[For next PATCH v2 1/2] arm: am33xx: Add rmii2_crs_dv mux selection in SMA2 register

2014-11-03 Thread Wadim Egorov 
"Silicon revision 1.0 devices only provide the MMC2_DAT7 signal when Mode3 is
selected. Silicon revision 2.0 and newer devices implement another level of
pin multiplexing which provides the original MMC2_DAT7 signal or RMII2_CRS_DV
signal when Mode3 is selected. This new level of of pin multiplexing is
selected with bit zero of the SMA2 register."

See AM335x Sitara Processors Manual.

Signed-off-by: Wadim Egorov 
---
v2: Added silicon revision check. SMA2 register does not exist in revision 1.0

 arch/arm/mach-omap/am33xx_generic.c  |   17 +
 arch/arm/mach-omap/include/mach/am33xx-generic.h |1 +
 2 files changed, 18 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap/am33xx_generic.c 
b/arch/arm/mach-omap/am33xx_generic.c
index f293134..7fe8881 100644
--- a/arch/arm/mach-omap/am33xx_generic.c
+++ b/arch/arm/mach-omap/am33xx_generic.c
@@ -428,3 +428,20 @@ void am335x_sdram_init(int ioctrl, const struct 
am33xx_cmd_control *cmd_ctrl,
 
am33xx_config_sdram(emif_regs);
 }
+
+#define AM33XX_CONTROL_SMA2_OFS0x1320
+
+/**
+ * am33xx_select_rmii2_crs_dv - Select RMII2_CRS_DV on GPMC_A9 pin in MODE3
+ */
+void am33xx_select_rmii2_crs_dv(void)
+{
+   uint32_t val;
+
+   if (am33xx_get_cpu_rev() == AM335X_ES1_0)
+   return;
+
+   val = readl(AM33XX_CTRL_BASE + AM33XX_CONTROL_SMA2_OFS);
+   val |= 0x0001;
+   writel(val, AM33XX_CTRL_BASE + AM33XX_CONTROL_SMA2_OFS);
+}
diff --git a/arch/arm/mach-omap/include/mach/am33xx-generic.h 
b/arch/arm/mach-omap/include/mach/am33xx-generic.h
index 6c85d51..1264e7e 100644
--- a/arch/arm/mach-omap/include/mach/am33xx-generic.h
+++ b/arch/arm/mach-omap/include/mach/am33xx-generic.h
@@ -33,5 +33,6 @@ void __noreturn am33xx_reset_cpu(unsigned long addr);
 void am33xx_enable_per_clocks(void);
 int am33xx_init(void);
 int am33xx_devices_init(void);
+void am33xx_select_rmii2_crs_dv(void);
 
 #endif /* __MACH_AM33XX_GENERIC_H */
-- 
1.7.0.4


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[For next PATCH v2 2/2] phyFLEX: Select RMII2_CRS_DV on GPMC_A9 pin

2014-11-03 Thread Wadim Egorov 
Signed-off-by: Wadim Egorov 
---
 arch/arm/boards/phytec-phyflex-am335x/board.c |2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boards/phytec-phyflex-am335x/board.c 
b/arch/arm/boards/phytec-phyflex-am335x/board.c
index 12fad8f..cf7dd2e 100644
--- a/arch/arm/boards/phytec-phyflex-am335x/board.c
+++ b/arch/arm/boards/phytec-phyflex-am335x/board.c
@@ -89,6 +89,8 @@ static int pfla03_devices_init(void)
armlinux_set_architecture(MACH_TYPE_PFLA03);
defaultenv_append_directory(defaultenv_phyflex_am335x);
 
+   am33xx_select_rmii2_crs_dv();
+
am33xx_bbu_spi_nor_mlo_register_handler("MLO.spi", "/dev/m25p0.xload");
am33xx_bbu_spi_nor_register_handler("spi", "/dev/m25p0.barebox");
am33xx_bbu_nand_xloadslots_register_handler("MLO.nand",
-- 
1.7.0.4


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Re: [PATCH 00/13] Tegra124 PCIe

2014-11-03 Thread Sascha Hauer 
On Sun, Nov 02, 2014 at 09:13:42PM +0100, Lucas Stach wrote:
> This series implements PCIe on Tegra124 aka K1. With
> this applied the Jetson-TK1 platform is finally useable
> for proper development, as the network is working now.
> 
> The series is spun against -next, as it depends on the
> previous Tegra PCIe work found there. I hope Sascha can
> still squeeze this in before the next release.

Just squeezed this in ;)

Sascha

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Re: [PATCH] serial: ns16550: Remove unused fields from NS16550_plat structure

2014-11-03 Thread Sascha Hauer 
On Thu, Oct 30, 2014 at 01:32:31PM +0300, Alexander Shiyan wrote:
> Signed-off-by: Alexander Shiyan 
> ---
>  include/ns16550.h | 3 ---
>  1 file changed, 3 deletions(-)

Applied, thanks

Sascha


-- 
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Industrial Linux Solutions | http://www.pengutronix.de/  |
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Re: [PATCH] ARM: atmel: add sama5d4 xplained ultra board support

2014-11-03 Thread Sascha Hauer 
On Wed, Oct 29, 2014 at 04:59:34PM +0800, Bo Shen wrote:
> The sama5d4 xplained ultra board support following features:
>   - NAND flash support
>   - SPI flash support
>   - MMC card support (MCI1)
>   - LCD display support (with QT1070)
>   - Ethernet support
> 
> Signed-off-by: Bo Shen 

Applied, thanks

Sascha


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Re: [PATCH 0/2] fix typos (import from linux kernel)

2014-11-03 Thread Sascha Hauer 
On Thu, Oct 30, 2014 at 03:30:37PM +0300, Antony Pavlov wrote:
> Antony Pavlov (2):
>   Typoes:  "whith" -> "with"
>   Makefile: fix typos
> 
>  Makefile  | 7 +++
>  drivers/mci/mxs.c | 2 +-
>  2 files changed, 4 insertions(+), 5 deletions(-)

Applied, thanks

Sascha

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