Re: [PATCH v2 10/10] clk: at91: fix warning about missing const-safety
Hello Sam, On 1/4/19 22:48, Sam Ravnborg wrote: > Hi Ahmad. > > On Mon, Apr 01, 2019 at 11:31:06AM +0200, Ahmad Fatoum wrote: >> compiling clk-main.c results in: >> >> warning: passing argument 1 of 'memcpy' discards 'const' qualifier from >> pointer target type [-Wdiscarded-qualifiers] >> memcpy(clkmain->clk.parent_names, parent_names, parents_array_size); >>^ >> >> Avoid this by replacing the xzalloc+memcpy pair with xmemdup. >> Zero-initialization of the buffer isn't necessary, because >> memcpy spans the whole buffer. >> >> Signed-off-by: Ahmad Fatoum > > It looks like clk-generated.c would suffer from the same > if you managed to build it. > Could you maybe verify and fix this too? Indeed. I've sent a patch as reply to this thread. Cheers Ahmad > > Sam > -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH v2 11/10] clk: at91: fix warning about missing const-safety
compiling clk-generated.c results in: warning: passing argument 1 of 'memcpy' discards 'const' qualifier from pointer target type [-Wdiscarded-qualifiers] memcpy(gck->hw.parent_names, parent_names, parents_array_size); ~~~^ Avoid this by replacing the xzalloc+memcpy pair with xmemdup. Zero-initialization of the buffer isn't necessary, because memcpy spans the whole buffer. Suggested-by: Sam Ravnborg Signed-off-by: Ahmad Fatoum --- drivers/clk/at91/clk-generated.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-generated.c index 60516ca10f36..396c35f3a7b3 100644 --- a/drivers/clk/at91/clk-generated.c +++ b/drivers/clk/at91/clk-generated.c @@ -181,8 +181,7 @@ at91_clk_register_generated(struct regmap *regmap, gck->hw.ops = &generated_ops; parents_array_size = num_parents * sizeof(gck->hw.parent_names[0]); - gck->hw.parent_names = xzalloc(parents_array_size); - memcpy(gck->hw.parent_names, parent_names, parents_array_size); + gck->hw.parent_names = xmemdup(parent_names, parents_array_size); gck->hw.num_parents = num_parents; /* gck->hw.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; */ -- 2.20.1 ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH v2 10/10] clk: at91: fix warning about missing const-safety
Hi Ahmad. On Mon, Apr 01, 2019 at 11:31:06AM +0200, Ahmad Fatoum wrote: > compiling clk-main.c results in: > > warning: passing argument 1 of 'memcpy' discards 'const' qualifier from > pointer target type [-Wdiscarded-qualifiers] > memcpy(clkmain->clk.parent_names, parent_names, parents_array_size); >^ > > Avoid this by replacing the xzalloc+memcpy pair with xmemdup. > Zero-initialization of the buffer isn't necessary, because > memcpy spans the whole buffer. > > Signed-off-by: Ahmad Fatoum It looks like clk-generated.c would suffer from the same if you managed to build it. Could you maybe verify and fix this too? Sam ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH v2 09/10] ARM: at91: remove at91sama5_get_ddram_size helper
On Mon, Apr 01, 2019 at 11:31:05AM +0200, Ahmad Fatoum wrote: > Substitute the current #ifdefery in at91sam9_ddrsdr.h by > open-coding at91sama5_get_ddram_size wherever it was called. > > Suggested-by: Sascha Hauer > Signed-off-by: Ahmad Fatoum Reviewed-by: Sam Ravnborg ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH v2 07/10] ARM: at91: remove at91sam9n12_get_ddram_size helper
On Mon, Apr 01, 2019 at 11:31:03AM +0200, Ahmad Fatoum wrote: > Substitute the current #ifdefery in at91sam9_ddrsdr.h by > open-coding at91sam9n12_get_ddram_size wherever it was called. > > Suggested-by: Sascha Hauer > Signed-off-by: Ahmad Fatoum Reviewed-by: Sam Ravnborg ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH v2 06/10] ARM: at91: remove at91sam9g45_get_ddram_size helper
On Mon, Apr 01, 2019 at 11:31:02AM +0200, Ahmad Fatoum wrote: > Substitute the current #ifdefery in at91sam9_ddrsdr.h by > open-coding at91sam9g45_get_ddram_size wherever it was called. > > Suggested-by: Sascha Hauer > Signed-off-by: Ahmad Fatoum Reviewed-by: Sam Ravnborg ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH v2 08/10] ARM: at91: remove at91sam9x5_get_ddram_size helper
On Mon, Apr 01, 2019 at 11:31:04AM +0200, Ahmad Fatoum wrote: > Substitute the current #ifdefery in at91sam9_ddrsdr.h by > open-coding at91sam9x5_get_ddram_size wherever it was called. > > Suggested-by: Sascha Hauer > Signed-off-by: Ahmad Fatoum Reviewed-by: Sam Ravnborg ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH] clk: imx6: remove quirky clk_set_parent(LDB_diN_sel, pll5_video_div)
On 1/4/19 22:15, Ahmad Fatoum wrote: Argh. This is RFC PATCH 6/6.. Missed the prefix. -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH] clk: imx6: remove quirky clk_set_parent(LDB_diN_sel, pll5_video_div)
barebox has inherited the clk_set_parent(ldb_diN_sel, pll5_video_div)
from upstream kernel commit 32f3b8da22 ("ARM i.MX6q: set the LDB serial
clock parent to the video PLL"), where it was enabled for all i.MX6Q
revisions after 1.0. It was applied whenever CONFIG_DRIVER_VIDEO_IMX_IPUV3
was defined.
The kernel removed this reparenting again as a preventive measure
against ERR009219 in 03d576f202 ("clk: imx6: Make the LDB_DI0 and
LDB_DI1 clocks read-only").
As the kernel used the device tree compatible, which is the same
for e.g. i.MX6Solo and DualLite, but barebox queried ANATOP which
lists different CPU types for i.MX6Solo and DualLite and because
i.MX6QuadPlus wasn't supported at first, barebox grew to do
the reparenting on the odd set of:
- Quad and Dual rev >1.0
- DualLite
- Solo rev >1.0
- QuadPlus and DualPlus rev >1.0
On all of these, except for the QuadPlus and the DualPlus, this
reparenting may glitch the LDB so that it permanently locks up.
Previous commits work around this glitch and this commit
now removes this unituituve quirk and instead of _sometimes_
breaking the boards in the previous list, _always_ breaks them
if they are strictly dependent on pll5_video_div being the parent
of ldb_diN_sel.
As of v2019.03.0, following mainline boards are potentially broken
by this (i.e. they're supported by barebox, are in the list above,
have a LDB enabled and might be defining CONFIG_DRIVER_VIDEO_IMX_IPUV3):
- imx6qdl-zii-rdu2.dtsi
- imx6qdl-udoo.dtsi
- imx6qdl-mba6x.dtsi
- imx6q-var-custom.dts
- imx6q-guf-santaro.dts
- imx6q-embedsky-e9.dtsi
These and any other affected non-mainline boards can have the old behavior
reinstated by adding the following to their respective device trees, but
this time in a glitch-free manner:
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
<&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
};
If barebox is configured to show a boot splash screen, this snippet
should exist in the barebox device tree. If barebox acts on it, the
kernel will show following warning:
ccm: ldb_di0_sel already changed from reset value: 0
ccm: ldb_di1_sel already changed from reset value: 0
This warning is safe to ignore.
Cc: Andrey Smirnov
Cc: Raphael Poggi
Cc: Sascha Hauer
Cc: Lucas Stach
Cc: Jean-Christophe PLAGNIOL-VILLARD
Signed-off-by: Ahmad Fatoum
---
drivers/clk/imx/clk-imx6.c | 19 ---
1 file changed, 19 deletions(-)
diff --git a/drivers/clk/imx/clk-imx6.c b/drivers/clk/imx/clk-imx6.c
index 65d8f4cd89be..a595785fed60 100644
--- a/drivers/clk/imx/clk-imx6.c
+++ b/drivers/clk/imx/clk-imx6.c
@@ -484,14 +484,6 @@ static void init_ldb_clks(struct device_node *np, void
__iomem *ccm_base)
sel[0][3] = sel[0][2] = sel[0][1] = sel[0][0];
sel[1][3] = sel[1][2] = sel[1][1] = sel[1][0];
- /*
-* This is for compatibility with the existing barebox behavior where
-* these configurations had their ldb_diN_sel clocks reparented.
-*/
- if (!(cpu_is_mx6s() && imx_silicon_revision() == IMX_CHIP_REV_1_0)) {
- sel[0][3] = sel[1][3] = LDB_DI_SEL_PLL5_VIDEO_DIV;
- }
-
of_assigned_ldb_sels(np, &sel[0][3], &sel[1][3]);
for (i = 0; i < 2; i++) {
@@ -646,17 +638,6 @@ static void imx6_add_video_clks(void __iomem *anab, void
__iomem *cb, struct dev
clk_set_parent(clks[IMX6QDL_CLK_IPU1_DI1_PRE_SEL],
clks[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
clk_set_parent(clks[IMX6QDL_CLK_IPU2_DI0_PRE_SEL],
clks[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
clk_set_parent(clks[IMX6QDL_CLK_IPU2_DI1_PRE_SEL],
clks[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
-
- /*
-* On SoC affected by ERR009219, it's not safe to call these
-* clk_set_parent. Thus we do this via init_ldb_clks if the device tree
-* indicates so. QuadPlus doesn't suffer from the erratum, so for now,
-* we leave the old behavior as is.
-*/
- if (((cpu_is_plus() && imx_silicon_revision() != IMX_CHIP_REV_1_0))) {
- clk_set_parent(clks[IMX6QDL_CLK_LDB_DI0_SEL],
clks[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
- clk_set_parent(clks[IMX6QDL_CLK_LDB_DI1_SEL],
clks[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
- }
}
static int imx6_ccm_probe(struct device_d *dev)
--
2.20.1
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[PATCH 0/6] clk: imx6: work around LDB hang caused by ERR009219
Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk
tree, the glitchy parent mux of ldb_di[x]_clk can cause a glitch to
enter the ldb_di_ipu_div divider[1]. If the divider gets locked up, no
ldb_di[x]_clk is generated, and the LVDS display will hang when the
ipu_di_clk is sourced from ldb_di_clk.
The glitch can happen if an assigned-clock-parents property sets
ldb_di[x]_clk's parent or in Linux versions prior to v4.10,
out-of-the-box because then Linux used to hardcode a
clk_set_parent(ldb_di[x]_sel, pll5_video_div) in clk-imx6.c.
The upstream kernel commit that added this reparenting
32f3b8da22 ("ARM i.MX6q: set the LDB serial clock parent to the video PLL")
made its way into barebox as well.
In barebox, this reparenting occurs whenever CONFIG_DRIVER_VIDEO_IMX_IPUV3
is defined and the CPU was either exactly a DualLite or of a revision
bigger than 1.0. The list of CPUs where the reparenting should happen
has not been updated as clk-imx6.c gained support for newer i.MX6 variants,
with the effect that the reparenting nowadays happens on the odd set of:
- (Quad or Dual) and rev >1.0
- DualLite
- Solo and rev >1.0
- (QuadPlus or DualPlus) rev >1.0
The erratum already has a Linux workaround. On barebox, it can currently
happen if there's an appropriate assigned-clock-parents property or the
reparenting happens (i.e. CONFIG_DRIVER_VIDEO_IMX_IPUV3 is selected on a
board with the aforementioned CPU/Revision pairs). Linux has removed the
reparenting along with the bug fix. If barebox did this, boards that
depended on the reparenting may be broken.
For this reason, the first four patches work around the erratum in a way
that the high level reparenting behavior remains as-is. The optional fifth
patch then drops the reparenting, same as Linux does, simplifying the code
and eventually improving the newly broken boards device tree as well (they
would need to spell out what clock parents they expect for their LDB
muxes instead of depending on a barebox quirk).
This series applies on top of current upstream/next, particularly
e0e87be220fa ("clk: mux: Support CLK_SET_RATE_NO_REPARENT flag").
Rundown
---
PATCH 1/6 and 4/6 are cosmetic. The former is an exercise in De Morgan's
Laws and rewrites the condition to spell out exactly when the reparenting
to video PLL happens. The latter replaces some hardcoded constants from the
kernel patch with symbolic names.
PATCH 2/6 and 3/6 import the kernel patches that worked around the
erratum by:
1) replacing the hardcoded clk_set_parent in a glitch-free manner
2) parsing assigned-clock-parents of ldb_di_sel clocks specially and
applying the reparenting using the glitch-free method above
PATCH 5/6 makes the ldb_di_sel clocks read-only to prevent
the generic clock code from trying to reconfigure the affected muxes
in a glitchy manner when it parses assigned-clock-parents.
These patches have been reordered from their upstream order to avoid
breaking boards which had the implicit assumption that the LDB clocks
have the video PLL as a parent.
Now that utmost care was invested into not breaking these boards,
RFC PATCH 6/6 breaks them by getting rid of the reparenting along with
its funny conditionals.
The line of thinking is:
If you explicitly use assigned-clock-parents to affect the LDB clocks,
this patch series will apply these without the lock up the erratum may
cause. Everything else is unchanged.
If you don't have that property, but CONFIG_DRIVER_IMX_IPUV3 is
selected, your LDB clocks would've locked up every hundred (?) or so
boots anyway, so you would've noticed, right?
Well, you didn't notice, so it should be Okay to just remove that
reparenting quirk. This simplifies the code and if the default of
mmdc_ch1_axi being the parent of the LDB clocks indeed breaks
you, you will bisect, compare /sys/kernel/debug/clk/clk_summary
and find PATCH 5/6 that tells you the exact device tree snippet you need
to copy into your device tree to restore the old behavior!
To save possibly affected mainline board authors the bisection effort,
they are CC'd in the last patch, so they can take a look. The
relevant boards are:
- imx6qdl-zii-rdu2.dtsi
- imx6qdl-udoo.dtsi
- imx6qdl-mba6x.dtsi
- imx6q-var-custom.dts
- imx6q-guf-santaro.dts
- imx6q-embedsky-e9.dtsi
[1] The ERR009219 erratum is explained in detail in EB821 ("LDB Clock
Switch Procedure & i.MX6 Asynchronous Clock Switching Guidelines"):
http://www.nxp.com/files/32bit/doc/eng_bulletin/EB821.pdf
Ahmad Fatoum (3):
clk: imx6: provide helper to check if video PLL post dividers work
clk: imx6: define an enum for ldb mux inputs
clk: imx6: remove quirky clk_set_parent(LDB_diN_sel, pll5_video_div)
Fabio Estevam (1):
clk: imx6: Fix procedure to switch the parent of LDB_DI_CLK
Philipp Zabel (2):
clk: imx6: Mask mmdc_ch1 handshake for periph2_sel and
mmdc_ch1_axi_podf
clk: imx6: Make the LDB_DI0 and LDB_DI1 clocks read-only
drivers/clk/imx/clk-imx6.c | 323 +++
[PATCH 3/6] clk: imx6: Fix procedure to switch the parent of LDB_DI_CLK
From: Fabio Estevam
Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk
tree, the glitchy parent mux of ldb_di[x]_clk can cause a glitch to
enter the ldb_di_ipu_div divider. If the divider gets locked up, no
ldb_di[x]_clk is generated, and the LVDS display will hang when the
ipu_di_clk is sourced from ldb_di_clk.
To fix the problem, both the new and current parent of the ldb_di_clk
should be disabled before the switch. This patch ensures that correct
steps are followed when ldb_di_clk parent is switched in the beginning
of boot. The glitchy muxes are then registered as read-only. The clock
parent can be selected using the assigned-clocks and
assigned-clock-parents properties of the ccm device tree node:
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_MMDC_CH1_AXI>,
<&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
};
The issue is explained in detail in EB821 ("LDB Clock Switch Procedure &
i.MX6 Asynchronous Clock Switching Guidelines") [1].
[1] http://www.nxp.com/files/32bit/doc/eng_bulletin/EB821.pdf
Signed-off-by: Ranjani Vaidyanathan
Signed-off-by: Fabio Estevam
Signed-off-by: Philipp Zabel
Reviewed-by: Akshay Bhat
Tested-by Joshua Clayton
Tested-by: Charles Kang
Signed-off-by: Shawn Guo
[afa: ported to barebox from Linux commit 5d283b0838]
[afa: maintained reparenting for imx6qp revision >1.0 as before]
Signed-off-by: Ahmad Fatoum
---
drivers/clk/imx/clk-imx6.c | 292 -
1 file changed, 284 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/imx/clk-imx6.c b/drivers/clk/imx/clk-imx6.c
index 21cbc77c50c5..d12b494d578c 100644
--- a/drivers/clk/imx/clk-imx6.c
+++ b/drivers/clk/imx/clk-imx6.c
@@ -70,6 +70,12 @@ static inline int cpu_has_working_video_pll_post_div(void) {
imx_silicon_revision() == IMX_CHIP_REV_1_0);
}
+/* i.MX6 Quad/Dual/DualLite/Solo are all affected */
+static inline int cpu_has_err009219(void) {
+ return cpu_is_mx6d() || cpu_is_mx6q() ||
+ cpu_is_mx6dl() || cpu_is_mx6s();
+}
+
static const char *step_sels[] = {
"osc",
"pll2_pfd2_396m",
@@ -299,9 +305,89 @@ static struct clk_div_table video_div_table[] = {
{ /* sentinel */ }
};
+static int ldb_di_sel_by_clock_id(int clock_id)
+{
+ switch (clock_id) {
+ case IMX6QDL_CLK_PLL5_VIDEO_DIV:
+ if (!cpu_has_working_video_pll_post_div())
+ return -ENOENT;
+ return 0;
+ case IMX6QDL_CLK_PLL2_PFD0_352M:
+ return 1;
+ case IMX6QDL_CLK_PLL2_PFD2_396M:
+ return 2;
+ case IMX6QDL_CLK_MMDC_CH1_AXI:
+ return 3;
+ case IMX6QDL_CLK_PLL3_USB_OTG:
+ return 4;
+ default:
+ return -ENOENT;
+ }
+}
+
+static void of_assigned_ldb_sels(struct device_node *node,
+unsigned int *ldb_di0_sel,
+unsigned int *ldb_di1_sel)
+{
+ struct of_phandle_args clkspec;
+ int index, rc, num_parents;
+ int parent, child, sel;
+
+ num_parents = of_count_phandle_with_args(node, "assigned-clock-parents",
+"#clock-cells");
+ for (index = 0; index < num_parents; index++) {
+ rc = of_parse_phandle_with_args(node, "assigned-clock-parents",
+ "#clock-cells", index, &clkspec);
+ if (rc < 0) {
+ /* skip empty (null) phandles */
+ if (rc == -ENOENT)
+ continue;
+ else
+ return;
+ }
+ if (clkspec.np != node || clkspec.args[0] >= IMX6QDL_CLK_END) {
+ pr_err("ccm: parent clock %d not in ccm\n", index);
+ return;
+ }
+ parent = clkspec.args[0];
+
+ rc = of_parse_phandle_with_args(node, "assigned-clocks",
+ "#clock-cells", index, &clkspec);
+ if (rc < 0)
+ return;
+ if (clkspec.np != node || clkspec.args[0] >= IMX6QDL_CLK_END) {
+ pr_err("ccm: child clock %d not in ccm\n", index);
+ return;
+ }
+ child = clkspec.args[0];
+
+ if (child != IMX6QDL_CLK_LDB_DI0_SEL &&
+ child != IMX6QDL_CLK_LDB_DI1_SEL)
+ continue;
+
+ sel = ldb_di_sel_by_clock_id(parent);
+ if (sel < 0) {
+ pr_err("ccm: invalid ldb_di%d parent clock: %d\n",
+ child == IMX6QDL_CLK_LDB_DI1_SEL, parent);
+
[PATCH 4/6] clk: imx6: define an enum for ldb mux inputs
For better readability should this code be reviewed
in future, replace the hardcoded input numbers
with an enum.
This is just a cosmetic change and was verified
to not affect clk-imx6.o.
Signed-off-by: Ahmad Fatoum
---
drivers/clk/imx/clk-imx6.c | 41 +++---
1 file changed, 25 insertions(+), 16 deletions(-)
diff --git a/drivers/clk/imx/clk-imx6.c b/drivers/clk/imx/clk-imx6.c
index d12b494d578c..f527d1d5e565 100644
--- a/drivers/clk/imx/clk-imx6.c
+++ b/drivers/clk/imx/clk-imx6.c
@@ -213,12 +213,20 @@ static const char *ipu_sels[] = {
"pll3_pfd1_540m",
};
+enum ldb_di_sel { /* for use in init_ldb_clks */
+ LDB_DI_SEL_PLL5_VIDEO_DIV = 0,
+ LDB_DI_SEL_PLL2_PFD0_352M = 1,
+ LDB_DI_SEL_PLL2_PFD2_396M = 2,
+ LDB_DI_SEL_MMDC_CH1_AXI = 3,
+ LDB_DI_SEL_PLL3_USB_OTG = 4,
+};
+
static const char *ldb_di_sels[] = {
- "pll5_video_div",
- "pll2_pfd0_352m",
- "pll2_pfd2_396m",
- "mmdc_ch1_axi_podf",
- "pll3_usb_otg",
+ [LDB_DI_SEL_PLL5_VIDEO_DIV] = "pll5_video_div",
+ [LDB_DI_SEL_PLL2_PFD0_352M] = "pll2_pfd0_352m",
+ [LDB_DI_SEL_PLL2_PFD2_396M] = "pll2_pfd2_396m",
+ [LDB_DI_SEL_MMDC_CH1_AXI] = "mmdc_ch1_axi_podf",
+ [LDB_DI_SEL_PLL3_USB_OTG] = "pll3_usb_otg",
};
static const char *ipu_di_pre_sels[] = {
@@ -311,23 +319,23 @@ static int ldb_di_sel_by_clock_id(int clock_id)
case IMX6QDL_CLK_PLL5_VIDEO_DIV:
if (!cpu_has_working_video_pll_post_div())
return -ENOENT;
- return 0;
+ return LDB_DI_SEL_PLL5_VIDEO_DIV;
case IMX6QDL_CLK_PLL2_PFD0_352M:
- return 1;
+ return LDB_DI_SEL_PLL2_PFD0_352M;
case IMX6QDL_CLK_PLL2_PFD2_396M:
- return 2;
+ return LDB_DI_SEL_PLL2_PFD2_396M;
case IMX6QDL_CLK_MMDC_CH1_AXI:
- return 3;
+ return LDB_DI_SEL_MMDC_CH1_AXI;
case IMX6QDL_CLK_PLL3_USB_OTG:
- return 4;
+ return LDB_DI_SEL_PLL3_USB_OTG;
default:
return -ENOENT;
}
}
static void of_assigned_ldb_sels(struct device_node *node,
-unsigned int *ldb_di0_sel,
-unsigned int *ldb_di1_sel)
+enum ldb_di_sel *ldb_di0_sel,
+enum ldb_di_sel *ldb_di1_sel)
{
struct of_phandle_args clkspec;
int index, rc, num_parents;
@@ -466,7 +474,7 @@ static void mmdc_ch1_reenable(void __iomem *ccm_base)
static void init_ldb_clks(struct device_node *np, void __iomem *ccm_base)
{
unsigned int reg;
- unsigned int sel[2][4];
+ enum ldb_di_sel sel[2][4];
int i;
reg = readl(ccm_base + CCM_CS2CDR);
@@ -481,14 +489,14 @@ static void init_ldb_clks(struct device_node *np, void
__iomem *ccm_base)
* these configurations had their ldb_diN_sel clocks reparented.
*/
if (!(cpu_is_mx6s() && imx_silicon_revision() == IMX_CHIP_REV_1_0)) {
- sel[0][3] = sel[1][3] = 0;
+ sel[0][3] = sel[1][3] = LDB_DI_SEL_PLL5_VIDEO_DIV;
}
of_assigned_ldb_sels(np, &sel[0][3], &sel[1][3]);
for (i = 0; i < 2; i++) {
/* Warn if a glitch might have been introduced already */
- if (sel[i][0] != 3) {
+ if (sel[i][0] != LDB_DI_SEL_MMDC_CH1_AXI) {
pr_warn("ccm: ldb_di%d_sel already changed from reset
value: %d\n",
i, sel[i][0]);
}
@@ -497,7 +505,8 @@ static void init_ldb_clks(struct device_node *np, void
__iomem *ccm_base)
continue;
/* Only switch to or from pll2_pfd2_396m if it is disabled */
- if ((sel[i][0] == 2 || sel[i][3] == 2) &&
+ if ((sel[i][0] == LDB_DI_SEL_PLL2_PFD2_396M ||
+sel[i][3] == LDB_DI_SEL_PLL2_PFD2_396M) &&
(clk_get_parent(clks[IMX6QDL_CLK_PERIPH_PRE]) ==
clks[IMX6QDL_CLK_PLL2_PFD2_396M])) {
pr_err("ccm: ldb_di%d_sel: couldn't disable
pll2_pfd2_396m\n",
--
2.20.1
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[PATCH 1/6] clk: imx6: provide helper to check if video PLL post dividers work
Audio/Video PLL post dividers don't work on i.MX6q revision 1.0.
This helper can be reused in the upcoming workaround patch for
erratum ERR009219.
The check in the helper has been inverted to make it clearer which
platforms are affected. Old call site was adjusted to spell
out what is really happening nowadays (with clk-imx6.c covering
more variants than just i.MX6Quad and DualLite):
!rev1.0 || mx6dl
== !rev1.0 || !!mx6dl
== !(rev1.0 && !mx6dl)
== !(rev1.0 && (mx6s || mx6q || mx6qp || mx6d || mx6dp))
== !(rev1.0 && ((mx6q || mx6d) || (mx6s || mx6qp || mx6dp)))
== !((rev1.0 && (mx6q || mx6d)) || (rev1.0 && (mx6s || mx6qp || mx6dp)))
== (!(rev1.0 && (mx6q || mx6d)) && !(rev1.0 && (mx6s || mx6qp || mx6dp)))
== cpu_has_working_video_pll_post_div() && !(rev1.0 && (mx6s || mx6qp || mx6dp))
Signed-off-by: Ahmad Fatoum
---
drivers/clk/imx/clk-imx6.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/imx/clk-imx6.c b/drivers/clk/imx/clk-imx6.c
index 35b995dae24e..88c4bcde1cb3 100644
--- a/drivers/clk/imx/clk-imx6.c
+++ b/drivers/clk/imx/clk-imx6.c
@@ -64,6 +64,12 @@ static inline int cpu_is_plus(void)
return cpu_is_mx6qp() || cpu_is_mx6dp();
}
+/* Audio/Video PLL post dividers don't work on i.MX6q revision 1.0 */
+static inline int cpu_has_working_video_pll_post_div(void) {
+ return !((cpu_is_mx6q() || cpu_is_mx6d()) &&
+imx_silicon_revision() == IMX_CHIP_REV_1_0);
+}
+
static const char *step_sels[] = {
"osc",
"pll2_pfd2_396m",
@@ -341,8 +347,8 @@ static void imx6_add_video_clks(void __iomem *anab, void
__iomem *cb)
clk_set_parent(clks[IMX6QDL_CLK_IPU2_DI0_PRE_SEL],
clks[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
clk_set_parent(clks[IMX6QDL_CLK_IPU2_DI1_PRE_SEL],
clks[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
- if ((imx_silicon_revision() != IMX_CHIP_REV_1_0) ||
- cpu_is_mx6dl()) {
+ if (cpu_has_working_video_pll_post_div() &&
+ !((cpu_is_plus() || cpu_is_mx6s()) && imx_silicon_revision() ==
IMX_CHIP_REV_1_0)) {
clk_set_parent(clks[IMX6QDL_CLK_LDB_DI0_SEL],
clks[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
clk_set_parent(clks[IMX6QDL_CLK_LDB_DI1_SEL],
clks[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
}
--
2.20.1
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[PATCH 2/6] clk: imx6: Mask mmdc_ch1 handshake for periph2_sel and mmdc_ch1_axi_podf
From: Philipp Zabel
MMDC CH1 is not used on i.MX6Q, so the handshake needed to change the
parent of periph2_sel or the divider of mmdc_ch1_axi_podf will never
succeed.
Disable the handshake mechanism to allow changing the frequency of
mmdc_ch1_axi, allowing to use it as a possible source for the LDB DI
clock.
Signed-off-by: Philipp Zabel
Signed-off-by: Fabio Estevam
Signed-off-by: Shawn Guo
[afa: ported to barebox from Linux commit f13abeff2c]
[afa: moved call site to where it would've been moved in following commit]
Signed-off-by: Ahmad Fatoum
---
drivers/clk/imx/clk-imx6.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/clk/imx/clk-imx6.c b/drivers/clk/imx/clk-imx6.c
index 88c4bcde1cb3..21cbc77c50c5 100644
--- a/drivers/clk/imx/clk-imx6.c
+++ b/drivers/clk/imx/clk-imx6.c
@@ -299,6 +299,19 @@ static struct clk_div_table video_div_table[] = {
{ /* sentinel */ }
};
+#define CCM_CCDR 0x04
+
+#define CCDR_MMDC_CH1_MASK BIT(16)
+
+static void __init imx6q_mmdc_ch1_mask_handshake(void __iomem *ccm_base)
+{
+ unsigned int reg;
+
+ reg = readl(ccm_base + CCM_CCDR);
+ reg |= CCDR_MMDC_CH1_MASK;
+ writel(reg, ccm_base + CCM_CCDR);
+}
+
static void imx6_add_video_clks(void __iomem *anab, void __iomem *cb)
{
clks[IMX6QDL_CLK_PLL5_POST_DIV] =
imx_clk_divider_table("pll5_post_div", "pll5_video", anab + 0xa0, 19, 2,
post_div_table);
@@ -306,6 +319,9 @@ static void imx6_add_video_clks(void __iomem *anab, void
__iomem *cb)
clks[IMX6QDL_CLK_IPU1_SEL] = imx_clk_mux("ipu1_sel", cb
+ 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
clks[IMX6QDL_CLK_IPU2_SEL] = imx_clk_mux("ipu2_sel", cb
+ 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
+
+ imx6q_mmdc_ch1_mask_handshake(cb);
+
clks[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_p("ldb_di0_sel",
cb + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels));
clks[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_p("ldb_di1_sel",
cb + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels));
clks[IMX6QDL_CLK_IPU1_DI0_PRE_SEL] = imx_clk_mux_p("ipu1_di0_pre_sel",
cb + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
--
2.20.1
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[PATCH 5/6] clk: imx6: Make the LDB_DI0 and LDB_DI1 clocks read-only
From: Philipp Zabel
Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk
tree, the glitchy parent mux of ldb_di[x]_clk can cause a glitch to
enter the ldb_di_ipu_div divider. If the divider gets locked up, no
ldb_di[x]_clk is generated, and the LVDS display will hang when the
ipu_di_clk is sourced from ldb_di_clk.
To fix the problem, both the new and current parent of the ldb_di_clk
should be disabled before the switch. As this can not be guaranteed by
the clock framework during runtime, make the ldb_di[x]_sel muxes read-only.
A workaround to set the muxes once during boot could be added to the
kernel or bootloader.
Signed-off-by: Philipp Zabel
Signed-off-by: Fabio Estevam
Signed-off-by: Shawn Guo
[afa: ported from Linux kernel commit 03d576f202]
[afa: added exception for i.MX6QP, see kernel commit f4a0a6c309]
Signed-off-by: Ahmad Fatoum
---
drivers/clk/imx/clk-imx6.c | 9 ++---
drivers/clk/imx/clk.h | 8
2 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/imx/clk-imx6.c b/drivers/clk/imx/clk-imx6.c
index f527d1d5e565..65d8f4cd89be 100644
--- a/drivers/clk/imx/clk-imx6.c
+++ b/drivers/clk/imx/clk-imx6.c
@@ -601,10 +601,13 @@ static void imx6_add_video_clks(void __iomem *anab, void
__iomem *cb, struct dev
* ldb_di_sel clocks.
*/
init_ldb_clks(ccm_np, cb);
- }
- clks[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_p("ldb_di0_sel",
cb + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels));
- clks[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_p("ldb_di1_sel",cb
+ 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels));
+ clks[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_ldb("ldb_di0_sel",
cb + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels));
+ clks[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_ldb("ldb_di1_sel",
cb + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels));
+ } else {
+ clks[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_p("ldb_di0_sel",
cb + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels));
+ clks[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_p("ldb_di1_sel",
cb + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels));
+ }
clks[IMX6QDL_CLK_IPU1_DI0_PRE_SEL] = imx_clk_mux_p("ipu1_di0_pre_sel",
cb + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
clks[IMX6QDL_CLK_IPU1_DI1_PRE_SEL] = imx_clk_mux_p("ipu1_di1_pre_sel",
cb + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
clks[IMX6QDL_CLK_IPU2_DI0_PRE_SEL] = imx_clk_mux_p("ipu2_di0_pre_sel",
cb + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 875c76a8b3e4..04286f03f727 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -39,6 +39,14 @@ static inline struct clk *imx_clk_divider_table(const char
*name,
width, table, 0);
}
+static inline struct clk *imx_clk_mux_ldb(const char *name, void __iomem *reg,
+ u8 shift, u8 width, const char **parents, int num_parents)
+{
+ return clk_mux(name, CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
reg,
+ shift, width, parents, num_parents, CLK_MUX_READ_ONLY);
+}
+
+
static inline struct clk *imx_clk_fixed_factor(const char *name,
const char *parent, unsigned int mult, unsigned int div)
{
--
2.20.1
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Re: [PATCH v3 02/15] ARM: at91: import at91bootstrap's at91_ddrsdrc.h
On Mon, Apr 01, 2019 at 03:36:06PM +0200, Ahmad Fatoum wrote: > Hello Roland, > > On 4/1/19 2:32 PM, Roland Hieber wrote: > > On Mon, Apr 01, 2019 at 12:18:10PM +0200, Ahmad Fatoum wrote: > >> Instead of adding missing definitions to the existing at91sam9_ddrsdr.h > >> and adapting the incoming DDRAM initialization code from at91bootstrap, > >> just replace the lightly used existing header with: > >> https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/include/arch/at91_ddrsdrc.h > >> > >> For easier comprehension, the replacement is done in three steps: > >> Here the header is imported. > >> > >> Signed-off-by: Ahmad Fatoum > >> --- > >> .../arm/mach-at91/include/mach/at91_ddrsdrc.h | 288 ++ > >> 1 file changed, 288 insertions(+) > >> create mode 100644 arch/arm/mach-at91/include/mach/at91_ddrsdrc.h > >> > >> diff --git a/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h > >> b/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h > >> new file mode 100644 > >> index ..57d0d8f489c4 > >> --- /dev/null > >> +++ b/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h > >> @@ -0,0 +1,288 @@ > >> +// SPDX-License-Identifier: BSD-1-Clause > > > > I've told you this in our personal converation before, but I'll happily > > repeat it here for a broader audience: The original GitHub source says > > > > * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY > > EXPRESS OR > > * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED > > WARRANTIES OF > > * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND > > NON-INFRINGEMENT ARE > > * DISCLAIMED. > > > > which additionally disclaims warranty for "NON-INFRINGEMENT", which is > > not in BSD-1-Clause text you added in the previous commit. I regard this > > as a substantive change of the licensing conditions according to the > > SPDX License List Matching Guidelines [s] and rather use the original > > license headers here as long as there is no SPDX license identifier for > > it. > To restate my opinion: > Atmel already disclaims ANY EXPRESS or IMPLIED WARRANTIES, which should > include NON-INFRINGEMENT regardless if whether it was explicitly listed > or not. Ah, good, it seems I misinterpreted your argument earlier. Sorry, so no objections from my side then. - Roland ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH v3 13/15] ARM: at91: microchip-ksz9477-evb: implement first stage
On 4/1/19 2:37 PM, Roland Hieber wrote:
> On Mon, Apr 01, 2019 at 12:18:21PM +0200, Ahmad Fatoum wrote:
>> This imports the low level init code from at91bootstrap
>> https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/board/sama5d3_xplained/sama5d3_xplained.c
>>
>> Signed-off-by: Ahmad Fatoum
>> ---
>> .../boards/microchip-ksz9477-evb/lowlevel.c | 208 +-
>> arch/arm/mach-at91/Kconfig| 2 +
>> arch/arm/mach-at91/include/mach/at91_pmc.h| 8 +
>> arch/arm/mach-at91/include/mach/sama5d3.h | 1 +
>> images/Makefile.at91 | 5 +
>> 5 files changed, 220 insertions(+), 4 deletions(-)
>>
>> diff --git a/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c
>> b/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c
>> index 4293f8aaa57d..cf44021bdfb7 100644
>> --- a/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c
>> +++ b/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c
>> @@ -1,7 +1,19 @@
>> +// SPDX-License-Identifier: GPL-2.0-only AND BSD-1-Clause
>> /*
>> + * Copyright (c) 2014, Atmel Corporation
>> * Copyright (C) 2018 Ahmad Fatoum, Pengutronix
>> *
>> - * Under GPLv2
>> + *
>> + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
>> + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
>> WARRANTIES OF
>> + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
>> ARE
>> + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
>> + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
>> NOT
>> + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
>> DATA,
>> + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
>> + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
>> + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
>> SOFTWARE,
>> + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
>> */
>
> Here you included the original disclaimer? For what reason? :)
Was already writing the cover letter and was too lazy to do the
git send-email spiel again.
>
> - Roland
>
>>
>> #include
>> @@ -10,18 +22,206 @@
>> #include
>> #include
>>
>> -#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +
>> +/* PCK = 528MHz, MCK = 132MHz */
>> +#define MASTER_CLOCK13200
>> +
>> +#define PMC_BASE IOMEM(SAMA5D3_BASE_PMC)
>> +#define sama5d3_pmc_enable_periph_clock(clk) \
>> +at91_pmc_enable_periph_clock(PMC_BASE, clk)
>> +
>> +#define BAUDRATE(mck, baud) \
>> +((mck) * 10) / ((baud) * 16)) % 10) >= 5) ? \
>> +(mck / (baud * 16) + 1) : ((mck) / (baud * 16)))
>> +
>> +
>> +static void configure_periph_a_piob_pin(unsigned int pin)
>> +{
>> +void __iomem *pio = IOMEM(SAMA5D3_BASE_PIOB);
>> +u32 mask = pin_to_mask(pin);
>> +
>> +at91_mux_disable_interrupt(pio, mask);
>> +at91_mux_set_pullup(pio, mask, 0);
>> +at91_mux_pio3_set_pulldown(pio, mask, 0);
>> +
>> +at91_mux_pio3_set_A_periph(pio, mask);
>> +
>> +at91_mux_gpio_disable(pio, mask);
>> +}
>> +
>> +static noinline void dbgu_init(void)
>> +{
>> +sama5d3_pmc_enable_periph_clock(SAMA5D3_ID_PIOB);
>> +
>> +configure_periph_a_piob_pin(AT91_PIN_PB30);
>> +configure_periph_a_piob_pin(AT91_PIN_PB31);
>> +
>> +sama5d3_pmc_enable_periph_clock(SAMA5D3_ID_DBGU);
>> +at91_dbgu_setup_ll(AT91_BASE_DBGU1, BAUDRATE(MASTER_CLOCK, 115200));
>> +
>> +putc_ll('>');
>> +}
>> +
>> +static void ddramc_reg_config(struct at91_ddramc_register *ddramc_config)
>> +{
>> +ddramc_config->mdr = (AT91C_DDRC2_DBW_32_BITS
>> +| AT91C_DDRC2_MD_DDR2_SDRAM);
>> +
>> +ddramc_config->cr = (AT91C_DDRC2_NC_DDR10_SDR9
>> +| AT91C_DDRC2_NR_13
>> +| AT91C_DDRC2_CAS_3
>> +| AT91C_DDRC2_DISABLE_RESET_DLL
>> +| AT91C_DDRC2_ENABLE_DLL
>> +| AT91C_DDRC2_ENRDM_ENABLE
>> +| AT91C_DDRC2_NB_BANKS_8
>> +| AT91C_DDRC2_NDQS_DISABLED
>> +| AT91C_DDRC2_DECOD_INTERLEAVED
>> +| AT91C_DDRC2_UNAL_SUPPORTED);
>> +
>> +/*
>> + * The DDR2-SDRAM device requires a refresh every 15.625 us or 7.81 us.
>> + * With a 133 MHz frequency, the refresh timer count register must to be
>> + * set with (15.625 x 133 MHz) ~ 2084 i.e. 0x824
>> + * or (7.81 x 133 MHz) ~ 1039 i.e. 0x40F.
>> + */
>> +ddramc_config->rtr = 0x40F; /* Refresh timer: 7.812us */
>> +
>> +/* One clock cycle @ 133 MHz = 7.5 ns */
>> +ddramc_config->t0pr = (AT91C_DDRC2_TRAS_(6) /* 6 * 7.5 = 45 ns */
>> +| AT91C_DDRC2_TRCD_(2) /* 2 * 7.5 = 22.5 ns */
>> +
Re: [PATCH v3 02/15] ARM: at91: import at91bootstrap's at91_ddrsdrc.h
Hello Roland, On 4/1/19 2:32 PM, Roland Hieber wrote: > On Mon, Apr 01, 2019 at 12:18:10PM +0200, Ahmad Fatoum wrote: >> Instead of adding missing definitions to the existing at91sam9_ddrsdr.h >> and adapting the incoming DDRAM initialization code from at91bootstrap, >> just replace the lightly used existing header with: >> https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/include/arch/at91_ddrsdrc.h >> >> For easier comprehension, the replacement is done in three steps: >> Here the header is imported. >> >> Signed-off-by: Ahmad Fatoum >> --- >> .../arm/mach-at91/include/mach/at91_ddrsdrc.h | 288 ++ >> 1 file changed, 288 insertions(+) >> create mode 100644 arch/arm/mach-at91/include/mach/at91_ddrsdrc.h >> >> diff --git a/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h >> b/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h >> new file mode 100644 >> index ..57d0d8f489c4 >> --- /dev/null >> +++ b/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h >> @@ -0,0 +1,288 @@ >> +// SPDX-License-Identifier: BSD-1-Clause > > I've told you this in our personal converation before, but I'll happily > repeat it here for a broader audience: The original GitHub source says > > * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS > OR > * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED > WARRANTIES OF > * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT > ARE > * DISCLAIMED. > > which additionally disclaims warranty for "NON-INFRINGEMENT", which is > not in BSD-1-Clause text you added in the previous commit. I regard this > as a substantive change of the licensing conditions according to the > SPDX License List Matching Guidelines [s] and rather use the original > license headers here as long as there is no SPDX license identifier for > it. To restate my opinion: Atmel already disclaims ANY EXPRESS or IMPLIED WARRANTIES, which should include NON-INFRINGEMENT regardless if whether it was explicitly listed or not. At least one person agrees with me: http://lists.opensource.org/pipermail/license-discuss_lists.opensource.org/2006-August/011643.html > > Same probably also applies to the other source files. > > [s]: https://spdx.org/spdx-license-list/matching-guidelines > > - Roland > >> +/* >> + * Copyright (c) 2006, Atmel Corporation >> + */ >> +#ifndef __AT91_DDRSDRC_H__ >> +#define __AT91_DDRSDRC_H__ >> + >> +/ Register offset in AT91S_HDDRSDRC2 structure ***/ >> +#define AT91C_HDDRSDRC2_MR 0x00/* Mode Register */ >> +#define AT91C_HDDRSDRC2_RTR 0x04/* Refresh Timer Register */ >> +#define AT91C_HDDRSDRC2_CR 0x08/* Configuration Register */ >> +#define AT91C_HDDRSDRC2_T0PR0x0C/* Timing Parameter 0 >> Register */ >> +#define AT91C_HDDRSDRC2_T1PR0x10/* Timing Parameter 1 >> Register */ >> +#define AT91C_HDDRSDRC2_T2PR0x14/* Timing Parameter 2 >> Register */ >> +#define AT91C_HDDRSDRC2_T3PR0x18/* Timing Parameter 3 >> Register */ >> +#define AT91C_HDDRSDRC2_LPR 0x1C/* Low-power Register */ >> +#define AT91C_HDDRSDRC2_MDR 0x20/* Memory Device Register */ >> +#define AT91C_HDDRSDRC2_DLL 0x24/* DLL Information Register */ >> +#define AT91C_HDDRSDRC2_HS 0x2C/* High Speed Register */ >> + >> +/* below items defined for sama5d3x */ >> +#define AT91C_MPDDRC_LPDDR2_HS 0x24/* MPDDRC LPDDR2 High >> Speed Register */ >> +#define AT91C_MPDDRC_LPDDR2_LPR 0x28/* MPDDRC LPDDR2 >> Low-power Register */ >> +#define AT91C_MPDDRC_LPDDR2_CAL_MR4 0x2C/* MPDDRC LPDDR2 >> Calibration and MR4 Register */ >> +#define AT91C_MPDDRC_LPDDR2_TIM_CAL 0x30/* MPDDRC LPDDR2 Timing >> Calibration Register */ >> +#define AT91C_MPDDRC_IO_CALIBR 0x34/* MPDDRC IO >> Calibration */ >> +#define AT91C_MPDDRC_OCMS 0x38/* MPDDRC OCMS Register >> */ >> +#define AT91C_MPDDRC_OCMS_KEY1 0x3C/* MPDDRC OCMS KEY1 >> Register */ >> +#define AT91C_MPDDRC_OCMS_KEY2 0x40/* MPDDRC OCMS KEY2 >> Register */ >> +/* 0x54 ~ 0x70 Reserved */ >> +#define AT91C_MPDDRC_DLL_MOR0x74/* MPDDRC DLL Master >> Offset Register */ >> +#define AT91C_MPDDRC_DLL_SOR0x78/* MPDDRC DLL Slave >> Offset Register */ >> +#define AT91C_MPDDRC_DLL_MSR0x7C/* MPDDRC DLL Master >> Status Register */ >> +#define AT91C_MPDDRC_DLL_S0SR 0x80/* MPDDRC DLL Slave 0 >> Status Register */ >> +#define AT91C_MPDDRC_DLL_S1SR 0x84/* MPDDRC DLL Slave 1 >> Status Register */ >> + >> +#define AT91C_MPDDRC_RD_DATA_PATH 0x5C/* MPDDRC Read Data Path */ >> + >> +/* 0x94 ~ 0xE0 Reserved */ >> +#define AT91C_HDDRSDRC2_WPCR0xE4/* Write Protect Mode >> Register */ >> +#define AT91C_HDDRSDR
Re: [PATCH v3 13/15] ARM: at91: microchip-ksz9477-evb: implement first stage
On Mon, Apr 01, 2019 at 12:18:21PM +0200, Ahmad Fatoum wrote:
> This imports the low level init code from at91bootstrap
> https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/board/sama5d3_xplained/sama5d3_xplained.c
>
> Signed-off-by: Ahmad Fatoum
> ---
> .../boards/microchip-ksz9477-evb/lowlevel.c | 208 +-
> arch/arm/mach-at91/Kconfig| 2 +
> arch/arm/mach-at91/include/mach/at91_pmc.h| 8 +
> arch/arm/mach-at91/include/mach/sama5d3.h | 1 +
> images/Makefile.at91 | 5 +
> 5 files changed, 220 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c
> b/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c
> index 4293f8aaa57d..cf44021bdfb7 100644
> --- a/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c
> +++ b/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c
> @@ -1,7 +1,19 @@
> +// SPDX-License-Identifier: GPL-2.0-only AND BSD-1-Clause
> /*
> + * Copyright (c) 2014, Atmel Corporation
> * Copyright (C) 2018 Ahmad Fatoum, Pengutronix
> *
> - * Under GPLv2
> + *
> + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
> + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
> OF
> + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
> + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
> + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
> NOT
> + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
> DATA,
> + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
> + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
> + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
> SOFTWARE,
> + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> */
Here you included the original disclaimer? For what reason? :)
- Roland
>
> #include
> @@ -10,18 +22,206 @@
> #include
> #include
>
> -#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +/* PCK = 528MHz, MCK = 132MHz */
> +#define MASTER_CLOCK 13200
> +
> +#define PMC_BASE IOMEM(SAMA5D3_BASE_PMC)
> +#define sama5d3_pmc_enable_periph_clock(clk) \
> + at91_pmc_enable_periph_clock(PMC_BASE, clk)
> +
> +#define BAUDRATE(mck, baud) \
> + ((mck) * 10) / ((baud) * 16)) % 10) >= 5) ? \
> + (mck / (baud * 16) + 1) : ((mck) / (baud * 16)))
> +
> +
> +static void configure_periph_a_piob_pin(unsigned int pin)
> +{
> + void __iomem *pio = IOMEM(SAMA5D3_BASE_PIOB);
> + u32 mask = pin_to_mask(pin);
> +
> + at91_mux_disable_interrupt(pio, mask);
> + at91_mux_set_pullup(pio, mask, 0);
> + at91_mux_pio3_set_pulldown(pio, mask, 0);
> +
> + at91_mux_pio3_set_A_periph(pio, mask);
> +
> + at91_mux_gpio_disable(pio, mask);
> +}
> +
> +static noinline void dbgu_init(void)
> +{
> + sama5d3_pmc_enable_periph_clock(SAMA5D3_ID_PIOB);
> +
> + configure_periph_a_piob_pin(AT91_PIN_PB30);
> + configure_periph_a_piob_pin(AT91_PIN_PB31);
> +
> + sama5d3_pmc_enable_periph_clock(SAMA5D3_ID_DBGU);
> + at91_dbgu_setup_ll(AT91_BASE_DBGU1, BAUDRATE(MASTER_CLOCK, 115200));
> +
> + putc_ll('>');
> +}
> +
> +static void ddramc_reg_config(struct at91_ddramc_register *ddramc_config)
> +{
> + ddramc_config->mdr = (AT91C_DDRC2_DBW_32_BITS
> + | AT91C_DDRC2_MD_DDR2_SDRAM);
> +
> + ddramc_config->cr = (AT91C_DDRC2_NC_DDR10_SDR9
> + | AT91C_DDRC2_NR_13
> + | AT91C_DDRC2_CAS_3
> + | AT91C_DDRC2_DISABLE_RESET_DLL
> + | AT91C_DDRC2_ENABLE_DLL
> + | AT91C_DDRC2_ENRDM_ENABLE
> + | AT91C_DDRC2_NB_BANKS_8
> + | AT91C_DDRC2_NDQS_DISABLED
> + | AT91C_DDRC2_DECOD_INTERLEAVED
> + | AT91C_DDRC2_UNAL_SUPPORTED);
> +
> + /*
> + * The DDR2-SDRAM device requires a refresh every 15.625 us or 7.81 us.
> + * With a 133 MHz frequency, the refresh timer count register must to be
> + * set with (15.625 x 133 MHz) ~ 2084 i.e. 0x824
> + * or (7.81 x 133 MHz) ~ 1039 i.e. 0x40F.
> + */
> + ddramc_config->rtr = 0x40F; /* Refresh timer: 7.812us */
> +
> + /* One clock cycle @ 133 MHz = 7.5 ns */
> + ddramc_config->t0pr = (AT91C_DDRC2_TRAS_(6) /* 6 * 7.5 = 45 ns */
> + | AT91C_DDRC2_TRCD_(2) /* 2 * 7.5 = 22.5 ns */
> + | AT91C_DDRC2_TWR_(2) /* 2 * 7.5 = 15 ns */
> + | AT91C_DDRC2_TRC_(8) /* 8 * 7.5 = 75 ns */
> + | AT91C_DDRC2_TRP_(2) /* 2 * 7.5 = 15 ns */
> +
Re: [PATCH v3 02/15] ARM: at91: import at91bootstrap's at91_ddrsdrc.h
On Mon, Apr 01, 2019 at 12:18:10PM +0200, Ahmad Fatoum wrote: > Instead of adding missing definitions to the existing at91sam9_ddrsdr.h > and adapting the incoming DDRAM initialization code from at91bootstrap, > just replace the lightly used existing header with: > https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/include/arch/at91_ddrsdrc.h > > For easier comprehension, the replacement is done in three steps: > Here the header is imported. > > Signed-off-by: Ahmad Fatoum > --- > .../arm/mach-at91/include/mach/at91_ddrsdrc.h | 288 ++ > 1 file changed, 288 insertions(+) > create mode 100644 arch/arm/mach-at91/include/mach/at91_ddrsdrc.h > > diff --git a/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h > b/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h > new file mode 100644 > index ..57d0d8f489c4 > --- /dev/null > +++ b/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h > @@ -0,0 +1,288 @@ > +// SPDX-License-Identifier: BSD-1-Clause I've told you this in our personal converation before, but I'll happily repeat it here for a broader audience: The original GitHub source says * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE * DISCLAIMED. which additionally disclaims warranty for "NON-INFRINGEMENT", which is not in BSD-1-Clause text you added in the previous commit. I regard this as a substantive change of the licensing conditions according to the SPDX License List Matching Guidelines [s] and rather use the original license headers here as long as there is no SPDX license identifier for it. Same probably also applies to the other source files. [s]: https://spdx.org/spdx-license-list/matching-guidelines - Roland > +/* > + * Copyright (c) 2006, Atmel Corporation > + */ > +#ifndef __AT91_DDRSDRC_H__ > +#define __AT91_DDRSDRC_H__ > + > +/ Register offset in AT91S_HDDRSDRC2 structure ***/ > +#define AT91C_HDDRSDRC2_MR 0x00/* Mode Register */ > +#define AT91C_HDDRSDRC2_RTR 0x04/* Refresh Timer Register */ > +#define AT91C_HDDRSDRC2_CR 0x08/* Configuration Register */ > +#define AT91C_HDDRSDRC2_T0PR 0x0C/* Timing Parameter 0 Register > */ > +#define AT91C_HDDRSDRC2_T1PR 0x10/* Timing Parameter 1 Register > */ > +#define AT91C_HDDRSDRC2_T2PR 0x14/* Timing Parameter 2 Register > */ > +#define AT91C_HDDRSDRC2_T3PR 0x18/* Timing Parameter 3 Register > */ > +#define AT91C_HDDRSDRC2_LPR 0x1C/* Low-power Register */ > +#define AT91C_HDDRSDRC2_MDR 0x20/* Memory Device Register */ > +#define AT91C_HDDRSDRC2_DLL 0x24/* DLL Information Register */ > +#define AT91C_HDDRSDRC2_HS 0x2C/* High Speed Register */ > + > +/* below items defined for sama5d3x */ > +#define AT91C_MPDDRC_LPDDR2_HS 0x24/* MPDDRC LPDDR2 High > Speed Register */ > +#define AT91C_MPDDRC_LPDDR2_LPR 0x28/* MPDDRC LPDDR2 > Low-power Register */ > +#define AT91C_MPDDRC_LPDDR2_CAL_MR4 0x2C/* MPDDRC LPDDR2 > Calibration and MR4 Register */ > +#define AT91C_MPDDRC_LPDDR2_TIM_CAL 0x30/* MPDDRC LPDDR2 Timing > Calibration Register */ > +#define AT91C_MPDDRC_IO_CALIBR 0x34/* MPDDRC IO > Calibration */ > +#define AT91C_MPDDRC_OCMS 0x38/* MPDDRC OCMS Register > */ > +#define AT91C_MPDDRC_OCMS_KEY1 0x3C/* MPDDRC OCMS KEY1 > Register */ > +#define AT91C_MPDDRC_OCMS_KEY2 0x40/* MPDDRC OCMS KEY2 > Register */ > +/* 0x54 ~ 0x70 Reserved */ > +#define AT91C_MPDDRC_DLL_MOR0x74/* MPDDRC DLL Master > Offset Register */ > +#define AT91C_MPDDRC_DLL_SOR0x78/* MPDDRC DLL Slave > Offset Register */ > +#define AT91C_MPDDRC_DLL_MSR0x7C/* MPDDRC DLL Master > Status Register */ > +#define AT91C_MPDDRC_DLL_S0SR 0x80/* MPDDRC DLL Slave 0 > Status Register */ > +#define AT91C_MPDDRC_DLL_S1SR 0x84/* MPDDRC DLL Slave 1 > Status Register */ > + > +#define AT91C_MPDDRC_RD_DATA_PATH0x5C/* MPDDRC Read Data Path */ > + > +/* 0x94 ~ 0xE0 Reserved */ > +#define AT91C_HDDRSDRC2_WPCR 0xE4/* Write Protect Mode Register > */ > +#define AT91C_HDDRSDRC2_WPSR 0xE8/* Write Protect Status > Register */ > + > +/* HDDRSDRC2_MR : (HDDRSDRC2 Offset: 0x0) Mode Register */ > +#define AT91C_DDRC2_MODE (0x7UL << 0) > +#define AT91C_DDRC2_MODE_NORMAL_CMD (0x0UL) > +#define AT91C_DDRC2_MODE_NOP_CMD(0x1UL) > +#define AT91C_DDRC2_MODE_PRCGALL_CMD(0x2UL) > +#define AT91C_DDRC2_MODE_LMR_CMD(0x3UL) > +#define AT91C_DDRC2_MODE_RFSH_CMD (0x4UL) > +
Re: [PATCH v3 01/15] LICENSES: add BSD-1-Clause license
On Mon, Apr 01, 2019 at 12:18:09PM +0200, Ahmad Fatoum wrote: > Incoming sama5d3 bootstrap code has been ported from the at91bootstrap > project and is licensed under a 1-clause BSD license. To remove > boilerplate legal text there, place the license at a fixed location > and only note SPDX-License-Identifier and Copyright in the source files. > > Signed-off-by: Ahmad Fatoum > --- > LICENSES/preferred/BSD-1-Clause | 15 +++ > 1 file changed, 15 insertions(+) > create mode 100644 LICENSES/preferred/BSD-1-Clause > > diff --git a/LICENSES/preferred/BSD-1-Clause b/LICENSES/preferred/BSD-1-Clause > new file mode 100644 > index ..f80acdf3b15f > --- /dev/null > +++ b/LICENSES/preferred/BSD-1-Clause > @@ -0,0 +1,15 @@ > +Valid-License-Identifier: BSD-1-Clause > +SPDX-URL: https://spdx.org/licenses/BSD-1-Clause.html > +Usage-Guide: > + To use the BSD 1-clause License put the following SPDX tag/value pair > + into a comment according to the placement guidelines in the licensing > + rules documentation: > +SPDX-License-Identifier: BSD-1-Clause > +License-Text: > + > +Copyright (c) All rights reserved. > + > +Redistribution and use in source and binary forms, with or without > modification, are permitted provided that the following conditions are met: > + > +1. Redistributions of source code must retain the above copyright notice, > this list of conditions and the following disclaimer. > +THIS SOFTWARE IS PROVIDED BY Berkeley Software Design, Inc. "AS IS" AND ANY > EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED > WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE > DISCLAIMED. IN NO EVENT SHALL Berkeley Software Design, Inc. BE LIABLE FOR > ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL > DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR > SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER > CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, > OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE > OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. I would replace "Berkeley Software Design, Inc." with "the copyright holder" here. In the link given in the SPDX-URL field these parts are marked as placeholders in red text, which does not transfer well over to plain text. :) I would also hard-line-wrap the text to 80 characters to make it better readable, but I guess that is a matter of personal preference. - Roland -- Roland Hieber | r.hie...@pengutronix.de | Pengutronix e.K. | https://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim | Phone: +49-5121-206917-5086 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH] clk: at91: fix compilation errors in sama5d2.c
sama5d2 was added along with the update to the upstream
device tree bindings, but wasn't wired in anywhere.
To prepare for usage in future sama5d2 support, fix
compilation errors related to absence of locks and
unavailability of audio/i2s clock/pll handling.
Signed-off-by: Ahmad Fatoum
---
drivers/clk/at91/sama5d2.c | 52 +-
1 file changed, 6 insertions(+), 46 deletions(-)
diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c
index dc15f7d9cbf3..7627c584ac08 100644
--- a/drivers/clk/at91/sama5d2.c
+++ b/drivers/clk/at91/sama5d2.c
@@ -84,8 +84,6 @@ static const struct {
{ .n = "trng_clk",.id = 47, .r = { .min = 0, .max = 8300 }, },
{ .n = "pdmic_clk", .id = 48, .r = { .min = 0, .max = 8300 }, },
{ .n = "securam_clk", .id = 51, },
- { .n = "i2s0_clk",.id = 54, .r = { .min = 0, .max = 8300 }, },
- { .n = "i2s1_clk",.id = 55, .r = { .min = 0, .max = 8300 }, },
{ .n = "can0_clk",.id = 56, .r = { .min = 0, .max = 8300 }, },
{ .n = "can1_clk",.id = 57, .r = { .min = 0, .max = 8300 }, },
{ .n = "classd_clk", .id = 59, .r = { .min = 0, .max = 8300 }, },
@@ -123,8 +121,6 @@ static const struct {
{ .n = "pwm_gclk",.id = 38, .r = { .min = 0, .max = 8300 }, },
{ .n = "isc_gclk",.id = 46, },
{ .n = "pdmic_gclk", .id = 48, },
- { .n = "i2s0_gclk", .id = 54, .pll = true },
- { .n = "i2s1_gclk", .id = 55, .pll = true },
{ .n = "can0_gclk", .id = 56, .r = { .min = 0, .max = 8000 }, },
{ .n = "can1_gclk", .id = 57, .r = { .min = 0, .max = 8000 }, },
{ .n = "classd_gclk", .id = 59, .r = { .min = 0, .max = 1 },
@@ -136,7 +132,7 @@ static void __init sama5d2_pmc_setup(struct device_node *np)
struct clk_range range = CLK_RANGE(0, 0);
const char *slck_name, *mainxtal_name;
struct pmc_data *sama5d2_pmc;
- const char *parent_names[6];
+ const char *parent_names[5];
struct regmap *regmap, *regmap_sfr;
struct clk *hw;
int i;
@@ -157,7 +153,7 @@ static void __init sama5d2_pmc_setup(struct device_node *np)
if (IS_ERR(regmap))
return;
- sama5d2_pmc = pmc_data_allocate(PMC_I2S1_MUX + 1,
+ sama5d2_pmc = pmc_data_allocate(PMC_MCK2 + 1,
nck(sama5d2_systemck),
nck(sama5d2_periph32ck),
nck(sama5d2_gck));
@@ -193,21 +189,6 @@ static void __init sama5d2_pmc_setup(struct device_node
*np)
if (IS_ERR(hw))
goto err_free;
- hw = at91_clk_register_audio_pll_frac(regmap, "audiopll_fracck",
- "mainck");
- if (IS_ERR(hw))
- goto err_free;
-
- hw = at91_clk_register_audio_pll_pad(regmap, "audiopll_padck",
-"audiopll_fracck");
- if (IS_ERR(hw))
- goto err_free;
-
- hw = at91_clk_register_audio_pll_pmc(regmap, "audiopll_pmcck",
-"audiopll_fracck");
- if (IS_ERR(hw))
- goto err_free;
-
regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr");
if (IS_ERR(regmap_sfr))
regmap_sfr = NULL;
@@ -270,7 +251,7 @@ static void __init sama5d2_pmc_setup(struct device_node *np)
}
for (i = 0; i < ARRAY_SIZE(sama5d2_periphck); i++) {
- hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
+ hw = at91_clk_register_sam9x5_peripheral(regmap,
sama5d2_periphck[i].n,
"masterck",
sama5d2_periphck[i].id,
@@ -282,7 +263,7 @@ static void __init sama5d2_pmc_setup(struct device_node *np)
}
for (i = 0; i < ARRAY_SIZE(sama5d2_periph32ck); i++) {
- hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
+ hw = at91_clk_register_sam9x5_peripheral(regmap,
sama5d2_periph32ck[i].n,
"h32mxck",
sama5d2_periph32ck[i].id,
@@ -298,11 +279,10 @@ static void __init sama5d2_pmc_setup(struct device_node
*np)
parent_names[2] = "plladivck";
parent_names[3] = "utmick";
parent_names[4] = "mck";
- parent_names[5] = "audiopll_pmcck";
for (i = 0; i < ARRAY_SIZE(sama5d2_gck); i++) {
- hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
+ hw = at91_clk_register_generated(regmap,
sama5d2_gck[i].n,
-
[PATCH v3 13/15] ARM: at91: microchip-ksz9477-evb: implement first stage
This imports the low level init code from at91bootstrap
https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/board/sama5d3_xplained/sama5d3_xplained.c
Signed-off-by: Ahmad Fatoum
---
.../boards/microchip-ksz9477-evb/lowlevel.c | 208 +-
arch/arm/mach-at91/Kconfig| 2 +
arch/arm/mach-at91/include/mach/at91_pmc.h| 8 +
arch/arm/mach-at91/include/mach/sama5d3.h | 1 +
images/Makefile.at91 | 5 +
5 files changed, 220 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c
b/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c
index 4293f8aaa57d..cf44021bdfb7 100644
--- a/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c
+++ b/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c
@@ -1,7 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0-only AND BSD-1-Clause
/*
+ * Copyright (c) 2014, Atmel Corporation
* Copyright (C) 2018 Ahmad Fatoum, Pengutronix
*
- * Under GPLv2
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include
@@ -10,18 +22,206 @@
#include
#include
-#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* PCK = 528MHz, MCK = 132MHz */
+#define MASTER_CLOCK 13200
+
+#define PMC_BASE IOMEM(SAMA5D3_BASE_PMC)
+#define sama5d3_pmc_enable_periph_clock(clk) \
+ at91_pmc_enable_periph_clock(PMC_BASE, clk)
+
+#define BAUDRATE(mck, baud) \
+ ((mck) * 10) / ((baud) * 16)) % 10) >= 5) ? \
+ (mck / (baud * 16) + 1) : ((mck) / (baud * 16)))
+
+
+static void configure_periph_a_piob_pin(unsigned int pin)
+{
+ void __iomem *pio = IOMEM(SAMA5D3_BASE_PIOB);
+ u32 mask = pin_to_mask(pin);
+
+ at91_mux_disable_interrupt(pio, mask);
+ at91_mux_set_pullup(pio, mask, 0);
+ at91_mux_pio3_set_pulldown(pio, mask, 0);
+
+ at91_mux_pio3_set_A_periph(pio, mask);
+
+ at91_mux_gpio_disable(pio, mask);
+}
+
+static noinline void dbgu_init(void)
+{
+ sama5d3_pmc_enable_periph_clock(SAMA5D3_ID_PIOB);
+
+ configure_periph_a_piob_pin(AT91_PIN_PB30);
+ configure_periph_a_piob_pin(AT91_PIN_PB31);
+
+ sama5d3_pmc_enable_periph_clock(SAMA5D3_ID_DBGU);
+ at91_dbgu_setup_ll(AT91_BASE_DBGU1, BAUDRATE(MASTER_CLOCK, 115200));
+
+ putc_ll('>');
+}
+
+static void ddramc_reg_config(struct at91_ddramc_register *ddramc_config)
+{
+ ddramc_config->mdr = (AT91C_DDRC2_DBW_32_BITS
+ | AT91C_DDRC2_MD_DDR2_SDRAM);
+
+ ddramc_config->cr = (AT91C_DDRC2_NC_DDR10_SDR9
+ | AT91C_DDRC2_NR_13
+ | AT91C_DDRC2_CAS_3
+ | AT91C_DDRC2_DISABLE_RESET_DLL
+ | AT91C_DDRC2_ENABLE_DLL
+ | AT91C_DDRC2_ENRDM_ENABLE
+ | AT91C_DDRC2_NB_BANKS_8
+ | AT91C_DDRC2_NDQS_DISABLED
+ | AT91C_DDRC2_DECOD_INTERLEAVED
+ | AT91C_DDRC2_UNAL_SUPPORTED);
+
+ /*
+* The DDR2-SDRAM device requires a refresh every 15.625 us or 7.81 us.
+* With a 133 MHz frequency, the refresh timer count register must to be
+* set with (15.625 x 133 MHz) ~ 2084 i.e. 0x824
+* or (7.81 x 133 MHz) ~ 1039 i.e. 0x40F.
+*/
+ ddramc_config->rtr = 0x40F; /* Refresh timer: 7.812us */
+
+ /* One clock cycle @ 133 MHz = 7.5 ns */
+ ddramc_config->t0pr = (AT91C_DDRC2_TRAS_(6) /* 6 * 7.5 = 45 ns */
+ | AT91C_DDRC2_TRCD_(2) /* 2 * 7.5 = 22.5 ns */
+ | AT91C_DDRC2_TWR_(2) /* 2 * 7.5 = 15 ns */
+ | AT91C_DDRC2_TRC_(8) /* 8 * 7.5 = 75 ns */
+ | AT91C_DDRC2_TRP_(2) /* 2 * 7.5 = 15 ns */
+ | AT91C_DDRC2_TRRD_(2) /* 2 * 7.5 = 15 ns */
+ | AT91C_DDRC2_TWTR_(2) /* 2 clock cycles min */
+ | AT91C_DDRC2_TMRD_(2));/* 2 clock cycles */
+
+ ddramc_config->t1pr = (AT91C_DDRC2_TXP_(2) /* 2 clock cycles */
+
[PATCH v3 04/15] ARM: at91: replace at91sam9_ddrsdr.h with at91bootstrap's at91_ddrsdrc.h
Instead of adding missing definitions to the existing at91sam9_ddrsdr.h
and adapting the incoming DDRAM initialization code from at91bootstrap,
just replace the lightly used existing header with:
https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/include/arch/at91_ddrsdrc.h
For easier comprehension, the replacement is done in three steps:
This last step copies the memory size querying functions from at91sam9_ddrsdr.h
to at91_ddrsdrc.h, then deletes it and fixes all references.
Signed-off-by: Ahmad Fatoum
---
arch/arm/boards/at91sam9m10g45ek/lowlevel.c | 2 +-
arch/arm/boards/at91sam9m10ihd/lowlevel.c | 2 +-
arch/arm/boards/at91sam9n12ek/lowlevel.c | 2 +-
arch/arm/boards/at91sam9x5ek/lowlevel.c | 2 +-
arch/arm/boards/pm9g45/lowlevel.c | 3 +-
arch/arm/boards/sama5d3_xplained/lowlevel.c | 2 +-
arch/arm/boards/sama5d3xek/lowlevel.c | 2 +-
arch/arm/boards/sama5d4_xplained/lowlevel.c | 2 +-
arch/arm/boards/sama5d4ek/lowlevel.c | 2 +-
arch/arm/mach-at91/at91sam9g45_devices.c | 2 +-
arch/arm/mach-at91/at91sam9g45_reset.S| 2 +-
arch/arm/mach-at91/at91sam9n12_devices.c | 2 +-
arch/arm/mach-at91/at91sam9x5_devices.c | 2 +-
.../arm/mach-at91/include/mach/at91_ddrsdrc.h | 44 +++
arch/arm/mach-at91/sama5d3_devices.c | 2 +-
arch/arm/mach-at91/sama5d4_devices.c | 2 +-
16 files changed, 60 insertions(+), 15 deletions(-)
diff --git a/arch/arm/boards/at91sam9m10g45ek/lowlevel.c
b/arch/arm/boards/at91sam9m10g45ek/lowlevel.c
index d5deedfc37b5..add97c641998 100644
--- a/arch/arm/boards/at91sam9m10g45ek/lowlevel.c
+++ b/arch/arm/boards/at91sam9m10g45ek/lowlevel.c
@@ -11,7 +11,7 @@
#include
#include
-#include
+#include
void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1,
uint32_t r2)
{
diff --git a/arch/arm/boards/at91sam9m10ihd/lowlevel.c
b/arch/arm/boards/at91sam9m10ihd/lowlevel.c
index 24d41cfa70ea..92988d1945e8 100644
--- a/arch/arm/boards/at91sam9m10ihd/lowlevel.c
+++ b/arch/arm/boards/at91sam9m10ihd/lowlevel.c
@@ -10,7 +10,7 @@
#include
#include
-#include
+#include
#include
#include
diff --git a/arch/arm/boards/at91sam9n12ek/lowlevel.c
b/arch/arm/boards/at91sam9n12ek/lowlevel.c
index 094fd941bc8c..9f460f71a896 100644
--- a/arch/arm/boards/at91sam9n12ek/lowlevel.c
+++ b/arch/arm/boards/at91sam9n12ek/lowlevel.c
@@ -10,7 +10,7 @@
#include
#include
-#include
+#include
#include
void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1,
uint32_t r2)
diff --git a/arch/arm/boards/at91sam9x5ek/lowlevel.c
b/arch/arm/boards/at91sam9x5ek/lowlevel.c
index 14c239408d6a..d87c0a99f424 100644
--- a/arch/arm/boards/at91sam9x5ek/lowlevel.c
+++ b/arch/arm/boards/at91sam9x5ek/lowlevel.c
@@ -1,6 +1,6 @@
#include
#include
-#include
+#include
#include
#include
#include
diff --git a/arch/arm/boards/pm9g45/lowlevel.c
b/arch/arm/boards/pm9g45/lowlevel.c
index fbf2b655c708..ec2ab7262245 100644
--- a/arch/arm/boards/pm9g45/lowlevel.c
+++ b/arch/arm/boards/pm9g45/lowlevel.c
@@ -10,7 +10,8 @@
#include
#include
-#include
+#include
+
#include
void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1,
uint32_t r2)
diff --git a/arch/arm/boards/sama5d3_xplained/lowlevel.c
b/arch/arm/boards/sama5d3_xplained/lowlevel.c
index 31c176a3a4c2..37384a160651 100644
--- a/arch/arm/boards/sama5d3_xplained/lowlevel.c
+++ b/arch/arm/boards/sama5d3_xplained/lowlevel.c
@@ -10,7 +10,7 @@
#include
#include
-#include
+#include
#include
void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1,
uint32_t r2)
diff --git a/arch/arm/boards/sama5d3xek/lowlevel.c
b/arch/arm/boards/sama5d3xek/lowlevel.c
index 31c176a3a4c2..37384a160651 100644
--- a/arch/arm/boards/sama5d3xek/lowlevel.c
+++ b/arch/arm/boards/sama5d3xek/lowlevel.c
@@ -10,7 +10,7 @@
#include
#include
-#include
+#include
#include
void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1,
uint32_t r2)
diff --git a/arch/arm/boards/sama5d4_xplained/lowlevel.c
b/arch/arm/boards/sama5d4_xplained/lowlevel.c
index 47cadfe6750c..89f0b8202eb1 100644
--- a/arch/arm/boards/sama5d4_xplained/lowlevel.c
+++ b/arch/arm/boards/sama5d4_xplained/lowlevel.c
@@ -10,7 +10,7 @@
#include
#include
-#include
+#include
#include
void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1,
uint32_t r2)
diff --git a/arch/arm/boards/sama5d4ek/lowlevel.c
b/arch/arm/boards/sama5d4ek/lowlevel.c
index 47cadfe6750c..89f0b8202eb1 100644
--- a/arch/arm/boards/sama5d4ek/lowlevel.c
+++ b/arch/arm/boards/sama5d4ek/lowlevel.c
@@ -10,7 +10,7 @@
#include
#include
-#include
+#include
#include
void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1,
uint32_t r2)
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c
b/arch/arm/mach-at91/at91sam9g45_devices.c
index df0
[PATCH v3 07/15] ARM: at91: import early_udelay from at91bootstrap
For use by the incoming at91bootstrap DDRAMC initialization code,
this commit provides an early_udelay function usable in PBL imported from
https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/driver/at91_pit.c
Signed-off-by: Ahmad Fatoum
---
arch/arm/mach-at91/Makefile | 1 +
arch/arm/mach-at91/early_udelay.c | 56 +++
arch/arm/mach-at91/include/mach/at91_pmc_ll.h | 13 -
.../arm/mach-at91/include/mach/early_udelay.h | 14 +
4 files changed, 83 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/mach-at91/early_udelay.c
create mode 100644 arch/arm/mach-at91/include/mach/early_udelay.h
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 91b06c085107..25a7916c34e4 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -1,5 +1,6 @@
obj-y += setup.o
pbl-y += at91_pmc_ll.o
+pbl-$(CONFIG_CLOCKSOURCE_ATMEL_PIT) += early_udelay.o
ifeq ($(CONFIG_COMMON_CLK_OF_PROVIDER),)
obj-y += clock.o
diff --git a/arch/arm/mach-at91/early_udelay.c
b/arch/arm/mach-at91/early_udelay.c
new file mode 100644
index ..632e797bebe9
--- /dev/null
+++ b/arch/arm/mach-at91/early_udelay.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: BSD-1-Clause
+/*
+ * Copyright (c) 2012, Atmel Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+static unsigned int master_clock;
+static void __iomem *pmc, *pit;
+static bool has_h32mxdiv;
+
+/* Because the below statement is used in the function:
+ * ((MASTER_CLOCK >> 10) * usec) is used,
+ * to our 32-bit system. the argu "usec" maximum value is:
+ * supposed "MASTER_CLOCK" is 132M.
+ * 13200 / 1024 = 128906
+ * (0x) / 128906 = 33318.
+ * So the maximum delay time is 33318 us.
+ */
+/* requires PIT to be initialized, but not the clocksource framework */
+void early_udelay(unsigned int usec)
+{
+ unsigned int delay;
+ unsigned int current;
+ unsigned int base = readl(pit + AT91_PIT_PIIR);
+
+ if (has_h32mxdiv)
+ master_clock /= 2;
+
+ delay = ((master_clock >> 10) * usec) >> 14;
+
+ do {
+ current = readl(pit + AT91_PIT_PIIR);
+ current -= base;
+ } while (current < delay);
+}
+
+void early_udelay_init(void __iomem *pmc_base,
+ void __iomem *pit_base,
+ unsigned int clock,
+ unsigned int master_clock_rate,
+ unsigned int flags)
+{
+ master_clock = master_clock_rate;
+ pmc = pmc_base;
+ pit = pit_base;
+ has_h32mxdiv = at91_pmc_check_mck_h32mxdiv(pmc, flags);
+
+ writel(AT91_PIT_PIV | AT91_PIT_PITEN, pit + AT91_PIT_MR);
+
+ at91_pmc_enable_periph_clock(pmc_base, clock);
+}
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc_ll.h
b/arch/arm/mach-at91/include/mach/at91_pmc_ll.h
index eda40e8e12e7..e3d3e3ad59db 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc_ll.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc_ll.h
@@ -13,6 +13,7 @@
#define AT91_PMC_LL_FLAG_SAM9X5_PMC(1 << 0)
#define AT91_PMC_LL_FLAG_MEASURE_XTAL (1 << 1)
#define AT91_PMC_LL_FLAG_DISABLE_RC(1 << 2)
+#define AT91_PMC_LL_FLAG_H32MXDIV (1 << 3)
#define AT91_PMC_LL_AT91RM9200 (0)
#define AT91_PMC_LL_AT91SAM9260(0)
@@ -27,7 +28,8 @@
AT91_PMC_LL_FLAG_MEASURE_XTAL)
#define AT91_PMC_LL_SAMA5D3(AT91_PMC_LL_FLAG_SAM9X5_PMC | \
AT91_PMC_LL_FLAG_DISABLE_RC)
-#define AT91_PMC_LL_SAMA5D4(AT91_PMC_LL_FLAG_SAM9X5_PMC)
+#define AT91_PMC_LL_SAMA5D4(AT91_PMC_LL_FLAG_SAM9X5_PMC | \
+AT91_PMC_LL_FLAG_H32MXDIV)
void at91_pmc_init(void __iomem *pmc_base, unsigned int flags);
void at91_pmc_cfg_mck(void __iomem *pmc_base, u32 pmc_mckr, unsigned int
flags);
@@ -75,4 +77,13 @@ static inline int at91_pmc_sam9x5_enable_periph_clock(void
__iomem *pmc_base,
return 0;
}
+static inline bool at91_pmc_check_mck_h32mxdiv(void __iomem *pmc_base,
+ unsigned flags)
+{
+ if (flags & AT91_PMC_LL_FLAG_H32MXDIV)
+ return readl(pmc_base + AT91_PMC_MCKR) & AT91_PMC_H32MXDIV;
+
+ return false;
+}
+
#endif
diff --git a/arch/arm/mach-at91/include/mach/early_udelay.h
b/arch/arm/mach-at91/include/mach/early_udelay.h
new file mode 100644
index ..1c1b0123fee8
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/early_udelay.h
@@ -0,0 +1,14 @@
+#ifndef __EARLY_UDELAY_H__
+#define __EARLY_UDELAY_H__
+
+#include
+
+/* requires PIT to be initialized, but not the clocksource framework */
+void early_udelay(unsigned int usec);
+void early_udelay_init(void __iomem *pmc_base,
+ void __iomem *pit_base,
+ unsigned int clock,
+ unsigned int master_clock_rate,
+ unsigned int flags);
+
+#endif
--
[PATCH v3 01/15] LICENSES: add BSD-1-Clause license
Incoming sama5d3 bootstrap code has been ported from the at91bootstrap project and is licensed under a 1-clause BSD license. To remove boilerplate legal text there, place the license at a fixed location and only note SPDX-License-Identifier and Copyright in the source files. Signed-off-by: Ahmad Fatoum --- LICENSES/preferred/BSD-1-Clause | 15 +++ 1 file changed, 15 insertions(+) create mode 100644 LICENSES/preferred/BSD-1-Clause diff --git a/LICENSES/preferred/BSD-1-Clause b/LICENSES/preferred/BSD-1-Clause new file mode 100644 index ..f80acdf3b15f --- /dev/null +++ b/LICENSES/preferred/BSD-1-Clause @@ -0,0 +1,15 @@ +Valid-License-Identifier: BSD-1-Clause +SPDX-URL: https://spdx.org/licenses/BSD-1-Clause.html +Usage-Guide: + To use the BSD 1-clause License put the following SPDX tag/value pair + into a comment according to the placement guidelines in the licensing + rules documentation: +SPDX-License-Identifier: BSD-1-Clause +License-Text: + +Copyright (c) All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. +THIS SOFTWARE IS PROVIDED BY Berkeley Software Design, Inc. "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Berkeley Software Design, Inc. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- 2.20.1 ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH v3 14/15] ARM: at91: microchip-ksz9477: provide board code fallback
The newly added device tree based first stage fails to load the second
stage from MMC, which might be in relation to a preceding atmel_mci
"command/data timeout" message.
Due to this and because it's not clear yet how viable it's to use the device
tree for the size-constrained first stage anyway, make CONFIG_OFDEVICE
configurable and provide a legacy board code based fallback whenever it's
unselected. The resulting image is 48K big with PBL_CONSOLE compared to
72K for the device tree based version without PBL_CONSOLE.
If barebox can be shrunk further and the device tree support in the
first stage was fixed, this commit could be reverted for full device
tree goodness.
The board code is a stripped down version of the sama5d3_xplained board's.
Signed-off-by: Ahmad Fatoum
---
.../arm/boards/microchip-ksz9477-evb/Makefile | 3 +
arch/arm/boards/microchip-ksz9477-evb/board.c | 127 ++
.../boards/microchip-ksz9477-evb/lowlevel.c | 3 +-
...rochip_ksz9477_evb_bootstrap_mmc_defconfig | 24
arch/arm/mach-at91/Kconfig| 14 +-
5 files changed, 167 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/boards/microchip-ksz9477-evb/board.c
create mode 100644
arch/arm/configs/microchip_ksz9477_evb_bootstrap_mmc_defconfig
diff --git a/arch/arm/boards/microchip-ksz9477-evb/Makefile
b/arch/arm/boards/microchip-ksz9477-evb/Makefile
index b08c4a93ca27..8d0379a3f59f 100644
--- a/arch/arm/boards/microchip-ksz9477-evb/Makefile
+++ b/arch/arm/boards/microchip-ksz9477-evb/Makefile
@@ -1 +1,4 @@
lwl-y += lowlevel.o
+ifeq ($(CONFIG_MACH_MICROCHIP_KSZ9477_EVB_DT),)
+obj-y += board.o
+endif
diff --git a/arch/arm/boards/microchip-ksz9477-evb/board.c
b/arch/arm/boards/microchip-ksz9477-evb/board.c
new file mode 100644
index ..455b9aca3ab0
--- /dev/null
+++ b/arch/arm/boards/microchip-ksz9477-evb/board.c
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2014 Bo Shen
+ */
+
+#include
+#include
+#include
+
+#if defined(CONFIG_NAND_ATMEL)
+static struct atmel_nand_data nand_pdata = {
+ .ale= 21,
+ .cle= 22,
+ .det_pin= -EINVAL,
+ .rdy_pin= -EINVAL,
+ .enable_pin = -EINVAL,
+ .ecc_mode = NAND_ECC_HW,
+ .has_pmecc = 1,
+ .pmecc_sector_size = 512,
+ .pmecc_corr_cap = 4,
+ .bus_width_16 = 1,
+ .on_flash_bbt = 1,
+};
+
+static struct sam9_smc_config sama5d3_xplained_nand_smc_config = {
+ .ncs_read_setup = 1,
+ .nrd_setup = 2,
+ .ncs_write_setup= 1,
+ .nwe_setup = 2,
+
+ .ncs_read_pulse = 5,
+ .nrd_pulse = 3,
+ .ncs_write_pulse= 5,
+ .nwe_pulse = 3,
+
+ .read_cycle = 8,
+ .write_cycle= 8,
+
+ .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_EXNWMODE_DISABLE,
+ .tdf_cycles = 3,
+
+ .tclr = 3,
+ .tadl = 10,
+ .tar= 3,
+ .ocms = 0,
+ .trr= 4,
+ .twb= 5,
+ .rbnsel = 3,
+ .nfsel = 1
+};
+
+static void ek_add_device_nand(void)
+{
+ struct clk *clk = clk_get(NULL, "smc_clk");
+
+ clk_enable(clk);
+
+ /* setup bus-width (8 or 16) */
+ if (nand_pdata.bus_width_16)
+ sama5d3_xplained_nand_smc_config.mode |= AT91_SMC_DBW_16;
+ else
+ sama5d3_xplained_nand_smc_config.mode |= AT91_SMC_DBW_8;
+
+ /* configure chip-select 3 (NAND) */
+ sama5_smc_configure(0, 3, &sama5d3_xplained_nand_smc_config);
+
+ at91_add_device_nand(&nand_pdata);
+}
+#else
+static void ek_add_device_nand(void) {}
+#endif
+
+#if defined(CONFIG_MCI_ATMEL)
+/*
+ * MCI (SD/MMC)
+ */
+static struct atmel_mci_platform_data mci0_data = {
+ .bus_width = 8,
+ .detect_pin = AT91_PIN_PE0,
+ .wp_pin = -EINVAL,
+};
+
+static void ek_add_device_mci(void)
+{
+ /* MMC0 */
+ at91_add_device_mci(0, &mci0_data);
+}
+#else
+static void ek_add_device_mci(void) {}
+#endif
+
+static int sama5d3_xplained_mem_init(void)
+{
+ at91_add_device_sdram(0);
+
+ return 0;
+}
+mem_initcall(sama5d3_xplained_mem_init);
+
+static const struct devfs_partition sama5d3_xplained_nand0_partitions[] = {
+ {
+ .offset = 0x0,
+ .size = SZ_256K,
+ .flags = DEVFS_PARTITION_FIXED,
+ .name = "at91bootstrap_raw",
+ .bbname = "at91bootstrap",
+ }, {
+ .offset = DEVFS_PARTITION_APPEND, /* 256 KiB */
+ .size = SZ_1M,
+ .flags = DEVFS_PARTITION_FIXED,
+ .name = "self_raw",
+ .bbname = "self0",
+ }, {
+
[PATCH v3 05/15] ARM: at91: watchdog: implement at91_wdt_disable
Low level init code might want to disable the watchdog in PBL.
Provide a helper to do so.
Signed-off-by: Ahmad Fatoum
---
arch/arm/mach-at91/include/mach/at91_wdt.h | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/mach-at91/include/mach/at91_wdt.h
b/arch/arm/mach-at91/include/mach/at91_wdt.h
index 36d37b9d2d64..d295d35d1b5c 100644
--- a/arch/arm/mach-at91/include/mach/at91_wdt.h
+++ b/arch/arm/mach-at91/include/mach/at91_wdt.h
@@ -35,4 +35,20 @@
#defineAT91_WDT_WDUNF (1 << 0)/*
Watchdog Underflow */
#defineAT91_WDT_WDERR (1 << 1)/*
Watchdog Error */
+#ifndef __ASSEMBLY__
+// SPDX-License-Identifier: BSD-1-Clause
+/*
+ * Copyright (c) 2006, Atmel Corporation
+ */
+
+#include
+
+static inline void at91_wdt_disable(void __iomem *wdt_base)
+{
+ u32 reg = readl(wdt_base + AT91_WDT_MR);
+ reg |= AT91_WDT_WDDIS;
+ writel(reg, wdt_base + AT91_WDT_MR);
+}
+
+#endif /* __ASSEMBLY__ */
#endif
--
2.20.1
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[PATCH v3 02/15] ARM: at91: import at91bootstrap's at91_ddrsdrc.h
Instead of adding missing definitions to the existing at91sam9_ddrsdr.h and adapting the incoming DDRAM initialization code from at91bootstrap, just replace the lightly used existing header with: https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/include/arch/at91_ddrsdrc.h For easier comprehension, the replacement is done in three steps: Here the header is imported. Signed-off-by: Ahmad Fatoum --- .../arm/mach-at91/include/mach/at91_ddrsdrc.h | 288 ++ 1 file changed, 288 insertions(+) create mode 100644 arch/arm/mach-at91/include/mach/at91_ddrsdrc.h diff --git a/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h b/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h new file mode 100644 index ..57d0d8f489c4 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h @@ -0,0 +1,288 @@ +// SPDX-License-Identifier: BSD-1-Clause +/* + * Copyright (c) 2006, Atmel Corporation + */ +#ifndef __AT91_DDRSDRC_H__ +#define __AT91_DDRSDRC_H__ + +/ Register offset in AT91S_HDDRSDRC2 structure ***/ +#define AT91C_HDDRSDRC2_MR 0x00/* Mode Register */ +#define AT91C_HDDRSDRC2_RTR0x04/* Refresh Timer Register */ +#define AT91C_HDDRSDRC2_CR 0x08/* Configuration Register */ +#define AT91C_HDDRSDRC2_T0PR 0x0C/* Timing Parameter 0 Register */ +#define AT91C_HDDRSDRC2_T1PR 0x10/* Timing Parameter 1 Register */ +#define AT91C_HDDRSDRC2_T2PR 0x14/* Timing Parameter 2 Register */ +#define AT91C_HDDRSDRC2_T3PR 0x18/* Timing Parameter 3 Register */ +#define AT91C_HDDRSDRC2_LPR0x1C/* Low-power Register */ +#define AT91C_HDDRSDRC2_MDR0x20/* Memory Device Register */ +#define AT91C_HDDRSDRC2_DLL0x24/* DLL Information Register */ +#define AT91C_HDDRSDRC2_HS 0x2C/* High Speed Register */ + +/* below items defined for sama5d3x */ +#defineAT91C_MPDDRC_LPDDR2_HS 0x24/* MPDDRC LPDDR2 High Speed Register */ +#defineAT91C_MPDDRC_LPDDR2_LPR 0x28/* MPDDRC LPDDR2 Low-power Register */ +#defineAT91C_MPDDRC_LPDDR2_CAL_MR4 0x2C/* MPDDRC LPDDR2 Calibration and MR4 Register */ +#defineAT91C_MPDDRC_LPDDR2_TIM_CAL 0x30/* MPDDRC LPDDR2 Timing Calibration Register */ +#defineAT91C_MPDDRC_IO_CALIBR 0x34/* MPDDRC IO Calibration */ +#defineAT91C_MPDDRC_OCMS 0x38/* MPDDRC OCMS Register */ +#defineAT91C_MPDDRC_OCMS_KEY1 0x3C/* MPDDRC OCMS KEY1 Register */ +#defineAT91C_MPDDRC_OCMS_KEY2 0x40/* MPDDRC OCMS KEY2 Register */ +/* 0x54 ~ 0x70 Reserved */ +#defineAT91C_MPDDRC_DLL_MOR0x74/* MPDDRC DLL Master Offset Register */ +#defineAT91C_MPDDRC_DLL_SOR0x78/* MPDDRC DLL Slave Offset Register */ +#defineAT91C_MPDDRC_DLL_MSR0x7C/* MPDDRC DLL Master Status Register */ +#defineAT91C_MPDDRC_DLL_S0SR 0x80/* MPDDRC DLL Slave 0 Status Register */ +#defineAT91C_MPDDRC_DLL_S1SR 0x84/* MPDDRC DLL Slave 1 Status Register */ + +#define AT91C_MPDDRC_RD_DATA_PATH 0x5C/* MPDDRC Read Data Path */ + +/* 0x94 ~ 0xE0 Reserved */ +#define AT91C_HDDRSDRC2_WPCR 0xE4/* Write Protect Mode Register */ +#define AT91C_HDDRSDRC2_WPSR 0xE8/* Write Protect Status Register */ + +/* HDDRSDRC2_MR : (HDDRSDRC2 Offset: 0x0) Mode Register */ +#define AT91C_DDRC2_MODE (0x7UL << 0) +#defineAT91C_DDRC2_MODE_NORMAL_CMD (0x0UL) +#defineAT91C_DDRC2_MODE_NOP_CMD(0x1UL) +#defineAT91C_DDRC2_MODE_PRCGALL_CMD(0x2UL) +#defineAT91C_DDRC2_MODE_LMR_CMD(0x3UL) +#defineAT91C_DDRC2_MODE_RFSH_CMD (0x4UL) +#defineAT91C_DDRC2_MODE_EXT_LMR_CMD(0x5UL) +#defineAT91C_DDRC2_MODE_DEEP_CMD (0x6UL) +#defineAT91C_DDRC2_MODE_LPDDR2_CMD (0x7UL) +#define AT91C_DDRC2_MRS(value) (value << 8) + +/* HDDRSDRC2_RTR : (HDDRSDRC2 Offset: 0x4) Refresh Timer Register */ +#define AT91C_DDRC2_COUNT (0xFFFUL << 0) + +/* HDDRSDRC2_CR : (HDDRSDRC2 Offset: 0x8) Configuration Register */ +#define AT91C_DDRC2_NC (0x3UL << 0) +#defineAT91C_DDRC2_NC_DDR9_SDR8(0x0UL) +#defineAT91C_DDRC2_NC_DDR10_SDR9 (0x1UL) +#defineAT91C_DDRC2_NC_DDR11_SDR10 (0x2UL) +#defineAT91C_DDRC2_NC_DDR12_SDR11 (0x3UL) +#define AT91C_DDRC2_NR (0x3UL << 2) +#defineAT91C_DDRC2_NR_11 (0x0UL << 2) +#defineAT91C_DDRC2_NR_12 (0x1UL << 2) +#defineAT91C_DDRC2_NR_13 (0x2UL << 2) +#defineAT91C_DDRC2_NR_14 (0x3UL << 2) +#define AT91C_DDRC2_CAS(0
[PATCH v3 09/15] ARM: at91: import lowlevel dbgu UART init code from at91bootstrap
From: Ahmad Fatoum
For use in PBL, import dbgu init code from:
https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/driver/at91_usart.c
Signed-off-by: Ahmad Fatoum
---
arch/arm/mach-at91/include/mach/at91_dbgu.h | 57 -
1 file changed, 56 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-at91/include/mach/at91_dbgu.h
b/arch/arm/mach-at91/include/mach/at91_dbgu.h
index 3b5948566e52..cf35a94b7540 100644
--- a/arch/arm/mach-at91/include/mach/at91_dbgu.h
+++ b/arch/arm/mach-at91/include/mach/at91_dbgu.h
@@ -5,7 +5,7 @@
* Copyright (C) SAN People
*
* Debug Unit (DBGU) - System peripherals registers.
- * Based on AT91RM9200 datasheet revision E.
+ * Based on AT91RM9200 datasheet revision E and SAMA5D3 datasheet revision B.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -16,9 +16,37 @@
#ifndef AT91_DBGU_H
#define AT91_DBGU_H
+#include
+
#if !defined(CONFIG_ARCH_AT91X40)
#define AT91_DBGU_CR (0x00) /* Control Register */
+#defineAT91_DBGU_RSTRX (1 << 2)/* Reset
Receiver */
+#defineAT91_DBGU_RSTTX (1 << 3)/* Reset
Transmitter */
+#defineAT91_DBGU_RXEN (1 << 4)/* Receiver
Enable */
+#defineAT91_DBGU_RXDIS (1 << 5)/* Receiver
Disable */
+#defineAT91_DBGU_TXEN (1 << 6)/* Transmitter
Enable */
+#defineAT91_DBGU_TXDIS (1 << 7)/* Transmitter
Disable */
+#defineAT91_DBGU_RSTSTA(1 << 8)/* Reset Status
Bits */
#define AT91_DBGU_MR (0x04) /* Mode Register */
+#defineAT91_DBGU_NBSTOP_1BIT (0 << 12) /* 1 stop bit
*/
+#defineAT91_DBGU_NBSTOP_1_5BIT (1 << 12) /* 1.5 stop bits */
+#defineAT91_DBGU_NBSTOP_2BIT (2 << 12) /* 2 stop
bits */
+
+#defineAT91_DBGU_CHRL_5BIT (0 << 6) /* 5 bit character
length */
+#defineAT91_DBGU_CHRL_6BIT (1 << 6) /* 6 bit character
length */
+#defineAT91_DBGU_CHRL_7BIT (2 << 6) /* 7 bit character
length */
+#defineAT91_DBGU_CHRL_8BIT (3 << 6) /* 8 bit character
length */
+
+#defineAT91_DBGU_PAR_EVEN (0 << 9)/* Even Parity
*/
+#defineAT91_DBGU_PAR_ODD (1 << 9)/* Odd Parity */
+#defineAT91_DBGU_PAR_SPACE (2 << 9)/* Space: Force
Parity to 0 */
+#defineAT91_DBGU_PAR_MARK (3 << 9)/* Mark: Force
Parity to 1 */
+#defineAT91_DBGU_PAR_NONE (4 << 9)/* No Parity */
+
+#defineAT91_DBGU_CHMODE_NORMAL (0 << 14) /* Normal mode */
+#defineAT91_DBGU_CHMODE_AUTO (1 << 14) /* Automatic Echo */
+#defineAT91_DBGU_CHMODE_LOCAL (2 << 14) /* Local Loopback */
+#defineAT91_DBGU_CHMODE_REMOTE (3 << 14) /* Remote Loopback */
#define AT91_DBGU_IER (0x08) /* Interrupt Enable Register */
#defineAT91_DBGU_TXRDY (1 << 1)/*
Transmitter Ready */
#defineAT91_DBGU_TXEMPTY (1 << 9)/*
Transmitter Empty */
@@ -63,4 +91,31 @@
#defineAT91_CIDR_NVPTYP(7<< 28)/*
Nonvolatile Program Memory Type */
#defineAT91_CIDR_EXT (1<< 31)/*
Extension Flag */
+#ifndef __ASSEMBLY__
+#ifdef CONFIG_DEBUG_LL
+static inline void at91_dbgu_setup_ll(unsigned long dbgu_base, unsigned
baudrate)
+{
+ writel(~0, dbgu_base + AT91_DBGU_IDR);
+
+ writel(AT91_DBGU_RSTRX
+ | AT91_DBGU_RSTTX
+ | AT91_DBGU_RXDIS
+ | AT91_DBGU_TXDIS,
+ dbgu_base + AT91_DBGU_CR);
+
+ writel(baudrate, dbgu_base + AT91_DBGU_BRGR);
+
+ writel(AT91_DBGU_PAR_NONE
+ | AT91_DBGU_CHMODE_NORMAL
+ | AT91_DBGU_CHRL_8BIT
+ | AT91_DBGU_NBSTOP_1BIT,
+ dbgu_base + AT91_DBGU_MR);
+
+ writel(AT91_DBGU_RXEN | AT91_DBGU_TXEN, dbgu_base + AT91_DBGU_CR);
+}
+#else
+static inline void at91_dbgu_setup_ll(unsigned long dbgu_base, unsigned
baudrate) {}
+#endif
+#endif
+
#endif
--
2.20.1
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[PATCH v3 11/15] ARM: at91: microchip-ksz9477-evb: use compressed DTB
This saves about 25K, which could be useful to fit
the incoming first stage board support into the SRAM's 64K.
Signed-off-by: Ahmad Fatoum
---
arch/arm/boards/microchip-ksz9477-evb/lowlevel.c | 4 ++--
arch/arm/mach-at91/Kconfig | 1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c
b/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c
index 639958a459ad..4293f8aaa57d 100644
--- a/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c
+++ b/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c
@@ -12,7 +12,7 @@
#include
-extern char __dtb_at91_microchip_ksz9477_evb_start[];
+extern char __dtb_z_at91_microchip_ksz9477_evb_start[];
ENTRY_FUNCTION(start_sama5d3_xplained_ung8071, r0, r1, r2)
{
@@ -22,7 +22,7 @@ ENTRY_FUNCTION(start_sama5d3_xplained_ung8071, r0, r1, r2)
arm_setup_stack(SAMA5D3_SRAM_BASE + SAMA5D3_SRAM_SIZE - 16);
- fdt = __dtb_at91_microchip_ksz9477_evb_start + get_runtime_offset();
+ fdt = __dtb_z_at91_microchip_ksz9477_evb_start + get_runtime_offset();
barebox_arm_entry(SAMA5_DDRCS, SZ_256M, fdt);
}
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 60f427d7d483..1401b8cfc9bb 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -547,6 +547,7 @@ config MACH_MICROCHIP_KSZ9477_EVB
depends on ARCH_SAMA5D3
select OFDEVICE
select COMMON_CLK_OF_PROVIDER
+ select ARM_USE_COMPRESSED_DTB
help
Select this if you are using Microchip's EVB-KSZ9477 Evaluation Kit.
--
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[PATCH v3 00/15] ARM: at91: microchip-kz9477-evb: support first stage boot
This is (the hopefully final and bestest) v3 of a series that pulls in
enough of at91bootstrap to make barebox usable as first stage bootloader
for the SAMA5 family of AT91 SoCs.
Besides incorporating feedback on v2 (mainly multi-image support), I've also
reinstated code paths needed by the sama5d2, whose port I worked a bit on.
This patchset applies on top of v2 of "ARM: at91: misc fixes and
cleanup", which I sent out an hour ago. As with v2, it leaves
the user the option to select OFDEVICE for the first stage. I haven't
managed to get a small enough of-based barebox that still works though.
The included defconfig uses board code instead, which makes the MMC
first stage fit into 49K.
Changes since v2 <20190219172150.11901-1-a.fat...@pengutronix.de>:
- addressed Roland's feedback: commits now indicate where they
copy code from if any
- SoC-specific get_ddram_size and associated #ifdeffery was removed
as suggested by Sascha. This series was rebased on-top.
- lowlevel_clock was renamed to at91_pmc_ll because I like that
name more
- removed instances of IS_ENABLED in generic code for multi-image
support. One instance could be inferred from function argument,
the rest now accepts a flags parameter.
- reinstated sama5d2 specific SDRAM and PMC initialization code
as well as necessary register offset definitions
- added missing Atmel copyright/disclaimer in the evb's lowlevel.c
as requested by Roland. Other files have the Atmel copyright,
the disclaimer looks compatible with the newly added
LICENSES/BSD-1-Clause
- removed board code define for multi-image build support as per
Sascha's comment
- adjusted code to use the new MAX_PBL_IMAGE_SIZE for indicating
maximum first stage bootloader size
Changes since v1 <20190116174559.17416-1-a.fat...@pengutronix.de>:
- dropped removal of h32mx code, it was just touched by
ARM: at91: microchip-kz9477-evb: support first stage boot and might
be useful for future ports
- dropped removal of sama5d3_matrix.h, already mainline via
f722f2a12 ("ARM: at91: delete unused mach/sama5d3_matrix.h")
- added commit with BSD-1-Clause license text
- split the migration to the at91bootstrap header for SDRAM defines
into 3 separate commits for better comprehension as suggested by Sam
- arch-prefixed globally visible functions/defines
- copied over some helper functions from at91bootstrap for board init,
or moved them to headers, so board code can look more like at91bootstrap
board code
- moved some helper function into headers, so they can be used in
multiple boards in future
- replaced all __raw_{read,write}T with {read,write}T
- added separate entry point for first stage, like am335x does
- added build-time size check for first stage
- renamed _first_stage suffix to _bootstrap, for symmetry with
the other at91sam9261
- compressed the DTB
- added infrastructure for future device tree based first stage
- added documentation as suggested by Sam
- changed NAND partition layout in board code as suggested by Sascha
- stylistic fixes here and there
Ahmad Fatoum (15):
LICENSES: add BSD-1-Clause license
ARM: at91: import at91bootstrap's at91_ddrsdrc.h
ARM: at91: migrate at91sam9_ddrsdr.h to use at91bootstrap's
at91_ddrsdrc.h
ARM: at91: replace at91sam9_ddrsdr.h with at91bootstrap's
at91_ddrsdrc.h
ARM: at91: watchdog: implement at91_wdt_disable
ARM: at91: import lowlevel clock initialization from at91bootstrap
ARM: at91: import early_udelay from at91bootstrap
ARM: at91: import low level DDRAMC initialization code from
at91bootstrap
ARM: at91: import lowlevel dbgu UART init code from at91bootstrap
images: at91: differentiate between first and second stage images
ARM: at91: microchip-ksz9477-evb: use compressed DTB
ARM: dts: microchip-ksz9477-evb: add dummy first stage device tree
ARM: at91: microchip-ksz9477-evb: implement first stage
ARM: at91: microchip-ksz9477: provide board code fallback
doc: microchip-ksz9477-evb: add documentation
.../boards/at91/microchip-ksz9477-evb.rst | 38 +-
LICENSES/other/X11| 28 +
LICENSES/preferred/BSD-1-Clause | 15 +
arch/arm/boards/at91sam9m10g45ek/lowlevel.c | 2 +-
arch/arm/boards/at91sam9m10ihd/lowlevel.c | 2 +-
arch/arm/boards/at91sam9n12ek/lowlevel.c | 2 +-
arch/arm/boards/at91sam9x5ek/lowlevel.c | 2 +-
.../arm/boards/microchip-ksz9477-evb/Makefile | 3 +
arch/arm/boards/microchip-ksz9477-evb/board.c | 127 +
.../boards/microchip-ksz9477-evb/lowlevel.c | 213 +++-
arch/arm/boards/pm9g45/lowlevel.c | 3 +-
arch/arm/boards/sama5d3_xplained/lowlevel.c | 2 +-
arch/arm/boards/sama5d3xek/lowlevel.c | 2 +-
arch/arm/boards/sama5d4_xplained/lowlevel.c | 2 +-
arch/arm/boards/sama5d4ek/lowlevel.c | 2 +-
...rochip_ksz9477_evb_bootstrap_mmc_defconfig | 24 +
arch/arm/dts
[PATCH v3 08/15] ARM: at91: import low level DDRAMC initialization code from at91bootstrap
This commit imports DDRAMC initialization routines for use in PBL from
https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/driver/ddramc.c
Signed-off-by: Ahmad Fatoum
---
arch/arm/mach-at91/Makefile | 1 +
arch/arm/mach-at91/ddramc.c | 507 +++
arch/arm/mach-at91/include/mach/ddramc.h | 36 ++
3 files changed, 544 insertions(+)
create mode 100644 arch/arm/mach-at91/ddramc.c
create mode 100644 arch/arm/mach-at91/include/mach/ddramc.h
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 25a7916c34e4..f4eb412a2397 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -1,6 +1,7 @@
obj-y += setup.o
pbl-y += at91_pmc_ll.o
pbl-$(CONFIG_CLOCKSOURCE_ATMEL_PIT) += early_udelay.o
+pbl-y += ddramc.o
ifeq ($(CONFIG_COMMON_CLK_OF_PROVIDER),)
obj-y += clock.o
diff --git a/arch/arm/mach-at91/ddramc.c b/arch/arm/mach-at91/ddramc.c
new file mode 100644
index ..a67c8266af4b
--- /dev/null
+++ b/arch/arm/mach-at91/ddramc.c
@@ -0,0 +1,507 @@
+// SPDX-License-Identifier: BSD-1-Clause
+/*
+ * Copyright (c) 2007, Stelian Pop
+ * Copyright (c) 2007 Lead Tech Design
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+void at91_ddram_initialize(unsigned long base_address,
+ unsigned long ram_address,
+ struct at91_ddramc_register *ddramc_config)
+{
+ unsigned long ba_offset;
+ unsigned long cr = 0;
+
+ /* compute BA[] offset according to CR configuration */
+ ba_offset = (ddramc_config->cr & AT91C_DDRC2_NC) + 9;
+ if ((ddramc_config->cr & AT91C_DDRC2_DECOD) ==
AT91C_DDRC2_DECOD_SEQUENTIAL)
+ ba_offset += ((ddramc_config->cr & AT91C_DDRC2_NR) >> 2) + 11;
+
+ ba_offset += (ddramc_config->mdr & AT91C_DDRC2_DBW) ? 1 : 2;
+
+ /*
+* Step 1: Program the memory device type into the Memory Device
Register
+*/
+ writel(ddramc_config->mdr, base_address + AT91C_HDDRSDRC2_MDR);
+
+ /*
+* Step 2: Program the feature of DDR2-SDRAM device into
+* the Timing Register, and into the Configuration Register
+*/
+ writel(ddramc_config->cr, base_address + AT91C_HDDRSDRC2_CR);
+
+ writel(ddramc_config->t0pr, base_address + AT91C_HDDRSDRC2_T0PR);
+ writel(ddramc_config->t1pr, base_address + AT91C_HDDRSDRC2_T1PR);
+ writel(ddramc_config->t2pr, base_address + AT91C_HDDRSDRC2_T2PR);
+
+ /*
+* Step 3: An NOP command is issued to the DDR2-SDRAM
+*/
+ writel(AT91C_DDRC2_MODE_NOP_CMD, base_address + AT91C_HDDRSDRC2_MR);
+ writel(0, ram_address);
+ /* Now, clocks which drive the DDR2-SDRAM device are enabled */
+
+ /* A minimum pause wait 200 us is provided to precede any signal toggle.
+ (6 core cycles per iteration, core is at 396MHz: min 13340 loops) */
+ early_udelay(200);
+
+ /*
+* Step 4: An NOP command is issued to the DDR2-SDRAM
+*/
+ writel(AT91C_DDRC2_MODE_NOP_CMD, base_address + AT91C_HDDRSDRC2_MR);
+ writel(0, ram_address);
+ /* Now, CKE is driven high */
+ /* wait 400 ns min */
+ early_udelay(1);
+
+ /*
+* Step 5: An all banks precharge command is issued to the DDR2-SDRAM.
+*/
+ writel(AT91C_DDRC2_MODE_PRCGALL_CMD, base_address + AT91C_HDDRSDRC2_MR);
+ writel(0, ram_address);
+
+ /* wait 2 cycles min (of tCK) = 15 ns min */
+ early_udelay(1);
+
+ /*
+* Step 6: An Extended Mode Register set(EMRS2) cycle is issued to
chose between commercial or high
+* temperature operations.
+* Perform a write access to DDR2-SDRAM to acknowledge this command.
+* The write address must be chosen so that BA[1] is set to 1 and BA[0]
is set to 0.
+*/
+ writel(AT91C_DDRC2_MODE_EXT_LMR_CMD, base_address + AT91C_HDDRSDRC2_MR);
+ writel(0, ram_address + (0x2 << ba_offset));
+
+ /* wait 2 cycles min (of tCK) = 15 ns min */
+ early_udelay(1);
+
+ /*
+* Step 7: An Extended Mode Register set(EMRS3) cycle is issued
+* to set the Extended Mode Register to "0".
+* Perform a write access to DDR2-SDRAM to acknowledge this command.
+* The write address must be chosen so that BA[1] is set to 1 and BA[0]
is set to 1.
+*/
+ writel(AT91C_DDRC2_MODE_EXT_LMR_CMD, base_address + AT91C_HDDRSDRC2_MR);
+ writel(0, ram_address + (0x3 << ba_offset));
+
+ /* wait 2 cycles min (of tCK) = 15 ns min */
+ early_udelay(1);
+
+ /*
+* Step 8: An Extened Mode Register set(EMRS1) cycle is issued to
enable DLL,
+* and to program D.I.C(Output Driver Impedance Control)
+* Perform a write access to DDR2-SDRAM to acknowledge this command.
+* The write address must be chosen so that BA[1] is set to 0 and BA[0]
is set to 1.
+*/
+ writel(AT91C_DDRC2
[PATCH v3 12/15] ARM: dts: microchip-ksz9477-evb: add dummy first stage device tree
The existing device tree is too big for the 64K byte constrained first stage. Because of the size limitation it might be better to only use the device tree for the second stage. This increases user-friendliness by leaving space for PBL_CONSOLE. For now provide a slightly smaller smaller *-boot-bin.dts device tree for first stage, which can be further stripped in future commits. Signed-off-by: Ahmad Fatoum --- LICENSES/other/X11| 28 +++ arch/arm/dts/Makefile | 4 ++- .../at91-microchip-ksz9477-evb-boot-bin.dts | 13 + 3 files changed, 44 insertions(+), 1 deletion(-) create mode 100644 LICENSES/other/X11 create mode 100644 arch/arm/dts/at91-microchip-ksz9477-evb-boot-bin.dts diff --git a/LICENSES/other/X11 b/LICENSES/other/X11 new file mode 100644 index ..fcbafbf7dc75 --- /dev/null +++ b/LICENSES/other/X11 @@ -0,0 +1,28 @@ +Valid-License-Identifier: X11 +SPDX-URL: https://spdx.org/licenses/X11.html +Usage-Guide: + To use the X11 put the following SPDX tag/value pair into a comment + according to the placement guidelines in the licensing rules + documentation: +SPDX-License-Identifier: X11 +License-Text: + + +X11 License + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +the rights to use, copy, modify, merge, publish, distribute, sublicense, +and/or sell copies of the Software, and to permit persons to whom the +Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 1c6129816daf..64c068334713 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -127,7 +127,9 @@ pbl-dtb-$(CONFIG_MACH_ZII_VF610_DEV) += \ vf610-zii-scu4-aib.dtb.o\ vf610-zii-spb4.dtb.o pbl-dtb-$(CONFIG_MACH_AT91SAM9263EK_DT) += at91sam9263ek.dtb.o -pbl-dtb-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += at91-microchip-ksz9477-evb.dtb.o +pbl-dtb-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += \ + at91-microchip-ksz9477-evb.dtb.o\ + at91-microchip-ksz9477-evb-boot-bin.dtb.o pbl-dtb-$(CONFIG_MACH_AT91SAM9X5EK) += at91sam9x5ek.dtb.o pbl-dtb-$(CONFIG_MACH_XILINX_ZCU104) += zynqmp-zcu104-revA.dtb.o diff --git a/arch/arm/dts/at91-microchip-ksz9477-evb-boot-bin.dts b/arch/arm/dts/at91-microchip-ksz9477-evb-boot-bin.dts new file mode 100644 index ..8823204bcbc7 --- /dev/null +++ b/arch/arm/dts/at91-microchip-ksz9477-evb-boot-bin.dts @@ -0,0 +1,13 @@ +/* + * at91-microchip-ksz9477-evb-boot-bin.dts - First Stage Device Tree for EVB-KSZ9477 + * + * Copyright (C) 2019 Ahmad Fatoum + * + * SPDX-License-Identifier: (GPL-2.0-only OR X11) + */ +#include "at91-microchip-ksz9477-evb.dts" + +/delete-node/ &spi1; +/delete-node/ &macb0; +/delete-node/ &macb1; +/delete-node/ &pinctrl_spi_ksz; -- 2.20.1 ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH v3 06/15] ARM: at91: import lowlevel clock initialization from at91bootstrap
For use by future at91 first stage bootloaders, this commit imports
https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/driver/pmc.c
Signed-off-by: Ahmad Fatoum
---
arch/arm/mach-at91/Makefile | 1 +
arch/arm/mach-at91/at91_pmc_ll.c | 184 ++
arch/arm/mach-at91/include/mach/at91_pmc.h| 24 ++-
arch/arm/mach-at91/include/mach/at91_pmc_ll.h | 78
4 files changed, 284 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/mach-at91/at91_pmc_ll.c
create mode 100644 arch/arm/mach-at91/include/mach/at91_pmc_ll.h
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index d81683ac121a..91b06c085107 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -1,4 +1,5 @@
obj-y += setup.o
+pbl-y += at91_pmc_ll.o
ifeq ($(CONFIG_COMMON_CLK_OF_PROVIDER),)
obj-y += clock.o
diff --git a/arch/arm/mach-at91/at91_pmc_ll.c b/arch/arm/mach-at91/at91_pmc_ll.c
new file mode 100644
index ..bb3b3e6cf970
--- /dev/null
+++ b/arch/arm/mach-at91/at91_pmc_ll.c
@@ -0,0 +1,184 @@
+// SPDX-License-Identifier: BSD-1-Clause
+/*
+ * Copyright (c) 2006, Atmel Corporation
+ */
+
+#include
+#include
+
+#define at91_pmc_write(off, val) writel(val, pmc_base + off)
+#define at91_pmc_read(off) readl(pmc_base + off)
+
+void at91_pmc_init(void __iomem *pmc_base, unsigned int flags)
+{
+ u32 tmp;
+
+ /*
+* Switch the master clock to the slow clock without modifying other
+* parameters. It is assumed that ROM code set H32MXDIV, PLLADIV2,
+* PCK_DIV3.
+*/
+ tmp = at91_pmc_read(AT91_PMC_MCKR);
+ tmp &= ~AT91_PMC_ALT_PCKR_CSS;
+ tmp |= AT91_PMC_CSS_SLOW;
+ at91_pmc_write(AT91_PMC_MCKR, tmp);
+
+ while (!(at91_pmc_read(AT91_PMC_SR) & AT91_PMC_MCKRDY))
+ ;
+
+ if (flags & AT91_PMC_LL_FLAG_SAM9X5_PMC) {
+ /*
+* Enable the Main Crystal Oscillator
+* tST_max = 2ms
+* Startup Time: 32768 * 2ms / 8 = 8
+*/
+ tmp = at91_pmc_read(AT91_CKGR_MOR);
+ tmp &= ~AT91_PMC_OSCOUNT;
+ tmp &= ~AT91_PMC_KEY_MASK;
+ tmp |= AT91_PMC_MOSCEN;
+ tmp |= AT91_PMC_OSCOUNT_(8);
+ tmp |= AT91_PMC_KEY;
+ at91_pmc_write(AT91_CKGR_MOR, tmp);
+
+ while (!(at91_pmc_read(AT91_PMC_SR) & AT91_PMC_MOSCS))
+ ;
+
+ if (flags & AT91_PMC_LL_FLAG_MEASURE_XTAL) {
+ /* Enable a measurement of the Main Crystal Oscillator
*/
+ tmp = at91_pmc_read(AT91_CKGR_MCFR);
+ tmp |= AT91_PMC_CCSS_XTAL_OSC;
+ tmp |= AT91_PMC_RCMEAS;
+ at91_pmc_write(AT91_CKGR_MCFR, tmp);
+
+ while (!(at91_pmc_read(AT91_CKGR_MCFR) &
AT91_PMC_MAINRDY))
+ ;
+ }
+
+
+ /* Switch from internal 12MHz RC to the Main Crystal Oscillator
*/
+ tmp = at91_pmc_read(AT91_CKGR_MOR);
+ tmp &= ~AT91_PMC_OSCBYPASS;
+ tmp &= ~AT91_PMC_KEY_MASK;
+ tmp |= AT91_PMC_KEY;
+ at91_pmc_write(AT91_CKGR_MOR, tmp);
+
+ tmp = at91_pmc_read(AT91_CKGR_MOR);
+ tmp |= AT91_PMC_MOSCSEL;
+ tmp &= ~AT91_PMC_KEY_MASK;
+ tmp |= AT91_PMC_KEY;
+ at91_pmc_write(AT91_CKGR_MOR, tmp);
+
+ while (!(at91_pmc_read(AT91_PMC_SR) & AT91_PMC_MOSCSELS))
+ ;
+
+ if (flags & AT91_PMC_LL_FLAG_DISABLE_RC) {
+ /* Disable the 12MHz RC Oscillator */
+ tmp = at91_pmc_read(AT91_CKGR_MOR);
+ tmp &= ~AT91_PMC_MOSCRCEN;
+ tmp &= ~AT91_PMC_KEY_MASK;
+ tmp |= AT91_PMC_KEY;
+ at91_pmc_write(AT91_CKGR_MOR, tmp);
+ }
+
+ } else {
+ /*
+* Enable the Main Crystal Oscillator
+* tST_max = 2ms
+* Startup Time: 32768 * 2ms / 8 = 8
+*/
+ tmp = at91_pmc_read(AT91_CKGR_MOR);
+ tmp &= ~AT91_PMC_OSCOUNT;
+ tmp |= AT91_PMC_MOSCEN;
+ tmp |= AT91_PMC_OSCOUNT_(8);
+ at91_pmc_write(AT91_CKGR_MOR, tmp);
+
+ while (!(at91_pmc_read(AT91_PMC_SR) & AT91_PMC_MOSCS))
+ ;
+ }
+
+ /* After stablization, switch to Main Clock */
+ if ((at91_pmc_read(AT91_PMC_MCKR) & AT91_PMC_ALT_PCKR_CSS) ==
AT91_PMC_CSS_SLOW) {
+ tmp = at91_pmc_read(AT91_PMC_MCKR);
+ tmp &= ~(0x1 << 13);
+ tmp &= ~AT91_PMC_ALT_PCKR_CSS;
+ tmp |= AT91_PMC_CSS_MAIN;
+ at91_pmc_write(AT91_PMC_MCKR, tmp);
+
+ while
[PATCH v3 15/15] doc: microchip-ksz9477-evb: add documentation
Signed-off-by: Ahmad Fatoum --- .../boards/at91/microchip-ksz9477-evb.rst | 38 ++- 1 file changed, 36 insertions(+), 2 deletions(-) diff --git a/Documentation/boards/at91/microchip-ksz9477-evb.rst b/Documentation/boards/at91/microchip-ksz9477-evb.rst index 4c4c4aecbfb3..2a68c2a552cd 100644 --- a/Documentation/boards/at91/microchip-ksz9477-evb.rst +++ b/Documentation/boards/at91/microchip-ksz9477-evb.rst @@ -1,11 +1,45 @@ Microchip KSZ 9477 Evaluation board === -This is an evaluation board for a switch that uses the at91sam9x5 CPU. +This is an evaluation board for the KSZ9477 switch that uses the sama5d36 CPU. The board uses Device Tree and supports multi image. -Building barebox: +Building barebox as second stage bootloader: .. code-block:: sh make ARCH=arm microchip_ksz9477_evb_defconfig + +There are also a separate defconfig for operating barebox as first stage +bootloader originating from SD Card. +This configuration doesn't yet support device-tree use as the NVM bootloader +(SoC ROM code) requires the first stage bootloader to fit into 64K. + +Generally, the first stage may comes from any of the following boot +sources (in that order): + +* SPI0 CS0 Flash +* SD Card +* NAND Flash +* SPI0 CS1 Flash +* I2C EEPROM + +After being loaded into SRAM by the NVM bootloader, the first stage does low +level clock initialization, configuration of the DDRAM controller and +bootstraps the second stage boot loader. + +SD Card Bootstrap +- + +For boot from SD card, barebox additionally needs to be configured as +first stage bootloader: + +.. code-block:: sh + + make ARCH=arm microchip_ksz9477_evb_bootstrap_mmc_defconfig + +The resulting barebox image must be renamed to ``BOOT.BIN`` +and located in the root directory of the first FAT16/32 partition +on the SD Card/eMMC. After initialization, ``BOOT.BIN`` will look +for a ``barebox.bin`` in the same directory and load and execute it +from SDRAM. -- 2.20.1 ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH v3 10/15] images: at91: differentiate between first and second stage images
Incoming microchip-ksz9477-evb first stage will add one more entry point for the first stage. As there is a little reason to use the same piggy data for both images (BOOT.BIN, the first stage, is limited to 64K), have CONFIG_AT91_LOAD_BAREBOX_SRAM decide which stage should be built. Signed-off-by: Ahmad Fatoum --- arch/arm/mach-at91/Kconfig | 2 +- images/Makefile.at91 | 12 +--- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 8e1bf0629ab7..60f427d7d483 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -615,7 +615,7 @@ config AT91_BOOTSTRAP select BOOTSTRAP config AT91_LOAD_BAREBOX_SRAM - bool "at91 load barebox in sram" + bool "at91 barebox image will be loaded into SRAM" depends on SHELL_NONE || HAVE_AT91_LOAD_BAREBOX_SRAM default y if SHELL_NONE diff --git a/images/Makefile.at91 b/images/Makefile.at91 index acdb591d2452..3f1dd57f6c58 100644 --- a/images/Makefile.at91 +++ b/images/Makefile.at91 @@ -4,12 +4,18 @@ pblb-$(CONFIG_MACH_AT91SAM9X5EK) += start_at91sam9x5ek FILE_barebox-at91sam9x5ek.img = start_at91sam9x5ek.pblb -image-$(CONFIG_MACH_AT91SAM9X5EK) += barebox-at91sam9x5ek.img +at91-barebox-$(CONFIG_MACH_AT91SAM9X5EK) += barebox-at91sam9x5ek.img pblb-$(CONFIG_MACH_AT91SAM9263EK) += start_at91sam9263ek FILE_barebox-at91sam9263ek.img = start_at91sam9263ek.pblb -image-$(CONFIG_MACH_AT91SAM9263EK) += barebox-at91sam9263ek.img +at91-barebox-$(CONFIG_MACH_AT91SAM9263EK) += barebox-at91sam9263ek.img pblb-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += start_sama5d3_xplained_ung8071 FILE_barebox-microchip-ksz9477-evb.img = start_sama5d3_xplained_ung8071.pblb -image-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += barebox-microchip-ksz9477-evb.img +at91-barebox-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += barebox-microchip-ksz9477-evb.img + +ifdef CONFIG_AT91_LOAD_BAREBOX_SRAM +image-y += $(at91-boot-bin-y) +else +image-y += $(at91-barebox-y) +endif -- 2.20.1 ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH v3 03/15] ARM: at91: migrate at91sam9_ddrsdr.h to use at91bootstrap's at91_ddrsdrc.h
Instead of adding missing definitions to the existing at91sam9_ddrsdr.h and adapting the incoming DDRAM initialization code from at91bootstrap, just replace the lightly used existing header with: https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/include/arch/at91_ddrsdrc.h For easier comprehension, the replacement is done in three steps: Here the existing at91sam9_ddrsdr.h has its now duplicate (in function, not name) macros removed and existing users are migrated to use the new header. Signed-off-by: Ahmad Fatoum --- arch/arm/mach-at91/at91sam9g45_reset.S| 6 +- .../mach-at91/include/mach/at91sam9_ddrsdr.h | 138 ++ 2 files changed, 12 insertions(+), 132 deletions(-) diff --git a/arch/arm/mach-at91/at91sam9g45_reset.S b/arch/arm/mach-at91/at91sam9g45_reset.S index 6a58de618ce0..085683c7f9d8 100644 --- a/arch/arm/mach-at91/at91sam9g45_reset.S +++ b/arch/arm/mach-at91/at91sam9g45_reset.S @@ -20,13 +20,13 @@ .globl at91sam9g45_reset at91sam9g45_reset: mov r2, #1 - mov r3, #AT91_DDRSDRC_LPCB_POWER_DOWN + mov r3, #AT91C_DDRC2_LPCB_POWERDOWN ldr r4, =AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST .balign 32 @ align to cache line - str r2, [r0, #AT91_DDRSDRC_RTR] @ disable DDR0 access - str r3, [r0, #AT91_DDRSDRC_LPR] @ power down DDR0 + str r2, [r0, #AT91C_HDDRSDRC2_RTR] @ disable DDR0 access + str r3, [r0, #AT91C_HDDRSDRC2_LPR] @ power down DDR0 str r4, [r1]@ reset processor b . diff --git a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h index b50c11b128bf..22c00d9edaac 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h +++ b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h @@ -12,130 +12,10 @@ #ifndef AT91SAM9_DDRSDR_H #define AT91SAM9_DDRSDR_H -#define AT91_DDRSDRC_MR0x00/* Mode Register */ -#defineAT91_DDRSDRC_MODE (0x7 << 0) /* Command Mode */ -#defineAT91_DDRSDRC_MODE_NORMAL0 -#defineAT91_DDRSDRC_MODE_NOP 1 -#defineAT91_DDRSDRC_MODE_PRECHARGE 2 -#defineAT91_DDRSDRC_MODE_LMR 3 -#defineAT91_DDRSDRC_MODE_REFRESH 4 -#defineAT91_DDRSDRC_MODE_EXT_LMR 5 -#defineAT91_DDRSDRC_MODE_DEEP 6 - -#define AT91_DDRSDRC_RTR 0x04/* Refresh Timer Register */ -#defineAT91_DDRSDRC_COUNT (0xfff << 0)/* Refresh Timer Counter */ - -#define AT91_DDRSDRC_CR0x08/* Configuration Register */ -#defineAT91_DDRSDRC_NC (3 << 0)/* Number of Column Bits */ -#defineAT91_DDRSDRC_NC_SDR8(0 << 0) -#defineAT91_DDRSDRC_NC_SDR9(1 << 0) -#defineAT91_DDRSDRC_NC_SDR10 (2 << 0) -#defineAT91_DDRSDRC_NC_SDR11 (3 << 0) -#defineAT91_DDRSDRC_NC_DDR9(0 << 0) -#defineAT91_DDRSDRC_NC_DDR10 (1 << 0) -#defineAT91_DDRSDRC_NC_DDR11 (2 << 0) -#defineAT91_DDRSDRC_NC_DDR12 (3 << 0) -#defineAT91_DDRSDRC_NR (3 << 2)/* Number of Row Bits */ -#defineAT91_DDRSDRC_NR_11 (0 << 2) -#defineAT91_DDRSDRC_NR_12 (1 << 2) -#defineAT91_DDRSDRC_NR_13 (2 << 2) -#defineAT91_DDRSDRC_NR_14 (3 << 2) -#defineAT91_DDRSDRC_CAS(7 << 4)/* CAS Latency */ -#defineAT91_DDRSDRC_CAS_2 (2 << 4) -#defineAT91_DDRSDRC_CAS_3 (3 << 4) -#defineAT91_DDRSDRC_CAS_25 (6 << 4) -#defineAT91_DDRSDRC_RST_DLL(1 << 7)/* Reset DLL */ -#defineAT91_DDRSDRC_DICDS (1 << 8)/* Output impedance control */ -#defineAT91_DDRSDRC_DIS_DLL(1 << 9)/* Disable DLL [SAM9 Only] */ -#defineAT91_DDRSDRC_OCD(1 << 12) /* Off-Chip Driver [SAM9 Only] */ -#defineAT91_DDRSDRC_DQMS (1 << 16) /* Mask Data is Shared [SAM9 Only] */ -#defineAT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y [SAM9 Only] */ -#defineAT91_DDRSDRC_NB
[PATCH v2 04/10] ARM: at91: fix at91sama5_get_ddram_size for sama5d4
at91sama5_get_ddram_size() is despite the name specific to the
sama5d3 which it was added alongside of. sama5d4 board code continues
to use it, but accessing SAMA5D3_BASE_MPDDRC (0xea00) on
a sama5d4 should result in a Data Abort (Datasheet Figure 5-1)..
Fix this by giving at91sama5_get_ddram_size the mpddrc base
address as argument and adjust call sites appropriately.
This change was not tested on a sama5d4.
Signed-off-by: Ahmad Fatoum
Reviewed-by: Sam Ravnborg
Tested-by: Sam Ravnborg
---
arch/arm/boards/sama5d3_xplained/lowlevel.c | 2 +-
arch/arm/boards/sama5d3xek/lowlevel.c | 2 +-
arch/arm/boards/sama5d4_xplained/lowlevel.c | 2 +-
arch/arm/boards/sama5d4ek/lowlevel.c | 2 +-
arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h | 6 ++
arch/arm/mach-at91/sama5d3_devices.c | 2 +-
arch/arm/mach-at91/sama5d4_devices.c | 2 +-
7 files changed, 8 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boards/sama5d3_xplained/lowlevel.c
b/arch/arm/boards/sama5d3_xplained/lowlevel.c
index 0e25270142f2..92dd515ca64e 100644
--- a/arch/arm/boards/sama5d3_xplained/lowlevel.c
+++ b/arch/arm/boards/sama5d3_xplained/lowlevel.c
@@ -19,5 +19,5 @@ void __naked __bare_init barebox_arm_reset_vector(uint32_t
r0, uint32_t r1, uint
arm_setup_stack(SAMA5D3_SRAM_BASE + SAMA5D3_SRAM_SIZE - 16);
- barebox_arm_entry(SAMA5_DDRCS, at91sama5_get_ddram_size(), NULL);
+ barebox_arm_entry(SAMA5_DDRCS,
at91sama5_get_ddram_size(IOMEM(SAMA5D3_BASE_MPDDRC)), NULL);
}
diff --git a/arch/arm/boards/sama5d3xek/lowlevel.c
b/arch/arm/boards/sama5d3xek/lowlevel.c
index 0e25270142f2..92dd515ca64e 100644
--- a/arch/arm/boards/sama5d3xek/lowlevel.c
+++ b/arch/arm/boards/sama5d3xek/lowlevel.c
@@ -19,5 +19,5 @@ void __naked __bare_init barebox_arm_reset_vector(uint32_t
r0, uint32_t r1, uint
arm_setup_stack(SAMA5D3_SRAM_BASE + SAMA5D3_SRAM_SIZE - 16);
- barebox_arm_entry(SAMA5_DDRCS, at91sama5_get_ddram_size(), NULL);
+ barebox_arm_entry(SAMA5_DDRCS,
at91sama5_get_ddram_size(IOMEM(SAMA5D3_BASE_MPDDRC)), NULL);
}
diff --git a/arch/arm/boards/sama5d4_xplained/lowlevel.c
b/arch/arm/boards/sama5d4_xplained/lowlevel.c
index 8ae4e6e0d237..168d424baee7 100644
--- a/arch/arm/boards/sama5d4_xplained/lowlevel.c
+++ b/arch/arm/boards/sama5d4_xplained/lowlevel.c
@@ -19,5 +19,5 @@ void __naked __bare_init barebox_arm_reset_vector(uint32_t
r0, uint32_t r1, uint
arm_setup_stack(SAMA5D4_SRAM_BASE + SAMA5D4_SRAM_SIZE - 16);
- barebox_arm_entry(SAMA5_DDRCS, at91sama5_get_ddram_size(), NULL);
+ barebox_arm_entry(SAMA5_DDRCS,
at91sama5_get_ddram_size(IOMEM(SAMA5D4_BASE_MPDDRC)), NULL);
}
diff --git a/arch/arm/boards/sama5d4ek/lowlevel.c
b/arch/arm/boards/sama5d4ek/lowlevel.c
index 8ae4e6e0d237..168d424baee7 100644
--- a/arch/arm/boards/sama5d4ek/lowlevel.c
+++ b/arch/arm/boards/sama5d4ek/lowlevel.c
@@ -19,5 +19,5 @@ void __naked __bare_init barebox_arm_reset_vector(uint32_t
r0, uint32_t r1, uint
arm_setup_stack(SAMA5D4_SRAM_BASE + SAMA5D4_SRAM_SIZE - 16);
- barebox_arm_entry(SAMA5_DDRCS, at91sama5_get_ddram_size(), NULL);
+ barebox_arm_entry(SAMA5_DDRCS,
at91sama5_get_ddram_size(IOMEM(SAMA5D4_BASE_MPDDRC)), NULL);
}
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
index b0c003cd1e05..a775d3b19691 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
@@ -222,13 +222,11 @@ static inline u32 at91sam9n12_get_ddram_size(void)
#endif
#ifdef CONFIG_SOC_SAMA5
-#include
-static inline u32 at91sama5_get_ddram_size(void)
+static inline u32 at91sama5_get_ddram_size(void __iomem *base)
{
u32 cr;
u32 mdr;
u32 size;
- void * __iomem base = IOMEM(SAMA5D3_BASE_MPDDRC);
cr = readl(base + AT91_DDRSDRC_CR);
mdr = readl(base + AT91_DDRSDRC_MDR);
@@ -253,7 +251,7 @@ static inline u32 at91sama5_get_ddram_size(void)
return size;
}
#else
-static inline u32 at91sama5_get_ddram_size(void)
+static inline u32 at91sama5_get_ddram_size(void __iomem *base)
{
return 0;
}
diff --git a/arch/arm/mach-at91/sama5d3_devices.c
b/arch/arm/mach-at91/sama5d3_devices.c
index f5075b39374f..b61d2b309ce0 100644
--- a/arch/arm/mach-at91/sama5d3_devices.c
+++ b/arch/arm/mach-at91/sama5d3_devices.c
@@ -28,7 +28,7 @@
void at91_add_device_sdram(u32 size)
{
if (!size)
- size = at91sama5_get_ddram_size();
+ size = at91sama5_get_ddram_size(IOMEM(SAMA5D3_BASE_MPDDRC));
arm_add_mem_device("ram0", SAMA5_DDRCS, size);
add_mem_device("sram0", SAMA5D3_SRAM_BASE,
diff --git a/arch/arm/mach-at91/sama5d4_devices.c
b/arch/arm/mach-at91/sama5d4_devices.c
index 4064e4441f9f..546d0888bfd8 100644
--- a/arch/arm/mach-at91/sama5d4_devices.c
+++ b/arch/arm/mach-at91/sama5d4_devices.c
@@ -29,7 +29,7
[PATCH v2 06/10] ARM: at91: remove at91sam9g45_get_ddram_size helper
Substitute the current #ifdefery in at91sam9_ddrsdr.h by
open-coding at91sam9g45_get_ddram_size wherever it was called.
Suggested-by: Sascha Hauer
Signed-off-by: Ahmad Fatoum
---
arch/arm/boards/at91sam9m10g45ek/lowlevel.c | 5 +++--
arch/arm/boards/at91sam9m10ihd/lowlevel.c | 5 +++--
arch/arm/boards/pm9g45/lowlevel.c | 5 +++--
arch/arm/mach-at91/at91sam9g45_devices.c | 2 +-
.../mach-at91/include/mach/at91sam9_ddrsdr.h | 20 ---
5 files changed, 10 insertions(+), 27 deletions(-)
diff --git a/arch/arm/boards/at91sam9m10g45ek/lowlevel.c
b/arch/arm/boards/at91sam9m10g45ek/lowlevel.c
index 1d83cdf0bfe1..d5deedfc37b5 100644
--- a/arch/arm/boards/at91sam9m10g45ek/lowlevel.c
+++ b/arch/arm/boards/at91sam9m10g45ek/lowlevel.c
@@ -19,6 +19,7 @@ void __naked __bare_init barebox_arm_reset_vector(uint32_t
r0, uint32_t r1, uint
arm_setup_stack(AT91SAM9G45_SRAM_BASE + AT91SAM9G45_SRAM_SIZE - 16);
- barebox_arm_entry(AT91_CHIPSELECT_6, at91sam9g45_get_ddram_size(1),
- NULL);
+ barebox_arm_entry(AT91_CHIPSELECT_6,
+ at91_get_ddram_size(IOMEM(AT91SAM9G45_BASE_DDRSDRC1),
false),
+ NULL);
}
diff --git a/arch/arm/boards/at91sam9m10ihd/lowlevel.c
b/arch/arm/boards/at91sam9m10ihd/lowlevel.c
index 4ccbb9355745..24d41cfa70ea 100644
--- a/arch/arm/boards/at91sam9m10ihd/lowlevel.c
+++ b/arch/arm/boards/at91sam9m10ihd/lowlevel.c
@@ -20,6 +20,7 @@ void __naked __bare_init barebox_arm_reset_vector(uint32_t
r0, uint32_t r1, uint
arm_setup_stack(AT91SAM9G45_SRAM_BASE + AT91SAM9G45_SRAM_SIZE - 16);
- barebox_arm_entry(AT91_CHIPSELECT_6, at91sam9g45_get_ddram_size(1),
- NULL);
+ barebox_arm_entry(AT91_CHIPSELECT_6,
+ at91_get_ddram_size(IOMEM(AT91SAM9G45_BASE_DDRSDRC1),
false),
+ NULL);
}
diff --git a/arch/arm/boards/pm9g45/lowlevel.c
b/arch/arm/boards/pm9g45/lowlevel.c
index 12cf950685c6..fbf2b655c708 100644
--- a/arch/arm/boards/pm9g45/lowlevel.c
+++ b/arch/arm/boards/pm9g45/lowlevel.c
@@ -19,6 +19,7 @@ void __naked __bare_init barebox_arm_reset_vector(uint32_t
r0, uint32_t r1, uint
arm_setup_stack(AT91SAM9G45_SRAM_BASE + AT91SAM9G45_SRAM_SIZE - 16);
- barebox_arm_entry(AT91_CHIPSELECT_6, at91sam9g45_get_ddram_size(1),
- NULL);
+ barebox_arm_entry(AT91_CHIPSELECT_6,
+ at91_get_ddram_size(IOMEM(AT91SAM9G45_BASE_DDRSDRC1),
false),
+ NULL);
}
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c
b/arch/arm/mach-at91/at91sam9g45_devices.c
index 43d8d5fbd6a2..df0c8a4e4f4e 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -28,7 +28,7 @@
void at91_add_device_sdram(u32 size)
{
if (!size)
- size = at91sam9g45_get_ddram_size(1);
+ size = at91_get_ddram_size(IOMEM(AT91SAM9G45_BASE_DDRSDRC1),
false);
arm_add_mem_device("ram0", AT91_CHIPSELECT_6, size);
add_mem_device("sram0", AT91SAM9G45_SRAM_BASE,
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
index 795eb0ce9a9f..9f1a2c78ff46 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
@@ -176,26 +176,6 @@ static inline u32 at91_get_ddram_size(void * __iomem base,
bool is_nb)
return size;
}
-#ifdef CONFIG_SOC_AT91SAM9G45
-#include
-static inline u32 at91sam9g45_get_ddram_size(int bank)
-{
- switch (bank) {
- case 0:
- return at91_get_ddram_size(IOMEM(AT91SAM9G45_BASE_DDRSDRC0),
false);
- case 1:
- return at91_get_ddram_size(IOMEM(AT91SAM9G45_BASE_DDRSDRC1),
false);
- default:
- return 0;
- }
-}
-#else
-static inline u32 at91sam9g45_get_ddram_size(int bank)
-{
- return 0;
-}
-#endif
-
#ifdef CONFIG_SOC_AT91SAM9X5
#include
static inline u32 at91sam9x5_get_ddram_size(void)
--
2.20.1
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[PATCH v2 08/10] ARM: at91: remove at91sam9x5_get_ddram_size helper
Substitute the current #ifdefery in at91sam9_ddrsdr.h by
open-coding at91sam9x5_get_ddram_size wherever it was called.
Suggested-by: Sascha Hauer
Signed-off-by: Ahmad Fatoum
---
arch/arm/boards/at91sam9x5ek/lowlevel.c | 4 +++-
arch/arm/mach-at91/at91sam9x5_devices.c | 2 +-
arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h | 13 -
3 files changed, 4 insertions(+), 15 deletions(-)
diff --git a/arch/arm/boards/at91sam9x5ek/lowlevel.c
b/arch/arm/boards/at91sam9x5ek/lowlevel.c
index 9aa0e8ba9b2b..14c239408d6a 100644
--- a/arch/arm/boards/at91sam9x5ek/lowlevel.c
+++ b/arch/arm/boards/at91sam9x5ek/lowlevel.c
@@ -17,5 +17,7 @@ ENTRY_FUNCTION(start_at91sam9x5ek, r0, r1, r2)
fdt = __dtb_at91sam9x5ek_start + get_runtime_offset();
- barebox_arm_entry(AT91_CHIPSELECT_1, at91sam9x5_get_ddram_size(), fdt);
+ barebox_arm_entry(AT91_CHIPSELECT_1,
+ at91_get_ddram_size(IOMEM(AT91SAM9X5_BASE_DDRSDRC0),
true),
+ fdt);
}
diff --git a/arch/arm/mach-at91/at91sam9x5_devices.c
b/arch/arm/mach-at91/at91sam9x5_devices.c
index ab506a1f4236..f794d9ae8f73 100644
--- a/arch/arm/mach-at91/at91sam9x5_devices.c
+++ b/arch/arm/mach-at91/at91sam9x5_devices.c
@@ -27,7 +27,7 @@
void at91_add_device_sdram(u32 size)
{
if (!size)
- size = at91sam9x5_get_ddram_size();
+ size = at91_get_ddram_size(IOMEM(AT91SAM9X5_BASE_DDRSDRC0),
true);
arm_add_mem_device("ram0", AT91_CHIPSELECT_1, size);
add_mem_device("sram0", AT91SAM9X5_SRAM_BASE,
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
index f9c908fc38b0..cc3affa17a61 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
@@ -176,19 +176,6 @@ static inline u32 at91_get_ddram_size(void * __iomem base,
bool is_nb)
return size;
}
-#ifdef CONFIG_SOC_AT91SAM9X5
-#include
-static inline u32 at91sam9x5_get_ddram_size(void)
-{
- return at91_get_ddram_size(IOMEM(AT91SAM9X5_BASE_DDRSDRC0), true);
-}
-#else
-static inline u32 at91sam9x5_get_ddram_size(void)
-{
- return 0;
-}
-#endif
-
#ifdef CONFIG_SOC_SAMA5
static inline u32 at91sama5_get_ddram_size(void __iomem *base)
{
--
2.20.1
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[PATCH v2 01/10] ARM: at91: replace __raw_{readl, writel} of peripherals with readl, writel
Use the potentially endianness-changing readl, writel and siblings
directly. They looks prettier and are the correct thing to do, as
even if the CPU is in big-endian mode, the peripherals are little-endian.
Unlike Linux, barebox readl,writel are the same Linux'
{readl,writel}_relaxed (they don't imply memory barriers)
and thus there shouldn't be any functional change.
Patch was generated by a mass search and replace. I looked it over,
adjust some whitespace and further verified by reviewing the output of
git diff HEAD~1 --word-diff | \
perl -pe 's/\[-(.*?)__raw_/{+$1/; s/-\]\{\+/+}{+/;' \
-e 's/(\{\+.*?\+\})\1/__ALL_IS_WELL__/' | grep '+}{+'
which filters out the common case of lines where a single
__raw_{readT,writeT} had its __raw_ prefix stripped without any
further changes.
Signed-off-by: Ahmad Fatoum
Reviewed-by: Sam Ravnborg
Tested-by: Sam Ravnborg
---
arch/arm/boards/at91rm9200ek/lowlevel.c | 40 -
.../include/mach/at91sam926x_board_init.h | 22 ++---
.../mach-at91/include/mach/at91sam9_ddrsdr.h | 8 +-
.../mach-at91/include/mach/at91sam9_sdramc.h | 4 +-
arch/arm/mach-at91/include/mach/debug_ll.h| 6 +-
arch/arm/mach-at91/include/mach/gpio.h| 57 ++--
arch/arm/mach-at91/sam9_smc.c | 58 ++---
arch/arm/mach-at91/setup.c| 4 +-
drivers/clocksource/timer-atmel-pit.c | 4 +-
drivers/mci/atmel-mci-regs.h | 4 +-
drivers/net/at91_ether.h | 4 +-
drivers/net/macb.h| 8 +-
drivers/pinctrl/pinctrl-at91.c| 28 +++---
drivers/spi/atmel_spi.h | 4 +-
drivers/usb/gadget/at91_udc.c | 86 +--
drivers/video/atmel_lcdfb.h | 4 +-
16 files changed, 168 insertions(+), 173 deletions(-)
diff --git a/arch/arm/boards/at91rm9200ek/lowlevel.c
b/arch/arm/boards/at91rm9200ek/lowlevel.c
index 030c3dbf04a5..b132ccc08431 100644
--- a/arch/arm/boards/at91rm9200ek/lowlevel.c
+++ b/arch/arm/boards/at91rm9200ek/lowlevel.c
@@ -33,28 +33,28 @@ void __naked __bare_init barebox_arm_reset_vector(uint32_t
r0, uint32_t r1, uint
/*
* PMC Check if the PLL is already initialized
*/
- r = __raw_readl(pmc + AT91_PMC_MCKR);
+ r = readl(pmc + AT91_PMC_MCKR);
if (r & AT91_PMC_CSS)
goto end;
/*
* Enable the Main Oscillator
*/
- __raw_writel(CONFIG_SYS_MOR_VAL, pmc + AT91_CKGR_MOR);
+ writel(CONFIG_SYS_MOR_VAL, pmc + AT91_CKGR_MOR);
do {
- r = __raw_readl(pmc + AT91_PMC_SR);
+ r = readl(pmc + AT91_PMC_SR);
} while (!(r & AT91_PMC_MOSCS));
/*
* EBI_CFGR
*/
- __raw_writel(CONFIG_SYS_EBI_CFGR_VAL, mc + AT91RM9200_EBI_CFGR);
+ writel(CONFIG_SYS_EBI_CFGR_VAL, mc + AT91RM9200_EBI_CFGR);
/*
* SMC2_CSR[0]: 16bit, 2 TDF, 4 WS
*/
- __raw_writel(CONFIG_SYS_SMC_CSR0_VAL, mc + AT91RM9200_SMC_CSR(0));
+ writel(CONFIG_SYS_SMC_CSR0_VAL, mc + AT91RM9200_SMC_CSR(0));
/*
* Init Clocks
@@ -63,24 +63,24 @@ void __naked __bare_init barebox_arm_reset_vector(uint32_t
r0, uint32_t r1, uint
/*
* PLLAR: x MHz for PCK
*/
- __raw_writel(CONFIG_SYS_PLLAR_VAL, pmc + AT91_CKGR_PLLAR);
+ writel(CONFIG_SYS_PLLAR_VAL, pmc + AT91_CKGR_PLLAR);
do {
- r = __raw_readl(pmc + AT91_PMC_SR);
+ r = readl(pmc + AT91_PMC_SR);
} while (!(r & AT91_PMC_LOCKA));
/*
* PCK/x = MCK Master Clock from SLOW
*/
- __raw_writel(CONFIG_SYS_MCKR2_VAL1, pmc + AT91_PMC_MCKR);
+ writel(CONFIG_SYS_MCKR2_VAL1, pmc + AT91_PMC_MCKR);
/*
* PCK/x = MCK Master Clock from PLLA
*/
- __raw_writel(CONFIG_SYS_MCKR2_VAL2, pmc + AT91_PMC_MCKR);
+ writel(CONFIG_SYS_MCKR2_VAL2, pmc + AT91_PMC_MCKR);
do {
- r = __raw_readl(pmc + AT91_PMC_SR);
+ r = readl(pmc + AT91_PMC_SR);
} while (!(r & AT91_PMC_MCKRDY));
/*
@@ -88,38 +88,38 @@ void __naked __bare_init barebox_arm_reset_vector(uint32_t
r0, uint32_t r1, uint
*/
/* PIOC_ASR: Configure PIOC as peripheral (D16/D31) */
- __raw_writel(CONFIG_SYS_PIOC_ASR_VAL, AT91RM9200_BASE_PIOC + PIO_ASR);
+ writel(CONFIG_SYS_PIOC_ASR_VAL, AT91RM9200_BASE_PIOC + PIO_ASR);
/* PIOC_BSR */
- __raw_writel(CONFIG_SYS_PIOC_BSR_VAL, AT91RM9200_BASE_PIOC + PIO_BSR);
+ writel(CONFIG_SYS_PIOC_BSR_VAL, AT91RM9200_BASE_PIOC + PIO_BSR);
/* PIOC_PDR */
- __raw_writel(CONFIG_SYS_PIOC_PDR_VAL, AT91RM9200_BASE_PIOC + PIO_PDR);
+ writel(CONFIG_SYS_PIOC_PDR_VAL, AT91RM9200_BASE_PIOC + PIO_PDR);
/* EBI_CSA : CS1=SDRAM */
- __raw_writel(CONFIG_SYS_EBI_CSA_VAL, mc + AT91
[PATCH v2 10/10] clk: at91: fix warning about missing const-safety
compiling clk-main.c results in: warning: passing argument 1 of 'memcpy' discards 'const' qualifier from pointer target type [-Wdiscarded-qualifiers] memcpy(clkmain->clk.parent_names, parent_names, parents_array_size); ^ Avoid this by replacing the xzalloc+memcpy pair with xmemdup. Zero-initialization of the buffer isn't necessary, because memcpy spans the whole buffer. Signed-off-by: Ahmad Fatoum --- drivers/clk/at91/clk-main.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c index 4d4127dd0016..abae35566c2f 100644 --- a/drivers/clk/at91/clk-main.c +++ b/drivers/clk/at91/clk-main.c @@ -455,8 +455,7 @@ at91_clk_register_sam9x5_main(struct regmap *regmap, clkmain->clk.name = name; clkmain->clk.ops = &sam9x5_main_ops; parents_array_size = num_parents * sizeof (clkmain->clk.parent_names[0]); - clkmain->clk.parent_names = xzalloc(parents_array_size); - memcpy(clkmain->clk.parent_names, parent_names, parents_array_size); + clkmain->clk.parent_names = xmemdup(parent_names, parents_array_size); clkmain->clk.num_parents = num_parents; /* init.flags = CLK_SET_PARENT_GATE; */ -- 2.20.1 ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH v2 07/10] ARM: at91: remove at91sam9n12_get_ddram_size helper
Substitute the current #ifdefery in at91sam9_ddrsdr.h by
open-coding at91sam9n12_get_ddram_size wherever it was called.
Suggested-by: Sascha Hauer
Signed-off-by: Ahmad Fatoum
---
arch/arm/boards/at91sam9n12ek/lowlevel.c | 5 +++--
arch/arm/mach-at91/at91sam9n12_devices.c | 2 +-
arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h | 13 -
3 files changed, 4 insertions(+), 16 deletions(-)
diff --git a/arch/arm/boards/at91sam9n12ek/lowlevel.c
b/arch/arm/boards/at91sam9n12ek/lowlevel.c
index f57e439b9ec5..094fd941bc8c 100644
--- a/arch/arm/boards/at91sam9n12ek/lowlevel.c
+++ b/arch/arm/boards/at91sam9n12ek/lowlevel.c
@@ -19,6 +19,7 @@ void __naked __bare_init barebox_arm_reset_vector(uint32_t
r0, uint32_t r1, uint
arm_setup_stack(AT91SAM9N12_SRAM_BASE + AT91SAM9N12_SRAM_SIZE - 16);
- barebox_arm_entry(AT91_CHIPSELECT_1, at91sam9n12_get_ddram_size(),
- NULL);
+ barebox_arm_entry(AT91_CHIPSELECT_1,
+ at91_get_ddram_size(IOMEM(AT91SAM9N12_BASE_DDRSDRC0),
true),
+ NULL);
}
diff --git a/arch/arm/mach-at91/at91sam9n12_devices.c
b/arch/arm/mach-at91/at91sam9n12_devices.c
index 43cbb79af4a5..3ee07568f2c7 100644
--- a/arch/arm/mach-at91/at91sam9n12_devices.c
+++ b/arch/arm/mach-at91/at91sam9n12_devices.c
@@ -28,7 +28,7 @@
void at91_add_device_sdram(u32 size)
{
if (!size)
- size = at91sam9n12_get_ddram_size();
+ size = at91_get_ddram_size(IOMEM(AT91SAM9N12_BASE_DDRSDRC0),
true);
arm_add_mem_device("ram0", AT91_CHIPSELECT_1, size);
add_mem_device("sram0", AT91SAM9N12_SRAM_BASE,
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
index 9f1a2c78ff46..f9c908fc38b0 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
@@ -189,19 +189,6 @@ static inline u32 at91sam9x5_get_ddram_size(void)
}
#endif
-#ifdef CONFIG_SOC_AT91SAM9N12
-#include
-static inline u32 at91sam9n12_get_ddram_size(void)
-{
- return at91_get_ddram_size(IOMEM(AT91SAM9N12_BASE_DDRSDRC0), true);
-}
-#else
-static inline u32 at91sam9n12_get_ddram_size(void)
-{
- return 0;
-}
-#endif
-
#ifdef CONFIG_SOC_SAMA5
static inline u32 at91sama5_get_ddram_size(void __iomem *base)
{
--
2.20.1
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[PATCH v2 05/10] ARM: at91: remove duplicate get_ddram_size code
Both at91_get_ddram_size and at91sama5_get_ddram_size are the
same if is_sdram == false and is_nb == true.
is_sdram is always false, because according to the sama5d{2,3,4}
datasheets, the lowest possible value for AT91_DDRSDRC_MD is 3
(i.e. none of them supports SDR SDRAM).
Therefore have at91sama5_get_ddram_size call at91_get_ddram_size
with is_nb == true and remove the duplicate code.
Signed-off-by: Ahmad Fatoum
Reviewed-by: Sam Ravnborg
Tested-by: Sam Ravnborg
---
.../mach-at91/include/mach/at91sam9_ddrsdr.h | 27 ++-
1 file changed, 2 insertions(+), 25 deletions(-)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
index a775d3b19691..795eb0ce9a9f 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
@@ -148,6 +148,7 @@ static inline u32 at91_get_ddram_size(void * __iomem base,
bool is_nb)
cr = readl(base + AT91_DDRSDRC_CR);
mdr = readl(base + AT91_DDRSDRC_MDR);
+ /* will always be false for sama5d2, sama5d3 or sama5d4 */
is_sdram = (mdr & AT91_DDRSDRC_MD) <= AT91_DDRSDRC_MD_LOW_POWER_SDR;
/* Formula:
@@ -224,31 +225,7 @@ static inline u32 at91sam9n12_get_ddram_size(void)
#ifdef CONFIG_SOC_SAMA5
static inline u32 at91sama5_get_ddram_size(void __iomem *base)
{
- u32 cr;
- u32 mdr;
- u32 size;
-
- cr = readl(base + AT91_DDRSDRC_CR);
- mdr = readl(base + AT91_DDRSDRC_MDR);
-
- /* Formula:
-* size = bank << (col + row + 1);
-* if (bandwidth == 32 bits)
-* size <<= 1;
-*/
- size = 1;
- /* COL */
- size += (cr & AT91_DDRSDRC_NC) + 9;
- /* ROW */
- size += ((cr & AT91_DDRSDRC_NR) >> 2) + 11;
- /* BANK */
- size = ((cr & AT91_DDRSDRC_NB) ? 8 : 4) << size;
-
- /* bandwidth */
- if (!(mdr & AT91_DDRSDRC_DBW))
- size <<= 1;
-
- return size;
+ return at91_get_ddram_size(base, true);
}
#else
static inline u32 at91sama5_get_ddram_size(void __iomem *base)
--
2.20.1
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[PATCH v2 03/10] arm: sama5d4: fix stack setup
From: Sam Ravnborg
The code that configure the stack uses sama5d3 constants.
Fix this to use the proper sama5d4 constants.
Boot tested on sama5d4_xplained.
Signed-off-by: Sam Ravnborg
---
arch/arm/boards/sama5d4_xplained/lowlevel.c | 2 +-
arch/arm/boards/sama5d4ek/lowlevel.c| 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boards/sama5d4_xplained/lowlevel.c
b/arch/arm/boards/sama5d4_xplained/lowlevel.c
index 0e25270142f2..8ae4e6e0d237 100644
--- a/arch/arm/boards/sama5d4_xplained/lowlevel.c
+++ b/arch/arm/boards/sama5d4_xplained/lowlevel.c
@@ -17,7 +17,7 @@ void __naked __bare_init barebox_arm_reset_vector(uint32_t
r0, uint32_t r1, uint
{
arm_cpu_lowlevel_init();
- arm_setup_stack(SAMA5D3_SRAM_BASE + SAMA5D3_SRAM_SIZE - 16);
+ arm_setup_stack(SAMA5D4_SRAM_BASE + SAMA5D4_SRAM_SIZE - 16);
barebox_arm_entry(SAMA5_DDRCS, at91sama5_get_ddram_size(), NULL);
}
diff --git a/arch/arm/boards/sama5d4ek/lowlevel.c
b/arch/arm/boards/sama5d4ek/lowlevel.c
index 0e25270142f2..8ae4e6e0d237 100644
--- a/arch/arm/boards/sama5d4ek/lowlevel.c
+++ b/arch/arm/boards/sama5d4ek/lowlevel.c
@@ -17,7 +17,7 @@ void __naked __bare_init barebox_arm_reset_vector(uint32_t
r0, uint32_t r1, uint
{
arm_cpu_lowlevel_init();
- arm_setup_stack(SAMA5D3_SRAM_BASE + SAMA5D3_SRAM_SIZE - 16);
+ arm_setup_stack(SAMA5D4_SRAM_BASE + SAMA5D4_SRAM_SIZE - 16);
barebox_arm_entry(SAMA5_DDRCS, at91sama5_get_ddram_size(), NULL);
}
--
2.20.1
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[PATCH v2 09/10] ARM: at91: remove at91sama5_get_ddram_size helper
Substitute the current #ifdefery in at91sam9_ddrsdr.h by
open-coding at91sama5_get_ddram_size wherever it was called.
Suggested-by: Sascha Hauer
Signed-off-by: Ahmad Fatoum
---
arch/arm/boards/sama5d3_xplained/lowlevel.c | 4 +++-
arch/arm/boards/sama5d3xek/lowlevel.c | 4 +++-
arch/arm/boards/sama5d4_xplained/lowlevel.c | 4 +++-
arch/arm/boards/sama5d4ek/lowlevel.c | 4 +++-
arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h | 12
arch/arm/mach-at91/sama5d3_devices.c | 2 +-
arch/arm/mach-at91/sama5d4_devices.c | 2 +-
7 files changed, 14 insertions(+), 18 deletions(-)
diff --git a/arch/arm/boards/sama5d3_xplained/lowlevel.c
b/arch/arm/boards/sama5d3_xplained/lowlevel.c
index 92dd515ca64e..31c176a3a4c2 100644
--- a/arch/arm/boards/sama5d3_xplained/lowlevel.c
+++ b/arch/arm/boards/sama5d3_xplained/lowlevel.c
@@ -19,5 +19,7 @@ void __naked __bare_init barebox_arm_reset_vector(uint32_t
r0, uint32_t r1, uint
arm_setup_stack(SAMA5D3_SRAM_BASE + SAMA5D3_SRAM_SIZE - 16);
- barebox_arm_entry(SAMA5_DDRCS,
at91sama5_get_ddram_size(IOMEM(SAMA5D3_BASE_MPDDRC)), NULL);
+ barebox_arm_entry(SAMA5_DDRCS,
+ at91_get_ddram_size(IOMEM(SAMA5D3_BASE_MPDDRC), true),
+ NULL);
}
diff --git a/arch/arm/boards/sama5d3xek/lowlevel.c
b/arch/arm/boards/sama5d3xek/lowlevel.c
index 92dd515ca64e..31c176a3a4c2 100644
--- a/arch/arm/boards/sama5d3xek/lowlevel.c
+++ b/arch/arm/boards/sama5d3xek/lowlevel.c
@@ -19,5 +19,7 @@ void __naked __bare_init barebox_arm_reset_vector(uint32_t
r0, uint32_t r1, uint
arm_setup_stack(SAMA5D3_SRAM_BASE + SAMA5D3_SRAM_SIZE - 16);
- barebox_arm_entry(SAMA5_DDRCS,
at91sama5_get_ddram_size(IOMEM(SAMA5D3_BASE_MPDDRC)), NULL);
+ barebox_arm_entry(SAMA5_DDRCS,
+ at91_get_ddram_size(IOMEM(SAMA5D3_BASE_MPDDRC), true),
+ NULL);
}
diff --git a/arch/arm/boards/sama5d4_xplained/lowlevel.c
b/arch/arm/boards/sama5d4_xplained/lowlevel.c
index 168d424baee7..47cadfe6750c 100644
--- a/arch/arm/boards/sama5d4_xplained/lowlevel.c
+++ b/arch/arm/boards/sama5d4_xplained/lowlevel.c
@@ -19,5 +19,7 @@ void __naked __bare_init barebox_arm_reset_vector(uint32_t
r0, uint32_t r1, uint
arm_setup_stack(SAMA5D4_SRAM_BASE + SAMA5D4_SRAM_SIZE - 16);
- barebox_arm_entry(SAMA5_DDRCS,
at91sama5_get_ddram_size(IOMEM(SAMA5D4_BASE_MPDDRC)), NULL);
+ barebox_arm_entry(SAMA5_DDRCS,
+ at91_get_ddram_size(IOMEM(SAMA5D4_BASE_MPDDRC), true),
+ NULL);
}
diff --git a/arch/arm/boards/sama5d4ek/lowlevel.c
b/arch/arm/boards/sama5d4ek/lowlevel.c
index 168d424baee7..47cadfe6750c 100644
--- a/arch/arm/boards/sama5d4ek/lowlevel.c
+++ b/arch/arm/boards/sama5d4ek/lowlevel.c
@@ -19,5 +19,7 @@ void __naked __bare_init barebox_arm_reset_vector(uint32_t
r0, uint32_t r1, uint
arm_setup_stack(SAMA5D4_SRAM_BASE + SAMA5D4_SRAM_SIZE - 16);
- barebox_arm_entry(SAMA5_DDRCS,
at91sama5_get_ddram_size(IOMEM(SAMA5D4_BASE_MPDDRC)), NULL);
+ barebox_arm_entry(SAMA5_DDRCS,
+ at91_get_ddram_size(IOMEM(SAMA5D4_BASE_MPDDRC), true),
+ NULL);
}
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
index cc3affa17a61..b50c11b128bf 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
@@ -176,18 +176,6 @@ static inline u32 at91_get_ddram_size(void * __iomem base,
bool is_nb)
return size;
}
-#ifdef CONFIG_SOC_SAMA5
-static inline u32 at91sama5_get_ddram_size(void __iomem *base)
-{
- return at91_get_ddram_size(base, true);
-}
-#else
-static inline u32 at91sama5_get_ddram_size(void __iomem *base)
-{
- return 0;
-}
-#endif
-
#endif
#endif
diff --git a/arch/arm/mach-at91/sama5d3_devices.c
b/arch/arm/mach-at91/sama5d3_devices.c
index b61d2b309ce0..479e81f0f588 100644
--- a/arch/arm/mach-at91/sama5d3_devices.c
+++ b/arch/arm/mach-at91/sama5d3_devices.c
@@ -28,7 +28,7 @@
void at91_add_device_sdram(u32 size)
{
if (!size)
- size = at91sama5_get_ddram_size(IOMEM(SAMA5D3_BASE_MPDDRC));
+ size = at91_get_ddram_size(IOMEM(SAMA5D3_BASE_MPDDRC), true),
arm_add_mem_device("ram0", SAMA5_DDRCS, size);
add_mem_device("sram0", SAMA5D3_SRAM_BASE,
diff --git a/arch/arm/mach-at91/sama5d4_devices.c
b/arch/arm/mach-at91/sama5d4_devices.c
index 546d0888bfd8..4a6683981595 100644
--- a/arch/arm/mach-at91/sama5d4_devices.c
+++ b/arch/arm/mach-at91/sama5d4_devices.c
@@ -29,7 +29,7 @@
void at91_add_device_sdram(u32 size)
{
if (!size)
- size = at91sama5_get_ddram_size(IOMEM(SAMA5D4_BASE_MPDDRC));
+ size = at91_get_ddram_size(IOMEM(SAMA5D4_BASE_MPDDRC), true);
arm_add_mem_device("ram0", SAMA5_DDRCS
[PATCH v2 00/10] ARM: at91: misc fixes and cleanup
Changes since v1:
- Collected Sam's Test-by and Reviewed-by
- Included Sam's fix for the sama5d4 as patch 03
- moved debug_ll base address defaults to common/Kconfig
- above also got rid of a typo in the base address constant name
- added patches 06-09 which remove board-specific helpers as suggested
by Sascha in the review of the sama5d3 first stage patchset
- added patch 10 with a fix for a warning I ran into in the newly
ported clock drivers
Ahmad Fatoum (9):
ARM: at91: replace __raw_{readl,writel} of peripherals with
readl,writel
ARM: at91: debug_ll: make UART base address configurable
ARM: at91: fix at91sama5_get_ddram_size for sama5d4
ARM: at91: remove duplicate get_ddram_size code
ARM: at91: remove at91sam9g45_get_ddram_size helper
ARM: at91: remove at91sam9n12_get_ddram_size helper
ARM: at91: remove at91sam9x5_get_ddram_size helper
ARM: at91: remove at91sama5_get_ddram_size helper
clk: at91: fix warning about missing const-safety
Sam Ravnborg (1):
arm: sama5d4: fix stack setup
arch/arm/boards/at91rm9200ek/lowlevel.c | 40 -
arch/arm/boards/at91sam9m10g45ek/lowlevel.c | 5 +-
arch/arm/boards/at91sam9m10ihd/lowlevel.c | 5 +-
arch/arm/boards/at91sam9n12ek/lowlevel.c | 5 +-
arch/arm/boards/at91sam9x5ek/lowlevel.c | 4 +-
arch/arm/boards/pm9g45/lowlevel.c | 5 +-
arch/arm/boards/sama5d3_xplained/lowlevel.c | 4 +-
arch/arm/boards/sama5d3xek/lowlevel.c | 4 +-
arch/arm/boards/sama5d4_xplained/lowlevel.c | 6 +-
arch/arm/boards/sama5d4ek/lowlevel.c | 6 +-
arch/arm/mach-at91/Kconfig| 17
arch/arm/mach-at91/at91sam9g45_devices.c | 2 +-
arch/arm/mach-at91/at91sam9n12_devices.c | 2 +-
arch/arm/mach-at91/at91sam9x5_devices.c | 2 +-
.../include/mach/at91sam926x_board_init.h | 22 ++---
.../mach-at91/include/mach/at91sam9_ddrsdr.h | 89 +--
.../mach-at91/include/mach/at91sam9_sdramc.h | 4 +-
arch/arm/mach-at91/include/mach/debug_ll.h| 13 +--
arch/arm/mach-at91/include/mach/gpio.h| 57 ++--
arch/arm/mach-at91/sam9_smc.c | 58 ++--
arch/arm/mach-at91/sama5d3_devices.c | 2 +-
arch/arm/mach-at91/sama5d4_devices.c | 2 +-
arch/arm/mach-at91/setup.c| 4 +-
common/Kconfig| 21 +
drivers/clk/at91/clk-main.c | 3 +-
drivers/clocksource/timer-atmel-pit.c | 4 +-
drivers/mci/atmel-mci-regs.h | 4 +-
drivers/net/at91_ether.h | 4 +-
drivers/net/macb.h| 8 +-
drivers/pinctrl/pinctrl-at91.c| 28 +++---
drivers/spi/atmel_spi.h | 4 +-
drivers/usb/gadget/at91_udc.c | 86 +-
drivers/video/atmel_lcdfb.h | 4 +-
33 files changed, 223 insertions(+), 301 deletions(-)
--
2.20.1
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[PATCH v2 02/10] ARM: at91: debug_ll: make UART base address configurable
This is in line with other platforms such as i.MX, which allow
specifying a debug port. As we can't use port indices because
the UARTs aren't mapped consecutively, allow specifying a hex
base at configuration time.
A side effect of this patch is that sama5d4's HAVE_AT91_DBGU2
is now honored as well. Previously anything besides DBGU0
defaulted to DBGU1.
Fixes: 06a0773ee31 ("ARM: at91: add sama5d4 soc support #2")
Reviewed-by: Sam Ravnborg
Tested-by: Sam Ravnborg
[afa: moved base address defaults to common/Kconfig]
Signed-off-by: Ahmad Fatoum
---
arch/arm/mach-at91/Kconfig | 17 -
arch/arm/mach-at91/include/mach/debug_ll.h | 13 +++--
common/Kconfig | 21 +
3 files changed, 24 insertions(+), 27 deletions(-)
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index efed73827849..8e1bf0629ab7 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -1,14 +1,5 @@
if ARCH_AT91
-config HAVE_AT91_DBGU0
- bool
-
-config HAVE_AT91_DBGU1
- bool
-
-config HAVE_AT91_DBGU2
- bool
-
config HAVE_AT91_UTMI
bool
@@ -115,7 +106,6 @@ config SOC_AT91RM9200
config SOC_AT91SAM9260
bool
select SOC_AT91SAM9
- select HAVE_AT91_DBGU0
select HAS_MACB
help
Select this if you are using one of Atmel's AT91SAM9260, AT91SAM9XE
@@ -124,21 +114,18 @@ config SOC_AT91SAM9260
config SOC_AT91SAM9261
bool
select SOC_AT91SAM9
- select HAVE_AT91_DBGU0
help
Select this if you are using one of Atmel's AT91SAM9261 or
AT91SAM9G10 SoC.
config SOC_AT91SAM9263
bool
select SOC_AT91SAM9
- select HAVE_AT91_DBGU1
select HAS_MACB
select HAVE_AT91_LOAD_BAREBOX_SRAM
config SOC_AT91SAM9G45
bool
select SOC_AT91SAM9
- select HAVE_AT91_DBGU1
select HAS_MACB
help
Select this if you are using one of Atmel's AT91SAM9G45 family SoC.
@@ -147,7 +134,6 @@ config SOC_AT91SAM9G45
config SOC_AT91SAM9X5
bool
select SOC_AT91SAM9
- select HAVE_AT91_DBGU0
select HAS_MACB
select COMMON_CLK_OF_PROVIDER
help
@@ -160,7 +146,6 @@ config SOC_AT91SAM9X5
config SOC_AT91SAM9N12
bool
select SOC_AT91SAM9
- select HAVE_AT91_DBGU0
help
Select this if you are using Atmel's AT91SAM9N12 SoC.
@@ -213,14 +198,12 @@ config ARCH_AT91SAM9N12
config ARCH_SAMA5D3
bool "SAMA5D3x"
select SOC_SAMA5D3
- select HAVE_AT91_DBGU1
select HAS_MACB
select HAVE_MACH_ARM_HEAD
config ARCH_SAMA5D4
bool "SAMA5D4"
select SOC_SAMA5D4
- select HAVE_AT91_DBGU2
select HAS_MACB
select HAVE_MACH_ARM_HEAD
diff --git a/arch/arm/mach-at91/include/mach/debug_ll.h
b/arch/arm/mach-at91/include/mach/debug_ll.h
index fd26cae21ef2..b71393042463 100644
--- a/arch/arm/mach-at91/include/mach/debug_ll.h
+++ b/arch/arm/mach-at91/include/mach/debug_ll.h
@@ -9,13 +9,6 @@
#define __MACH_DEBUG_LL_H__
#include
-#include
-
-#ifdef CONFIG_HAVE_AT91_DBGU0
-#define UART_BASE AT91_BASE_DBGU0
-#else
-#define UART_BASE AT91_BASE_DBGU1
-#endif
#define ATMEL_US_CSR 0x0014
#define ATMEL_US_THR 0x001c
@@ -31,11 +24,11 @@
*/
static inline void PUTC_LL(char c)
{
- while (!(readl(UART_BASE + ATMEL_US_CSR) & ATMEL_US_TXRDY))
+ while (!(readl(CONFIG_DEBUG_AT91_UART_BASE + ATMEL_US_CSR) &
ATMEL_US_TXRDY))
barrier();
- writel(c, UART_BASE + ATMEL_US_THR);
+ writel(c, CONFIG_DEBUG_AT91_UART_BASE + ATMEL_US_THR);
- while (!(readl(UART_BASE + ATMEL_US_CSR) & ATMEL_US_TXEMPTY))
+ while (!(readl(CONFIG_DEBUG_AT91_UART_BASE + ATMEL_US_CSR) &
ATMEL_US_TXEMPTY))
barrier();
}
#endif
diff --git a/common/Kconfig b/common/Kconfig
index 7832df5c554f..2f30b2acf890 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -1168,6 +1168,13 @@ config DEBUG_RPI1_UART
Say Y here if you want low-level debugging support on
RaspberryPi 1 boards.
+config DEBUG_AT91_UART
+ bool "AT91 Debug UART"
+ depends on ARCH_AT91
+ help
+ Say Y here if you want barebox low-level debugging support
+ on AT91 based platforms.
+
config DEBUG_RPI2_3_UART
bool "RaspberryPi 2/3 PL011 UART"
depends on ARCH_BCM283X
@@ -1238,6 +1245,7 @@ config DEBUG_SOCFPGA_UART_CLOCK
help
Choose UART root clock.
+
config DEBUG_LAYERSCAPE_UART_PORT
int "Layerscape UART port selection"
depends on ARCH_LAYERSCAPE
@@ -1246,6 +1254,19 @@ config DEBUG_LAYERSCAPE_UART_PORT
Select the UART port number used for early debugging here. Port
numbers start counting from 1.
+config DEBUG_AT91_UART_BASE
+ hex "AT91 Debug UART Port Selection" if DEBUG_AT91_UART
+ default 0xfff
