[PATCH 1/3] net: designware: socfpga: fix phy setup for Arria10
Barebox-version of the Linux v5.2 patch:
40ae25505fe834648ce4aa70b073ee934942bfdb
net: stmmac: socfpga: fix phy and ptp_ref setup for Arria10/Stratix10
On the Arria10, Agilex, and Stratix10 SoC, there are a few differences from
the Cyclone5 and Arria5:
- The emac PHY setup bits are in separate registers.
- The PTP reference clock select mask is different.
- The register to enable the emac signal from FPGA is different.
Thus, this patch creates a separate function for setting the phy modes on
Arria10/Agilex/Stratix10. The separation is based a new DTS binding:
"altr,socfpga-stmmac-a10-s10".
Signed-off-by: Dinh Nguyen
Signed-off-by: David S. Miller
The new DTS binding is already part of v2019.10.0 and the driver doesn't
probe on Arria10 without the new binding introduced in this patch.
Signed-off-by: Steffen Trumtrar
---
drivers/net/designware.h | 1 +
drivers/net/designware_socfpga.c | 133 +++
2 files changed, 118 insertions(+), 16 deletions(-)
diff --git a/drivers/net/designware.h b/drivers/net/designware.h
index 305f674bf064..0a6a6bf1a497 100644
--- a/drivers/net/designware.h
+++ b/drivers/net/designware.h
@@ -35,6 +35,7 @@ struct dw_eth_dev {
struct dw_eth_drvdata {
bool enh_desc;
+ void *priv;
};
struct dw_eth_dev *dwc_drv_probe(struct device_d *dev);
diff --git a/drivers/net/designware_socfpga.c b/drivers/net/designware_socfpga.c
index 77157c2b511f..ce3ac38ebe87 100644
--- a/drivers/net/designware_socfpga.c
+++ b/drivers/net/designware_socfpga.c
@@ -14,11 +14,27 @@
#include
#include
#include
-#include
#include
#include "designware.h"
-#define SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK 0x0010
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
+#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB0
+#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB2
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK0x0003
+#define SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK 0x0010
+#define SYSMGR_GEN10_EMACGRP_CTRL_PTP_REF_CLK_MASK 0x0100
+
+#define SYSMGR_FPGAGRP_MODULE 0x0028
+#define SYSMGR_FPGAGRP_MODULE_EMAC 0x0004
+#define SYSMGR_FPGAINTF_EMAC_REG 0x0070
+#define SYSMGR_FPGAINTF_EMAC_BIT 0x1
+
+struct socfpga_dwc_dev;
+struct socfpga_dwmac_ops {
+ int (*set_phy_mode)(struct socfpga_dwc_dev *dwmac_priv);
+};
struct socfpga_dwc_dev {
struct dw_eth_dev *priv;
@@ -26,27 +42,36 @@ struct socfpga_dwc_dev {
u32reg_shift;
void __iomem *sys_mgr_base;
bool f2h_ptp_ref_clk;
+ const struct socfpga_dwmac_ops *ops;
};
-static int socfpga_dwc_set_phy_mode(struct socfpga_dwc_dev *dwc_dev)
+static int socfpga_set_phy_mode_common(int phymode, u32 *val)
{
- struct dw_eth_dev *eth_dev = dwc_dev->priv;
- int phymode = eth_dev->interface;
- u32 reg_offset = dwc_dev->reg_offset;
- u32 reg_shift = dwc_dev->reg_shift;
- u32 ctrl, val;
-
switch (phymode) {
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_ID:
- val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
+ *val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
break;
case PHY_INTERFACE_MODE_MII:
case PHY_INTERFACE_MODE_GMII:
case PHY_INTERFACE_MODE_SGMII:
- val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
+ *val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
break;
default:
+ return -EINVAL;
+ }
+ return 0;
+};
+
+static int socfpga_gen5_set_phy_mode(struct socfpga_dwc_dev *dwc_dev)
+{
+ struct dw_eth_dev *eth_dev = dwc_dev->priv;
+ int phymode = eth_dev->interface;
+ u32 reg_offset = dwc_dev->reg_offset;
+ u32 reg_shift = dwc_dev->reg_shift;
+ u32 ctrl, val;
+
+ if (socfpga_set_phy_mode_common(phymode, &val)) {
dev_err(ð_dev->netdev.dev, "bad phy mode %d\n", phymode);
return -EINVAL;
}
@@ -85,6 +110,54 @@ static int socfpga_dwc_set_phy_mode(struct socfpga_dwc_dev
*dwc_dev)
return 0;
}
+static int socfpga_gen10_set_phy_mode(struct socfpga_dwc_dev *dwc_dev)
+{
+ struct dw_eth_dev *eth_dev = dwc_dev->priv;
+ int phymode = eth_dev->interface;
+ u32 reg_offset = dwc_dev->reg_offset;
+ u32 reg_shift = dwc_dev->reg_shift;
+ u32 ctrl, val;
+
+ if (socfpga_set_phy_mode_common(phymode, &val)) {
+ dev_err(ð_dev->netdev.dev, "bad phy mode %d\n", phymode);
+ return -EINVAL;
+ }
+
+ /* Assert reset to the enet controller before changing the phy m
[PATCH 3/3] ARM: socfpga: defconfig: enable state_drv
The Arria10 DTS uses the state framework. Enable the driver so it gets probed. Signed-off-by: Steffen Trumtrar --- arch/arm/configs/socfpga-arria10_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/socfpga-arria10_defconfig b/arch/arm/configs/socfpga-arria10_defconfig index ae420c1dd290..e47a0ab1836d 100644 --- a/arch/arm/configs/socfpga-arria10_defconfig +++ b/arch/arm/configs/socfpga-arria10_defconfig @@ -74,6 +74,7 @@ CONFIG_MCI=y CONFIG_MCI_STARTUP=y CONFIG_MCI_MMC_BOOT_PARTITIONS=y CONFIG_MCI_DW=y +CONFIG_STATE_DRV=y # CONFIG_PINCTRL is not set CONFIG_FS_TFTP=y CONFIG_FS_NFS=y -- 2.23.0 ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH 2/3] ARM: socfpga: cyclone5-system-manager.h: remove defines
These defines are common for arria10 and cyclone5. Instead of having them here, they are moved to drivers/net/designware_socfpga.c. Signed-off-by: Steffen Trumtrar --- .../include/mach/cyclone5-system-manager.h| 11 --- 1 file changed, 11 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/cyclone5-system-manager.h b/arch/arm/mach-socfpga/include/mach/cyclone5-system-manager.h index 24f52effd886..7cec60937b84 100644 --- a/arch/arm/mach-socfpga/include/mach/cyclone5-system-manager.h +++ b/arch/arm/mach-socfpga/include/mach/cyclone5-system-manager.h @@ -57,15 +57,4 @@ void socfpga_sysmgr_pinmux_init(unsigned long *sys_mgr_init_table, int num); #define SYSMGR_FPGAINTF_NAND (1<<4) #define SYSMGR_FPGAINTF_SDMMC (1<<5) -/* Enumeration: sysmgr::emacgrp::ctrl::physel::enum*/ -#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0 -#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1 -#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2 -#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0 -#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2 -#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x0003 - -#define SYSMGR_FPGAGRP_MODULE 0x0028 -#define SYSMGR_FPGAGRP_MODULE_EMAC 0x0004 - #endif /* _SYSTEM_MANAGER_H_ */ -- 2.23.0 ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: readling, ctrl-u is not working like linux console
On Wed, Oct 16, 2019 at 09:47:05PM +0800, duhuanpeng wrote: > > > > FWIW, in bash on both my tty2 and urxvt, Ctrl-U clears the whole line. > > did you try to move your cursor in the middle of a line. Ah, I misread your first mail. Yes, my bash only discards characters before the cursor until the start of the line. - Roland > > I guess my bash use this keybinds: > > [1] > https://www.gnu.org/software/bash/manual/bash.html#Bindable-Readline-Commands > > 8.4.4 Killing And Yanking > kill-line (C-k) > Kill the text from point to the end of the line. > > backward-kill-line (C-x Rubout) > Kill backward from the cursor to the beginning of the current line. > > unix-line-discard (C-u) > Kill backward from the cursor to the beginning of the current line. > > kill-whole-line () > Kill all characters on the current line, no matter where point is. By > default, this is unbound. > > > Regards, > duhuanpeng > > ___ > barebox mailing list > barebox@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/barebox > -- Roland Hieber | r.hie...@pengutronix.de | Pengutronix e.K. | https://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim | Phone: +49-5121-206917-5086 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: MFGTools from NXP
Yes I have tried with 2019.01.0 barebox but no change. On linux I cannot even connect with PUTTY even though /dev/ttyACM0 is present. On Windows at least I can connect via PUTTY On both OSes fastboot does not list any device. But the board is detected in device manager/dmesg. Best regards, Mihaita Ivascu On Wed, Oct 16, 2019 at 2:46 PM Ahmad Fatoum wrote: > > On 10/16/19 2:44 PM, Mihaita Ivascu wrote: > > 2018.04.0 > > I've v2019.09.0 and did the same steps you described and it works for me. > Can you try with a newer version? > > > > > On Wed, Oct 16, 2019 at 2:41 PM Ahmad Fatoum > > wrote: > >> > >> On 10/16/19 2:35 PM, Mihaita Ivascu wrote: > >>> No it does not. Still no devices listed. > >> > >> Strange. What barebox version? > >> > >>> > >>> Thanks, > >>> Mihaita > >>> > >>> On Wed, Oct 16, 2019 at 1:36 PM Ahmad Fatoum > >>> wrote: > > On 10/16/19 1:28 PM, Mihaita Ivascu wrote: > > On Wed, Oct 16, 2019 at 11:53 AM Ahmad Fatoum > > wrote: > >> > >> > >> On 10/16/19 11:48 AM, Mihaita Ivascu wrote: > >>> On Wed, Oct 16, 2019 at 11:26 AM Ahmad Fatoum > >>> > > wrote: > > On 10/16/19 11:21 AM, Mihaita Ivascu wrote: > > Hello, > > > >Thanks for your answer. Yes i am able to connect via PUTTY to the > > target. > >Then I should use some adb commands in order to push the new > > barebox/firmware ? do you know where I could find some examples? > > fastboot device -l works normally on Linux. You need to check what > you > > need > to do on Windows to do the same. You should only need the Fastboot > > utility > for this. > > >>> [mi] Yes I have both fastboot and adb installed on both Windows and > >>> Linux machines. In both cases it does not list any device. > >>>The board is detected as fastboot android is windows device > >>> manager. But the fastboot and adb does not list it. same for Linux. > >>> Please see attachment > >> > >> Let's focus on Linux. You don't see a device there? > >> What does barebox say? Does it say 'multi_bind: creating Fastboot > > function'? > >> What does you Linux host's dmesg say? > >> > > > > barebox@Phytec phyCORE-i.MX6 Ultra Lite SOM:/ usbgadget -aA > > udc0: registering UDC driver [g_multi] > > multi_bind: creating Fastboot function > > multi_bind: creating ACM function > > g_multi usbgadget: Multifunction Composite Gadget > > g_multi usbgadget: userspace failed to provide iSerialNumber > > g_multi usbgadget: g_multi ready > > barebox@Phytec phyCORE-i.MX6 Ultra Lite SOM:/ g_multi usbgadget: > > high-speed > > config #1: Multifunction Composite Gadget > > > > dmesg: > > > > [ 25.602275] usb 1-1.3: USB disconnect, device number 3 > > [ 28.359930] usb 1-1.3: new high-speed USB device number 5 using > > ehci-pci > > [ 28.452971] usb 1-1.3: New USB device found, idVendor=1d6b, > > idProduct=0104 > > [ 28.452976] usb 1-1.3: New USB device strings: Mfr=0, Product=2, > > SerialNumber=0 > > [ 28.452980] usb 1-1.3: Product: Phytec phyCORE-i.MX6 Ultra Lite SOM > > [ 28.457925] cdc_acm 1-1.3:1.1: ttyACM0: USB ACM device > > > > > > So I see the device on Linux. But fastboot does not list any device on > > Linux. > > sudo doesn't change this? > > > > >> > > > > >Also I have a question: purpose of this activity is for me to be > > able to flash some imx6ul boards that have no firmware: no barebox. > >So I know hardware config for the port is otg mode but as I have > > no > > barebox running them before I am wondering if I will be able to > > connect via PUTTY if I do not set the ACM gadget from barebox? > > Check the Embest MarS board's environment in barebox master. It sets > up > a fastboot gadget automatically on boot from imx-usb-loader. > You can adjust it to your liking. > >>> > >>> [mi] I was not able to find any docs about this board. I will keep > >>> searching/asking in the nxp community. If you have already ahve any > >>> files related to it would be helpful. Thanks > >> > >> It's in the barebox next branch (not master, sorry), see here: > >> > > https://github.com/saschahauer/barebox/blob/next/arch/arm/boards/embest-marsboard/defaultenv-mars/init/fastboot > >> > >> You can copy and adjust the environment setup for your board. > >> > > Cheers > Ahmad > > > > > Thanks, > > Mihaita > > > > On Wed, Oct 16, 2019 at 10:51 AM Ahmad Fatoum > > > > wrote: > >> > >> On 10/16/19 10:40 AM, Mihaita Ivascu wrote: > >>> Hello again,
