Re: qemu arm vexpress / virt32 support
Thanks, -next works! Also since 2020.10.0 cut right after I wrote this email, I just tested head (4cce60b7fe2798e81b04c5d9ad79dc9b443635a8) and the 2020.10.0 release. Both work. I no longer know what githash I was on at the time of my original email. FWIW, I think in my previous testing 2019.12.0 and 2019.11.0 didn't work, but 2019.10.0 did. Though that was via buildroot integration, and I'm honestly not sure if they apply any patches. At any rate, I'll stick to 2020.10.0 and see how that goes. Wes On Tue, Jan 14, 2020 at 3:06 PM Lucas Stach wrote: > > Hi Wesley, > > Am Dienstag, den 14.01.2020, 12:40 -0500 schrieb Wesley Chow: > > I see here that vexpress is supposed to be the 32 bit arm config of choice: > > > > http://lists.infradead.org/pipermail/barebox/2017-November/031597.html > > > > Is this still the case, ie there's no interest in supporting the 32 bit > > virt? > > I wouldn't say there is no interest in supporting the virt platform in > Barebox. It's true that none of the current developers have a strong > interest in the virt platform. > > If someone from the community shows an interest and implements all the > virtio infrastructure and related drivers, I see no reason why those > patches wouldn't be considered for mainline inclusion. > > I guess that's an elaborate way to say: patches welcome! > > > > > Using vexpress, I get this: > > > > ARCH=arm CROSS_COMPILE=/usr/bin/arm-linux-gnueabihf- make vexpress_defconfig > > ... > > $ qemu-system-arm -M vexpress-a9 -cpu cortex-a9 -m 256 -nographic > > -kernel images/barebox-vexpress-ca9.img > > pulseaudio: set_sink_input_volume() failed > > pulseaudio: Reason: Invalid argument > > pulseaudio: set_sink_input_mute() failed > > pulseaudio: Reason: Invalid argument > > PFLASH: Possible BUG - Write block confirm > > > > (then qemu exits) > > > > This is with barebox head, qemu 2.11, but same results with qemu 4.2.0 > > too. I'm new to barebox -- is this the correct invocation? > > I've just built barebox -next and using qemu 4.1.1 the documented > (Documentation/boards/arm-qemu-vexpress.rst) commandline > "qemu-system-arm -m 1024M -machine vexpress-a9 -cpu cortex-a9 > -nographic -no-reboot -kernel images/barebox-vexpress-ca9.img" yields a > working Barebox for me. > > Regards, > Lucas > ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [RFC 2/5] WIP: MIPS: implement dma mapping functions
On Mon, 13 Jan 2020 09:26:36 +0100
Oleksij Rempel wrote:
> On 09.01.20 08:28, Antony Pavlov wrote:
> > TODO: fix warnings
> >
> > arch/mips/include/asm/dma-mapping.h: In function ‘dma_free_coherent’:
> > arch/mips/include/asm/dma-mapping.h:31:21: warning: passing argument 1 of
> > ‘phys_to_virt’
> > makes integer from pointer without a cast [-Wint-conversion]
> > free(phys_to_virt(vaddr));
> > ^
> > In file included from include/common.h:33:0,
> > from drivers/net/e1000/main.c:32:
> > arch/mips/include/asm/io.h:40:21: note: expected ‘long unsigned int’ but
> > argument is of type ‘void *’
> > static inline void *phys_to_virt(unsigned long address)
> > ^~~~
> >
> > Signed-off-by: Antony Pavlov
> > Signed-off-by: Peter Mamonov
> > ---
> > arch/mips/include/asm/dma-mapping.h | 2 +-
> > arch/mips/lib/dma-default.c | 22 --
> > 2 files changed, 21 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/mips/include/asm/dma-mapping.h
> > b/arch/mips/include/asm/dma-mapping.h
> > index c71a087038..5013e7b369 100644
> > --- a/arch/mips/include/asm/dma-mapping.h
> > +++ b/arch/mips/include/asm/dma-mapping.h
> > @@ -28,7 +28,7 @@ static inline void dma_free_coherent(void *vaddr,
> > dma_addr_t dma_handle,
> > size_t size)
> > {
> > if (IS_ENABLED(CONFIG_MMU))
> > - free((void *)CKSEG0ADDR(vaddr));
> > + free(phys_to_virt(vaddr));
> > else
> > free(vaddr);
> > }
> > diff --git a/arch/mips/lib/dma-default.c b/arch/mips/lib/dma-default.c
> > index fbe627c24c..40caf6f91b 100644
> > --- a/arch/mips/lib/dma-default.c
> > +++ b/arch/mips/lib/dma-default.c
> > @@ -8,9 +8,11 @@
> >
> > #if defined(CONFIG_CPU_MIPS32) || \
> > defined(CONFIG_CPU_MIPS64)
> > -static inline void __dma_sync_mips(unsigned long addr, size_t size,
> > +static inline void __dma_sync_mips(dma_addr_t _addr, size_t size,
> >enum dma_data_direction direction)
> > {
> > + void *addr = phys_to_virt(_addr);
> > +
> > switch (direction) {
> > case DMA_TO_DEVICE:
> > dma_flush_range(addr, addr + size);
> > @@ -29,7 +31,7 @@ static inline void __dma_sync_mips(unsigned long addr,
> > size_t size,
> > }
> > }
> > #else
> > -static inline void __dma_sync_mips(void *addr, size_t size,
> > +static inline void __dma_sync_mips(dma_addr_t addr, size_t size,
> > enum dma_data_direction direction)
> > {
> > }
> > @@ -46,3 +48,19 @@ void dma_sync_single_for_device(dma_addr_t address,
> > size_t size,
> > {
> > __dma_sync_mips(address, size, dir);
> > }
> > +
> > +dma_addr_t dma_map_single(struct device_d *dev, void *ptr, size_t size,
> > + enum dma_data_direction dir)
> > +{
> > + unsigned long addr = virt_to_phys(ptr);
> > +
> > + dma_sync_single_for_device(addr, size, dir);
>
> Hm.. i was thinking Hit Invalidate D instruction works with Virtual
> addresses. Are you
> sure we need to use virt_to_phys() here?
dma_sync_single_for_device() is a barebox-wide function (see include/dma.h).
The dma_sync_single_for_device() 1st argument type is dma_addr_t (physical
address).
So virt_to_phys() conversion is necessary here.
> > +
> > + return addr;
> > +}
> > +
> > +void dma_unmap_single(struct device_d *dev, dma_addr_t addr, size_t size,
> > + enum dma_data_direction dir)
> > +{
> > + dma_sync_single_for_cpu(addr, size, dir);
> > +}
> >
>
> Kind regards,
> Oleksij Rempel
>
> --
> Pengutronix e.K. | |
> Industrial Linux Solutions | http://www.pengutronix.de/ |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0|
> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
--
Best regards,
Antony Pavlov
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Re: qemu arm virt64 hangs
Hi Wesley, Am Dienstag, den 14.01.2020, 12:36 -0500 schrieb Wesley Chow: > hi all! > > 64 bit virt doesn't appear to be working. > > $ ARCH=arm CROSS_COMPILE=/usr/bin/aarch64-linux-gnu- make > qemu_virt64_defconfig > ... > $ qemu-system-aarch64 -M virt -cpu cortex-a57 -nographic -kernel > barebox > > (qemu hangs) > > I see here that at some point aarch64 had issues, but do these remain > unresolved? https://www.spinics.net/lists/u-boot-v2/msg33882.html I've just sent a patch to at least solve the stack issues discussed in this thread. Unfortunately this doesn't yield a completely working Barebox for me. I get the following output before things go downhill in a data abort: barebox 2019.12.0-00296-g6b1cae953fba #370 Tue Jan 14 21:18:14 CET 2020 Board: ARM QEMU virt64 Regards, Lucas ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH] ARM: qemu-virt64: convert to assembly entry
The C entry function isn't naked, so tries to push to the stack
in the function prologue. This doesn't work on QEMU where there
is no valid SP on entry. Convert the lowlevel entry to the
assembly facilities provided for this case.
Signed-off-by: Lucas Stach
---
arch/arm/boards/qemu-virt64/Makefile| 2 +-
arch/arm/boards/qemu-virt64/lowlevel.c | 4 +++-
arch/arm/boards/qemu-virt64/lowlevel_init.S | 12
3 files changed, 16 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/boards/qemu-virt64/lowlevel_init.S
diff --git a/arch/arm/boards/qemu-virt64/Makefile
b/arch/arm/boards/qemu-virt64/Makefile
index e35460754898..b394dde0a1fe 100644
--- a/arch/arm/boards/qemu-virt64/Makefile
+++ b/arch/arm/boards/qemu-virt64/Makefile
@@ -1,3 +1,3 @@
obj-y += init.o
-lwl-y += lowlevel.o
+lwl-y += lowlevel.o lowlevel_init.o
bbenv-$(CONFIG_DEFAULT_ENVIRONMENT_GENERIC) += defaultenv-qemu-virt64
diff --git a/arch/arm/boards/qemu-virt64/lowlevel.c
b/arch/arm/boards/qemu-virt64/lowlevel.c
index 629e2e9f6ecf..fcb052369abc 100644
--- a/arch/arm/boards/qemu-virt64/lowlevel.c
+++ b/arch/arm/boards/qemu-virt64/lowlevel.c
@@ -10,7 +10,9 @@
#include
#include
-void barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
+void qemu_virt64_start(uint32_t, uint32_t, uint32_t);
+
+void noinline qemu_virt64_start(uint32_t r0, uint32_t r1, uint32_t r2)
{
arm_cpu_lowlevel_init();
arm_setup_stack(0x4000 + SZ_2G - SZ_16K);
diff --git a/arch/arm/boards/qemu-virt64/lowlevel_init.S
b/arch/arm/boards/qemu-virt64/lowlevel_init.S
new file mode 100644
index ..1967fadb6cbe
--- /dev/null
+++ b/arch/arm/boards/qemu-virt64/lowlevel_init.S
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#include
+#include
+
+/* The DRAM is already setup */
+#define STACK_TOP 0x8000
+
+ENTRY_PROC(barebox_arm_reset_vector)
+ mov x0, #STACK_TOP
+ mov sp, x0
+ b qemu_virt64_start
+ENTRY_PROC_END(barebox_arm_reset_vector)
--
2.24.1
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qemu arm virt64 hangs
hi all! 64 bit virt doesn't appear to be working. $ ARCH=arm CROSS_COMPILE=/usr/bin/aarch64-linux-gnu- make qemu_virt64_defconfig ... $ qemu-system-aarch64 -M virt -cpu cortex-a57 -nographic -kernel barebox (qemu hangs) I see here that at some point aarch64 had issues, but do these remain unresolved? https://www.spinics.net/lists/u-boot-v2/msg33882.html I'm new to barebox, so apologies if I did something boneheaded. Thanks, Wes ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [RFC PATCH 0/7] usb: dwc2 host driver
On Tue, Jan 14, 2020 at 03:27:04PM +0100, Sascha Hauer wrote: > Hi Jules, > > On Tue, Jan 14, 2020 at 02:21:05PM +0100, Jules Maselbas wrote: > > Hi Sascha, > > > > I've been working on a driver for the dwc2 otg controller, for both host > > and device mode. Like you I've started from U-Boot driver and I mixed > > it with some part from Linux. For instance I've removed the register > > structs and I've been using the same defines for register bit-fields as > > in Linux. > > > > I would like to share my version of the host driver, as the gadget driver > > one still requires some cleanup. This series is not to be applied on the > > driver you proposed. However I am willing to propose a new series that can > > be applied on the driver you proposed. What do you think? > > The dwc2 driver was a quick shot, I am all in for improvements. Removing > the register structs is very nice and I would be interested in gadget > support as well. The gadget support is almost ready, I got the dfu gadget working. :) > What SoC are you using the driver on? I am using this driver on our custom SoC, the Kalray Coolidge MPPA (k1c). I didn't tried on other SoC. > I am not sure if it makes sense to rebase your patches on my driver. If > you can convince me that yours is better then we could just remove mine > and merge yours instead. I don't have a strong argument in favor of my version. Except that I have already made some changes over the original U-Boot version: I've tried to improve the roothub interface making it easier to decode new requests. I have removed the memcpy done in transfer_chunk between the usb data buffer and the dma buffer :/ However this mean that all buffer used for usb tranfert must be dma capable. Not all usb transfers use dma_alloc for it's buffers but sometime they are allocated on the stack, this can be problematic if the stack cannot be used by DMA. I also have fixed an error in the handling of the toggle bit, but I think the solution is a bit hacky. I think the driver should rather use the toggle bit stored in the usb_device structure, but this will require more rework. If theses changes make sense then let's use this version. Best, Jules > Sascha > > -- > Pengutronix e.K. | | > Steuerwalder Str. 21 | http://www.pengutronix.de/ | > 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH] pinctrl-single: Handle "pinctrl-single, function-mask" dt property
From: Siméon Marijon
Implement linux behavior regarding "pinctrl-single,function-mask" and
"pinctrl-single,bits".
It allows multiple pins control per register.
(linux sha1: 4e7e8017a80e1810100c9b416b86e3baef900285)
Signed-off-by: Simeon Marijon
---
drivers/pinctrl/pinctrl-single.c | 81 ++--
1 file changed, 62 insertions(+), 19 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index 3c581ed5d..d4f411b4a 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -29,7 +29,13 @@ struct pinctrl_single {
struct pinctrl_device pinctrl;
unsigned (*read)(void __iomem *reg);
void (*write)(unsigned val, void __iomem *reg);
- unsigned width;
+ unsigned int width;
+ unsigned int fmask;
+ unsigned int fshift;
+ unsigned int fmax;
+
+ bool bits_per_mux;
+ unsigned int bits_per_pin;
};
static unsigned __maybe_unused pcs_readb(void __iomem *reg)
@@ -66,27 +72,47 @@ static int pcs_set_state(struct pinctrl_device *pdev,
struct device_node *np)
{
struct pinctrl_single *pcs = container_of(pdev, struct pinctrl_single,
pinctrl);
unsigned size = 0, index = 0;
+ unsigned int offset, val, rows, mask, reg, i;
const __be32 *mux;
dev_dbg(pcs->pinctrl.dev, "set state: %s\n", np->full_name);
-
- mux = of_get_property(np, "pinctrl-single,pins", );
-
- size /= sizeof(*mux); /* Number of elements in array */
-
- if (!mux || !size || (size & 1)) {
- dev_err(pcs->pinctrl.dev, "bad data for mux %s\n",
- np->full_name);
- return -EINVAL;
- }
-
- while (index < size) {
- unsigned offset, val;
-
- offset = be32_to_cpup(mux + index++);
- val = be32_to_cpup(mux + index++);
-
- pcs->write(val, pcs->base + offset);
+ if (pcs->bits_per_mux) {
+ mux = of_get_property(np, "pinctrl-single,bits", );
+ if (size % 3 != 0)
+ dev_err(pcs->pinctrl.dev,
+ "invalid args_count for spec: %u\n", size);
+
+ size /= sizeof(*mux); /* Number of elements in array */
+ rows = size / 3;
+
+ for (i = 0; i < rows; i++) {
+ offset = be32_to_cpup(mux + index++);
+ mask = be32_to_cpup(mux + index++);
+ val = be32_to_cpup(mux + index++);
+ reg = pcs->read(pcs->base + offset);
+ reg &= ~mask;
+ reg |= val;
+ pcs->write(reg, pcs->base + offset);
+ }
+ } else {
+ mux = of_get_property(np, "pinctrl-single,pins", );
+
+ size /= sizeof(*mux); /* Number of elements in array */
+
+ if (!mux || !size || (size & 1)) {
+ dev_err(pcs->pinctrl.dev, "bad data for mux %s\n",
+ np->full_name);
+ return -EINVAL;
+ }
+
+ while (index < size) {
+ unsigned int offset, val;
+
+ offset = be32_to_cpup(mux + index++);
+ val = be32_to_cpup(mux + index++);
+
+ pcs->write(val, pcs->base + offset);
+ }
}
return 0;
@@ -137,6 +163,23 @@ static int pcs_probe(struct device_d *dev)
goto out;
}
+ ret = of_property_read_u32(np, "pinctrl-single,function-mask",
+ >fmask);
+ if (!ret) {
+ pcs->fshift = __ffs(pcs->fmask);
+ pcs->fmax = pcs->fmask >> pcs->fshift;
+ } else {
+ /* If mask property doesn't exist, function mux is invalid. */
+ pcs->fmask = 0;
+ pcs->fshift = 0;
+ pcs->fmax = 0;
+ }
+
+ pcs->bits_per_mux =
+ of_property_read_bool(np, "pinctrl-single,bit-per-mux");
+ if (pcs->bits_per_mux)
+ pcs->bits_per_pin = fls(pcs->fmask);
+
ret = pinctrl_register(>pinctrl);
if (ret)
goto out;
--
2.15.0.276.g89ea799
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Re: [RFC PATCH 0/7] usb: dwc2 host driver
Hi Jules, On Tue, Jan 14, 2020 at 02:21:05PM +0100, Jules Maselbas wrote: > Hi Sascha, > > I've been working on a driver for the dwc2 otg controller, for both host > and device mode. Like you I've started from U-Boot driver and I mixed > it with some part from Linux. For instance I've removed the register > structs and I've been using the same defines for register bit-fields as > in Linux. > > I would like to share my version of the host driver, as the gadget driver > one still requires some cleanup. This series is not to be applied on the > driver you proposed. However I am willing to propose a new series that can > be applied on the driver you proposed. What do you think? The dwc2 driver was a quick shot, I am all in for improvements. Removing the register structs is very nice and I would be interested in gadget support as well. What SoC are you using the driver on? I am not sure if it makes sense to rebase your patches on my driver. If you can convince me that yours is better then we could just remove mine and merge yours instead. Sascha -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
barebox-2020.01.0
Hi All, We have the first release in this decade ;) >From the amount of patches it seems most of the work for this release has gone into the SDHCI driver. A good bunch of the different implementations for the same functionalities has been merged to a common code base. Other than that Layerscape now has PCIe support, there are some more Layerscape improvements as well. As usual, see below for more details about the changes in this release. Have Fun! Sascha Ahmad Fatoum (42): ARM: i.MX6: Embedsky E9: remove inaccurate comment ARM: i.MX6: sabresd: remove inaccurate comment watchdog: always populate watchdog priority from device tree if possible watchdog: implement generic support for .running device parameter watchdog: imxwd: support .running device parameter on i.MX2+ watchdog: f71808e: support .running device parameter ARM: dts: stm32mp: move alias to SoC device tree ARM: stm32mp157c-dk2: add optional DEBUG_LL print to entry point mfd: stpmic1: use register define from header watchdog: stm32_iwdg: return -ENOSYS on attempt to disable i2c: stm32: use device_reset_us helper instead of open-coding Documentation: boards: stm32mp: document boot error LED ARM: stm32mp: add helper for querying ram size ARM: stm32mp: add basic DDR controller driver ARM: stm32mp: add stm32mp_cpu_lowlevel_init with stack set up ARM: stm32mp: dk2: don't hard-code memory size nvmem: bsec: fix typo in function name (s/st32/stm32/) ARM: psci: factor out smc command into commands/ ARM: psci: properly wire in command help commands: psci: make locally-used function static commands: smc: verify PSCI_POWER_ON with interprocessor handshake commands: smc: make command usable when ARM_PSCI is undefined mci: dove: fix dereference of nullable pointer ARM: cpu: dtb: remove unused declaration remoteproc: register a device for new remoteproc instances remoteproc: add support for starting st,stm32mp1-m4 watchdog: stm32_iwdg: explicitly set .running to UNSUPPORTED scripts: imx: report file where error occurred net: designware: eqos: remove done TODO param: add dev_add_param_tristate(_ro) helpers watchdog: core: use new dev_add_param_tristate helper for .running param images: i.MX: rearrange image rules in preparation for boilerplate removal efi: add and use new efi_device_has_guid helper driver: add missing parentheses around macro argument efi: fix off-by-one in mem_malloc_init(..., end) x86: efi: lds: don't discard any relocation sections PCI: add driver_data member to struct pci_device_id PCI: copy over some Linux PCI helpers efi: turn set of defines into enumerations serial: add support for PCI NS16550 UARTs bus: efi: add basic ACPI bus infrastructure misc: add ACPI test driver Andrey Smirnov (13): ARM: VFxxx: Display UID information on boot mci: imx-esdhc: Drop unnecessary type conversion mci: imx-esdhc: Drop unused type definition mci: imx-esdhc: Drop extra helper varaible mci: imx-esdhc-pbl: Don't setup DMA registers mci: imx-esdhc-pbl: Share initialization code mci: imx-esdhc-pbl: Drop 'wrap_wml' flag mci: imx-esdhc-pbl: Share IO accessors with regular driver mci: imx-esdhc-pbl: Use sdhci_transfer_data() mci: imx-esdhc-pbl: Use sdhci_set_cmd_xfer_mode() mci: imx-esdhc: Share code for esdhc_(setup|do)_data operations mci: imx-esdhc: Introduce esdhc_poll() mci: imx-esdhc: Share code for esdhc_send_cmd() Antony Pavlov (1): i2c: gpio: use of_get_named_gpio() instead of of_get_named_gpio_flags() Clement Leger (1): mtd: spi-nor: Add support for is25lp01g Du Huanpeng (1): MIPS: Makefile: minor codingstyle fix Florian Klink (4): scripts: use #!/usr/bin/env bash shebang instead of #!/bin/bash dts/scripts: use #!/usr/bin/env bash shebang instead of #!/bin/bash docs: use #!/usr/bin/env bash shebang instead of #!/bin/bash docs: use #!/usr/bin/env python shebang instead of #!/usr/bin/python Lucas Stach (58): ARM: zynq: zedboard: enable MACB driver in defconfig ARM: zynq: add trivial image build mechanism ARM: zynq: use getopt in zynq_mkimage ARM: zynq: move header generation to zynq_mkimage ARM: zynq: add size check in zynq_mkimage ARM: zynq: zedboard: provide DTB net: macb: handle more clocks net: macb: add Zynq compatible ARM: zynq: move clock controller driver to drivers/clk clk: zynq: use base address of clock controller clk: zynq: improve PLL enable handling clk: zynq: fix up address from DT clk: zynq: partially sync with Linux ARM: zynq: switch to DT based probing clk: zynq: remove clkdevs ARM: zynq: switch to
[RFC PATCH 3/7] usb: dwc2: Dynamic fifo size support from Linux
Signed-off-by: Jules Maselbas
---
drivers/usb/dwc2/host.c | 146 ++--
drivers/usb/dwc2/regs.h | 8 ---
2 files changed, 124 insertions(+), 30 deletions(-)
diff --git a/drivers/usb/dwc2/host.c b/drivers/usb/dwc2/host.c
index a1f2e3ea1..84eb9b627 100644
--- a/drivers/usb/dwc2/host.c
+++ b/drivers/usb/dwc2/host.c
@@ -437,6 +437,129 @@ int dwc2_submit_int_msg(struct usb_device *udev, unsigned
long pipe,
}
}
+/*
+ * dwc2_calculate_dynamic_fifo() - Calculates the default fifo size
+ * For system that have a total fifo depth that is smaller than the default
+ * RX + TX fifo size.
+ *
+ * @dwc2: Programming view of DWC_otg controller
+ */
+static void dwc2_calculate_dynamic_fifo(struct dwc2 *dwc2)
+{
+ struct dwc2_core_params *params = >params;
+ struct dwc2_hw_params *hw = >hw_params;
+ u32 rxfsiz, nptxfsiz, ptxfsiz, total_fifo_size;
+
+ total_fifo_size = hw->total_fifo_size;
+ rxfsiz = params->host_rx_fifo_size;
+ nptxfsiz = params->host_nperio_tx_fifo_size;
+ ptxfsiz = params->host_perio_tx_fifo_size;
+
+ /*
+* Will use Method 2 defined in the DWC2 spec: minimum FIFO depth
+* allocation with support for high bandwidth endpoints. Synopsys
+* defines MPS(Max Packet size) for a periodic EP=1024, and for
+* non-periodic as 512.
+*/
+ if (total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)) {
+ /*
+* For Buffer DMA mode/Scatter Gather DMA mode
+* 2 * ((Largest Packet size / 4) + 1 + 1) + n
+* with n = number of host channel.
+* 2 * ((1024/4) + 2) = 516
+*/
+ rxfsiz = 516 + hw->host_channels;
+
+ /*
+* min non-periodic tx fifo depth
+* 2 * (largest non-periodic USB packet used / 4)
+* 2 * (512/4) = 256
+*/
+ nptxfsiz = 256;
+
+ /*
+* min periodic tx fifo depth
+* (largest packet size*MC)/4
+* (1024 * 3)/4 = 768
+*/
+ ptxfsiz = 768;
+ }
+
+ params->host_rx_fifo_size = rxfsiz;
+ params->host_nperio_tx_fifo_size = nptxfsiz;
+ params->host_perio_tx_fifo_size = ptxfsiz;
+
+ /*
+* If the summation of RX, NPTX and PTX fifo sizes is still
+* bigger than the total_fifo_size, then we have a problem.
+*
+* We won't be able to allocate as many endpoints. Right now,
+* we're just printing an error message, but ideally this FIFO
+* allocation algorithm would be improved in the future.
+*
+* FIXME improve this FIFO allocation algorithm.
+*/
+ if (unlikely(total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)))
+ dwc2_err(dwc2, "invalid fifo sizes\n");
+}
+
+static void dwc2_config_fifos(struct dwc2 *dwc2)
+{
+ struct dwc2_core_params *params = >params;
+ u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz;
+
+ if (!params->enable_dynamic_fifo)
+ return;
+
+ dwc2_calculate_dynamic_fifo(dwc2);
+
+ /* Rx FIFO */
+ grxfsiz = dwc2_readl(dwc2, GRXFSIZ);
+ dwc2_dbg(dwc2, "initial grxfsiz=%08x\n", grxfsiz);
+ grxfsiz &= ~GRXFSIZ_DEPTH_MASK;
+ grxfsiz |= params->host_rx_fifo_size <<
+ GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK;
+ dwc2_writel(dwc2, grxfsiz, GRXFSIZ);
+ dwc2_dbg(dwc2, "new grxfsiz=%08x\n", dwc2_readl(dwc2, GRXFSIZ));
+
+ /* Non-periodic Tx FIFO */
+ dwc2_dbg(dwc2, "initial gnptxfsiz=%08x\n", dwc2_readl(dwc2, GNPTXFSIZ));
+ nptxfsiz = params->host_nperio_tx_fifo_size <<
+ FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
+ nptxfsiz |= params->host_rx_fifo_size <<
+ FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
+ dwc2_writel(dwc2, nptxfsiz, GNPTXFSIZ);
+ dwc2_dbg(dwc2, "new gnptxfsiz=%08x\n", dwc2_readl(dwc2, GNPTXFSIZ));
+
+ /* Periodic Tx FIFO */
+ dwc2_dbg(dwc2, "initial hptxfsiz=%08x\n", dwc2_readl(dwc2, HPTXFSIZ));
+ hptxfsiz = params->host_perio_tx_fifo_size <<
+ FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
+ hptxfsiz |= (params->host_rx_fifo_size +
+params->host_nperio_tx_fifo_size) <<
+ FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
+ dwc2_writel(dwc2, hptxfsiz, HPTXFSIZ);
+ dwc2_dbg(dwc2, "new hptxfsiz=%08x\n", dwc2_readl(dwc2, HPTXFSIZ));
+
+ if (dwc2->params.en_multiple_tx_fifo &&
+ dwc2->hw_params.snpsid >= DWC2_CORE_REV_2_91a) {
+ /*
+* This feature was implemented in 2.91a version
+* Global DFIFOCFG calculation for Host mode -
+* include RxFIFO, NPTXFIFO and HPTXFIFO
+*/
+ dfifocfg = dwc2_readl(dwc2, GDFIFOCFG);
+
[RFC PATCH 5/7] HACK: usb: dwc2: Fix toggle reset
>From USB 2.0 specification, section 9.4.5:
ClearFeature(ENDPOINT_HALT) request always results in
the data toggle being reinitialized to DATA0.
Signed-off-by: Jules Maselbas
---
drivers/usb/dwc2/host.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/usb/dwc2/host.c b/drivers/usb/dwc2/host.c
index 2cde5977b..a97c7dac5 100644
--- a/drivers/usb/dwc2/host.c
+++ b/drivers/usb/dwc2/host.c
@@ -373,7 +373,24 @@ int dwc2_submit_control_msg(struct usb_device *udev,
if (ret)
return ret;
+ if (setup->requesttype == USB_RECIP_ENDPOINT
+ && setup->request == USB_REQ_CLEAR_FEATURE) {
+ /* From USB 2.0, section 9.4.5:
+* ClearFeature(ENDPOINT_HALT) request always results
+* in the data toggle being reinitialized to DATA0.
+*/
+ int ep = le16_to_cpu(setup->index & 0x7f);
+ int in = le16_to_cpu(setup->index & 0x80);
+ int data0 = TSIZ_SC_MC_PID_DATA0;
+
+ if (in)
+ dwc2->in_data_toggle[devnum][ep] = data0;
+ else
+ dwc2->out_data_toggle[devnum][ep] = data0;
+ }
+
udev->act_len = act_len;
+ udev->status = 0;
return 0;
}
--
2.21.0.196.g041f5ea
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[RFC PATCH 2/7] usb: dwc2: host: Handle dma mapping errors
Signed-off-by: Jules Maselbas
---
drivers/usb/dwc2/host.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/usb/dwc2/host.c b/drivers/usb/dwc2/host.c
index 4137dd3cb..a1f2e3ea1 100644
--- a/drivers/usb/dwc2/host.c
+++ b/drivers/usb/dwc2/host.c
@@ -154,6 +154,11 @@ static int transfer_chunk(struct dwc2 *dwc2, u8 hc,
dma_addr = dma_map_single(dwc2->dev, buffer, xfer_len,
in ? DMA_FROM_DEVICE : DMA_TO_DEVICE);
+ if (dma_mapping_error(dwc2->dev, dma_addr)) {
+ dwc2_err(dwc2, "Failed to map buffer@0x%p for dma\n", buffer);
+ return -EFAULT;
+ }
+
dwc2_dbg(dwc2, "chunk: pid=%d xfer_len=%u pkts=%u dma_addr=%llx\n",
*pid, xfer_len, num_packets, dma_addr);
--
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[RFC PATCH 4/7] usb: dwc2: Rework roothub interface
Roothub requests are now decoded in one place.
Signed-off-by: Jules Maselbas
---
drivers/usb/dwc2/dwc2.h | 2 +-
drivers/usb/dwc2/host.c | 4 +-
drivers/usb/dwc2/rhub.c | 520 +++-
3 files changed, 246 insertions(+), 280 deletions(-)
diff --git a/drivers/usb/dwc2/dwc2.h b/drivers/usb/dwc2/dwc2.h
index 0ac4b40fc..0a4323ab4 100644
--- a/drivers/usb/dwc2/dwc2.h
+++ b/drivers/usb/dwc2/dwc2.h
@@ -35,7 +35,7 @@ int dwc2_submit_int_msg(struct usb_device *dev, unsigned long
pipe,
void *buffer, int transfer_len, int interval);
int dwc2_host_init(struct usb_host *host);
-int dwc2_submit_rh_msg(struct dwc2 *dwc2, struct usb_device *dev,
+int dwc2_submit_roothub(struct dwc2 *dwc2, struct usb_device *dev,
unsigned long pipe, void *buf, int len,
struct devrequest *setup);
diff --git a/drivers/usb/dwc2/host.c b/drivers/usb/dwc2/host.c
index 84eb9b627..2cde5977b 100644
--- a/drivers/usb/dwc2/host.c
+++ b/drivers/usb/dwc2/host.c
@@ -332,9 +332,9 @@ int dwc2_submit_control_msg(struct usb_device *udev,
int status_direction;
if (devnum == dwc2->root_hub_devnum) {
- udev->status = 0;
udev->speed = USB_SPEED_HIGH;
- return dwc2_submit_rh_msg(dwc2, udev, pipe, buffer, len, setup);
+ ret = dwc2_submit_roothub(dwc2, udev, pipe, buffer, len, setup);
+ return ret;
}
/* SETUP stage */
diff --git a/drivers/usb/dwc2/rhub.c b/drivers/usb/dwc2/rhub.c
index b94723d7b..cc733f34e 100644
--- a/drivers/usb/dwc2/rhub.c
+++ b/drivers/usb/dwc2/rhub.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
#include "dwc2.h"
static struct descriptor {
@@ -6,7 +7,7 @@ static struct descriptor {
struct usb_config_descriptor config;
struct usb_interface_descriptor interface;
struct usb_endpoint_descriptor endpoint;
-} __attribute__ ((packed)) descriptor = {
+} __packed descriptor = {
.hub = {
.bLength= USB_DT_HUB_NONVAR_SIZE +
((USB_MAXCHILDREN + 1 + 7) / 8),
@@ -21,7 +22,7 @@ static struct descriptor {
.device = {
.bLength= USB_DT_DEVICE_SIZE,
.bDescriptorType= USB_DT_DEVICE,
- .bcdUSB = __constant_cpu_to_le16(2), /* v2.0 */
+ .bcdUSB = cpu_to_le16(2), /* v2.0 */
.bDeviceClass = USB_CLASS_HUB,
.bDeviceSubClass= 0,
.bDeviceProtocol= USB_HUB_PR_HS_NO_TT,
@@ -37,7 +38,7 @@ static struct descriptor {
.config = {
.bLength= USB_DT_CONFIG_SIZE,
.bDescriptorType= USB_DT_CONFIG,
- .wTotalLength = __constant_cpu_to_le16(
+ .wTotalLength = cpu_to_le16(
USB_DT_CONFIG_SIZE +
USB_DT_INTERFACE_SIZE +
USB_DT_ENDPOINT_SIZE),
@@ -63,356 +64,321 @@ static struct descriptor {
.bDescriptorType= USB_DT_ENDPOINT,
.bEndpointAddress = 1 | USB_DIR_IN, /* 0x81 */
.bmAttributes = USB_ENDPOINT_XFER_INT,
- .wMaxPacketSize = __constant_cpu_to_le16(
+ .wMaxPacketSize = cpu_to_le16(
(USB_MAXCHILDREN + 1 + 7) / 8),
.bInterval = 255
},
};
-static char *language_string = "\x09\x04";
-static char *vendor_string = "u-boot";
-static char *product_string = "DWC2 root hub";
-
-/*
- * DWC2 to USB API interface
- */
-static int dwc2_submit_rh_msg_in_status(struct dwc2 *dwc2,
- struct usb_device *dev, void *buffer,
- int txlen, struct devrequest *cmd)
+static int dwc2_get_port_status(struct dwc2 *dwc2, struct usb_device *dev,
+ void *buf, int len)
{
struct usb_port_status *portsts;
- uint32_t hprt0 = 0;
- uint32_t port_status = 0;
- uint32_t port_change = 0;
- int len = 0;
+ uint32_t hprt0;
+ uint32_t status = 0;
+ uint32_t change = 0;
int speed;
- switch (cmd->requesttype & (USB_TYPE_MASK | USB_RECIP_MASK)) {
- case USB_TYPE_STANDARD | USB_RECIP_DEVICE:
- *(uint16_t *)buffer = cpu_to_le16(1);
- len = 2;
- break;
- case USB_TYPE_STANDARD | USB_RECIP_INTERFACE:
- case USB_TYPE_STANDARD | USB_RECIP_ENDPOINT:
- *(uint16_t *)buffer = cpu_to_le16(0);
- len = 2;
- break;
- case USB_RT_HUB:/* USB_TYPE_CLASS | USB_RECIP_DEVICE */
- *(uint32_t
[RFC PATCH 7/7] usb: dwc2: Read dr_mode from device tree
Signed-off-by: Jules Maselbas
---
drivers/usb/dwc2/core.c | 89 +
drivers/usb/dwc2/dwc2.c | 2 +
drivers/usb/dwc2/dwc2.h | 1 +
3 files changed, 92 insertions(+)
diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c
index 9a36b0904..94ff977bb 100644
--- a/drivers/usb/dwc2/core.c
+++ b/drivers/usb/dwc2/core.c
@@ -1,6 +1,33 @@
// SPDX-License-Identifier: GPL-2.0+
#include "dwc2.h"
+/* Returns the controller's GHWCFG2.OTG_MODE. */
+static unsigned int dwc2_op_mode(struct dwc2 *dwc2)
+{
+ u32 ghwcfg2 = dwc2_readl(dwc2, GHWCFG2);
+
+ return (ghwcfg2 & GHWCFG2_OP_MODE_MASK) >>
+ GHWCFG2_OP_MODE_SHIFT;
+}
+
+/* Returns true if the controller is host-only. */
+static bool dwc2_hw_is_host(struct dwc2 *dwc2)
+{
+ unsigned int op_mode = dwc2_op_mode(dwc2);
+
+ return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_HOST) ||
+ (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST);
+}
+
+/* Returns true if the controller is device-only. */
+static bool dwc2_hw_is_device(struct dwc2 *dwc2)
+{
+ unsigned int op_mode = dwc2_op_mode(dwc2);
+
+ return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ||
+ (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE);
+}
+
void dwc2_set_param_otg_cap(struct dwc2 *dwc2)
{
u8 val;
@@ -493,6 +520,68 @@ void dwc2_gusbcfg_init(struct dwc2 *dwc2)
dwc2_writel(dwc2, usbcfg, GUSBCFG);
}
+/*
+ * Check the dr_mode against the module configuration and hardware
+ * capabilities.
+ *
+ * The hardware, module, and dr_mode, can each be set to host, device,
+ * or otg. Check that all these values are compatible and adjust the
+ * value of dr_mode if possible.
+ *
+ * actual
+ *HW MOD dr_mode dr_mode
+ * --
+ * HST HST any: HST
+ * HST DEV any: ---
+ * HST OTG any: HST
+ *
+ * DEV HST any: ---
+ * DEV DEV any: DEV
+ * DEV OTG any: DEV
+ *
+ * OTG HST any: HST
+ * OTG DEV any: DEV
+ * OTG OTG any: dr_mode
+ */
+int dwc2_get_dr_mode(struct dwc2 *dwc2)
+{
+ enum usb_dr_mode mode;
+
+ mode = of_usb_get_dr_mode(dwc2->dev->device_node, NULL);
+ dwc2->dr_mode = mode;
+
+ if (dwc2_hw_is_device(dwc2)) {
+ if (IS_ENABLED(CONFIG_USB_DWC2_HOST)) {
+ dwc2_err(dwc2,
+ "Controller does not support host mode.\n");
+ return -EINVAL;
+ }
+ mode = USB_DR_MODE_PERIPHERAL;
+ } else if (dwc2_hw_is_host(dwc2)) {
+ if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL)) {
+ dwc2_err(dwc2,
+ "Controller does not support device mode.\n");
+ return -EINVAL;
+ }
+ mode = USB_DR_MODE_HOST;
+ } else {
+ if (IS_ENABLED(CONFIG_USB_DWC2_HOST))
+ mode = USB_DR_MODE_HOST;
+ else if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL))
+ mode = USB_DR_MODE_PERIPHERAL;
+ }
+
+ if (mode != dwc2->dr_mode) {
+ dwc2_warn(dwc2,
+"Configuration mismatch. dr_mode forced to %s\n",
+ mode == USB_DR_MODE_HOST ? "host" : "device");
+
+ dwc2->dr_mode = mode;
+ }
+
+ return 0;
+}
+
/*
* Do core a soft reset of the core. Be careful with this because it
* resets all the internal state machines of the core.
diff --git a/drivers/usb/dwc2/dwc2.c b/drivers/usb/dwc2/dwc2.c
index 893f573bc..1df393e77 100644
--- a/drivers/usb/dwc2/dwc2.c
+++ b/drivers/usb/dwc2/dwc2.c
@@ -62,6 +62,8 @@ static int dwc2_probe(struct device_d *dev)
/* Detect config values from hardware */
dwc2_get_hwparams(dwc2);
+ dwc2_get_dr_mode(dwc2);
+
dwc2_set_default_params(dwc2);
dma_set_mask(dev, DMA_BIT_MASK(32));
diff --git a/drivers/usb/dwc2/dwc2.h b/drivers/usb/dwc2/dwc2.h
index 0a4323ab4..35ba00660 100644
--- a/drivers/usb/dwc2/dwc2.h
+++ b/drivers/usb/dwc2/dwc2.h
@@ -21,6 +21,7 @@ void dwc2_flush_all_fifo(struct dwc2 *dwc2);
int dwc2_phy_init(struct dwc2 *dwc2, bool select_phy);
int dwc2_gahbcfg_init(struct dwc2 *dwc2);
void dwc2_gusbcfg_init(struct dwc2 *dwc2);
+int dwc2_get_dr_mode(struct dwc2 *dwc2);
int dwc2_core_reset(struct dwc2 *dwc2);
void dwc2_core_init(struct dwc2 *dwc2);
--
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[RFC PATCH 1/7] usb: dwc2: Add host controller driver
The host driver is mostly taken from U-Boot, other part are from Linux
Signed-off-by: Jules Maselbas
---
drivers/usb/Kconfig | 2 +
drivers/usb/Makefile | 1 +
drivers/usb/dwc2/Kconfig | 4 +
drivers/usb/dwc2/Makefile | 1 +
drivers/usb/dwc2/core.c | 614 +++
drivers/usb/dwc2/core.h | 546
drivers/usb/dwc2/dwc2.c | 101 +
drivers/usb/dwc2/dwc2.h | 41 ++
drivers/usb/dwc2/host.c | 618 +++
drivers/usb/dwc2/regs.h | 847 ++
drivers/usb/dwc2/rhub.c | 418 +++
11 files changed, 3193 insertions(+)
create mode 100644 drivers/usb/dwc2/Kconfig
create mode 100644 drivers/usb/dwc2/Makefile
create mode 100644 drivers/usb/dwc2/core.c
create mode 100644 drivers/usb/dwc2/core.h
create mode 100644 drivers/usb/dwc2/dwc2.c
create mode 100644 drivers/usb/dwc2/dwc2.h
create mode 100644 drivers/usb/dwc2/host.c
create mode 100644 drivers/usb/dwc2/regs.h
create mode 100644 drivers/usb/dwc2/rhub.c
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index 99eff1c8d..aab1564ab 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -9,6 +9,8 @@ if USB_HOST
source "drivers/usb/imx/Kconfig"
+source "drivers/usb/dwc2/Kconfig"
+
source "drivers/usb/dwc3/Kconfig"
source "drivers/usb/host/Kconfig"
diff --git a/drivers/usb/Makefile b/drivers/usb/Makefile
index 9e9809950..ecd7ad1d3 100644
--- a/drivers/usb/Makefile
+++ b/drivers/usb/Makefile
@@ -1,5 +1,6 @@
obj-$(CONFIG_USB) += core/
obj-$(CONFIG_USB_IMX_CHIPIDEA) += imx/
+obj-$(CONFIG_USB_DWC2) += dwc2/
obj-$(CONFIG_USB_DWC3) += dwc3/
obj-$(CONFIG_USB_MUSB) += musb/
obj-$(CONFIG_USB_GADGET) += gadget/
diff --git a/drivers/usb/dwc2/Kconfig b/drivers/usb/dwc2/Kconfig
new file mode 100644
index 0..c88134cbb
--- /dev/null
+++ b/drivers/usb/dwc2/Kconfig
@@ -0,0 +1,4 @@
+config USB_DWC2
+ bool "DWC2 driver"
+ help
+ DesignWare Core USB2 OTG driver.
diff --git a/drivers/usb/dwc2/Makefile b/drivers/usb/dwc2/Makefile
new file mode 100644
index 0..3b922c282
--- /dev/null
+++ b/drivers/usb/dwc2/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_USB_DWC2) += dwc2.o core.o host.o rhub.o
diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c
new file mode 100644
index 0..9a36b0904
--- /dev/null
+++ b/drivers/usb/dwc2/core.c
@@ -0,0 +1,614 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include "dwc2.h"
+
+void dwc2_set_param_otg_cap(struct dwc2 *dwc2)
+{
+ u8 val;
+
+ switch (dwc2->hw_params.op_mode) {
+ case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
+ val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE;
+ break;
+ case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
+ case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
+ case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
+ val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE;
+ break;
+ default:
+ val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
+ break;
+ }
+
+ dwc2->params.otg_cap = val;
+}
+
+void dwc2_set_param_phy_type(struct dwc2 *dwc2)
+{
+ u8 val;
+
+ switch (dwc2->hw_params.hs_phy_type) {
+ case GHWCFG2_HS_PHY_TYPE_UTMI:
+ case GHWCFG2_HS_PHY_TYPE_UTMI_ULPI:
+ val = DWC2_PHY_TYPE_PARAM_UTMI;
+ break;
+ case GHWCFG2_HS_PHY_TYPE_ULPI:
+ val = DWC2_PHY_TYPE_PARAM_ULPI;
+ break;
+ case GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED:
+ val = DWC2_PHY_TYPE_PARAM_FS;
+ break;
+ }
+
+ dwc2->params.phy_type = val;
+}
+
+void dwc2_set_param_speed(struct dwc2 *dwc2)
+{
+ if (dwc2->params.phy_type == DWC2_PHY_TYPE_PARAM_FS)
+ dwc2->params.speed = DWC2_SPEED_PARAM_FULL;
+ else
+ dwc2->params.speed = DWC2_SPEED_PARAM_HIGH;
+}
+
+void dwc2_set_param_phy_utmi_width(struct dwc2 *dwc2)
+{
+ int val;
+
+ val = (dwc2->hw_params.utmi_phy_data_width ==
+ GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16;
+
+ dwc2->params.phy_utmi_width = val;
+}
+
+/**
+ * dwc2_set_default_params() - Set all core parameters to their
+ * auto-detected default values.
+ *
+ * @dwc2: Programming view of the DWC2 controller
+ *
+ */
+void dwc2_set_default_params(struct dwc2 *dwc2)
+{
+ struct dwc2_hw_params *hw = >hw_params;
+ struct dwc2_core_params *p = >params;
+ bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
+
+ dwc2_set_param_otg_cap(dwc2);
+ dwc2_set_param_phy_type(dwc2);
+ dwc2_set_param_speed(dwc2);
+ dwc2_set_param_phy_utmi_width(dwc2);
+ p->phy_ulpi_ddr = false;
+ p->phy_ulpi_ext_vbus = false;
+
+ p->enable_dynamic_fifo = hw->enable_dynamic_fifo;
+ p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo;
+ p->i2c_enable = hw->i2c_enable;
+ p->acg_enable = hw->acg_enable;
+
[RFC PATCH 6/7] usb: dwc2: Rewrite dwc2_hc_init
Removed the uses of a table to convert the usb endpoint type for
the controller.
Signed-off-by: Jules Maselbas
---
drivers/usb/dwc2/host.c | 47 +++--
1 file changed, 27 insertions(+), 20 deletions(-)
diff --git a/drivers/usb/dwc2/host.c b/drivers/usb/dwc2/host.c
index a97c7dac5..083c964e8 100644
--- a/drivers/usb/dwc2/host.c
+++ b/drivers/usb/dwc2/host.c
@@ -7,13 +7,6 @@
/* Use only HC channel 0. */
#define DWC2_HC_CHANNEL0
-static int dwc2_eptype[] = {
- DXEPCTL_EPTYPE_ISO,
- DXEPCTL_EPTYPE_INTERRUPT,
- DXEPCTL_EPTYPE_CONTROL,
- DXEPCTL_EPTYPE_BULK,
-};
-
static int dwc2_do_split(struct dwc2 *dwc2, struct usb_device *dev)
{
uint32_t hprt0 = dwc2_readl(dwc2, HPRT0);
@@ -80,15 +73,32 @@ static void dwc2_hc_enable_ints(struct dwc2 *dwc2, uint8_t
hc)
* @param regs Programming view of DWC2 controller
* @param hc Information needed to initialize the host channel
*/
-static void dwc2_hc_init(struct dwc2 *dwc2, uint8_t hc,
- struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num,
- uint8_t ep_is_in, uint32_t ep_type, uint16_t max_packet)
+static void dwc2_hc_init(struct dwc2 *dwc2, struct usb_device *dev, u8 hc,
+unsigned long pipe, int is_in)
{
- uint32_t hcchar = (dev_addr << HCCHAR_DEVADDR_SHIFT) |
- (ep_num << HCCHAR_EPNUM_SHIFT) |
- (ep_is_in ? HCCHAR_EPDIR : 0) |
- ep_type |
- (max_packet << HCCHAR_MPS_SHIFT);
+ int addr = usb_pipedevice(pipe);
+ int endp = usb_pipeendpoint(pipe);
+ int type = usb_pipetype(pipe);
+ int mps = usb_maxpacket(dev, pipe);
+ uint32_t hcchar = (addr << HCCHAR_DEVADDR_SHIFT) |
+ (endp << HCCHAR_EPNUM_SHIFT) |
+ (is_in ? HCCHAR_EPDIR : 0) |
+ (mps << HCCHAR_MPS_SHIFT);
+
+ switch (type) {
+ case PIPE_ISOCHRONOUS:
+ hcchar |= DXEPCTL_EPTYPE_ISO;
+ break;
+ case PIPE_INTERRUPT:
+ hcchar |= DXEPCTL_EPTYPE_INTERRUPT;
+ break;
+ case PIPE_CONTROL:
+ hcchar |= DXEPCTL_EPTYPE_CONTROL;
+ break;
+ case PIPE_BULK:
+ hcchar |= DXEPCTL_EPTYPE_BULK;
+ break;
+ }
if (dev->speed == USB_SPEED_LOW)
hcchar |= HCCHAR_LSPDDEV;
@@ -207,10 +217,7 @@ static int dwc2_submit_packet(struct dwc2 *dwc2, struct
usb_device *dev,
unsigned long pipe, u8 *pid, int in, void *buf,
int len)
{
- int devnum = usb_pipedevice(pipe);
- int ep = usb_pipeendpoint(pipe);
int mps = usb_maxpacket(dev, pipe);
- int eptype = dwc2_eptype[usb_pipetype(pipe)];
int do_split = dwc2_do_split(dwc2, dev);
int complete_split = 0;
int done = 0;
@@ -231,7 +238,7 @@ static int dwc2_submit_packet(struct dwc2 *dwc2, struct
usb_device *dev,
max_xfer_len = num_packets * mps;
/* Initialize channel */
- dwc2_hc_init(dwc2, DWC2_HC_CHANNEL, dev, devnum, ep, in, eptype, mps);
+ dwc2_hc_init(dwc2, dev, DWC2_HC_CHANNEL, pipe, in);
/* Check if the target is a FS/LS device behind a HS hub */
if (do_split) {
@@ -262,7 +269,7 @@ static int dwc2_submit_packet(struct dwc2 *dwc2, struct
usb_device *dev,
dwc2_writel(dwc2, hcsplt, HCSPLT(DWC2_HC_CHANNEL));
}
- if (eptype == DXEPCTL_EPTYPE_INTERRUPT) {
+ if (usb_pipeint(pipe)) {
int uframe_num = dwc2_readl(dwc2, HFNUM);
if (!(uframe_num & 0x1))
--
2.21.0.196.g041f5ea
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Re: [PATCH] MIPS: dts: rename tplink-mr3020.dts -> ar9331_tl_mr3020.dts
On Thu, Jan 09, 2020 at 10:21:22AM +0300, Antony Pavlov wrote:
> Linux MIPS uses _.dts board dts-file
> naming scheme so use it in barebox too.
>
> Signed-off-by: Antony Pavlov
> ---
> arch/mips/boards/tplink-mr3020/lowlevel.S | 2 +-
> arch/mips/dts/Makefile| 2 +-
> arch/mips/dts/{tplink-mr3020.dts => ar9331_tl_mr3020.dts} | 0
> 3 files changed, 2 insertions(+), 2 deletions(-)
Applied, thanks
Sascha
--
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Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0|
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
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[PATCH] usb: ehci: Do not use memset on dma coherent memory
memset is an optimized operation that at least on ARM64 may only be
called on cached memory, see 32e8842c40 ("ARM: lib64: Make string
functions aware of MMU configuration"). To avoid crashes in the ehci
driver we no longer call memset on memory allocated with
dma_alloc_coherent(), but use a simple memzero32 function instead.
Reported-by: Elmar Albert
Signed-off-by: Sascha Hauer
---
drivers/usb/host/ehci-hcd.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index f3be177ceb..417ae5df75 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -137,6 +137,15 @@ static struct descriptor {
#define ehci_is_TDI() (ehci->flags & EHCI_HAS_TT)
+static void memzero32(void *ptr, size_t size)
+{
+ uint32_t *ptr32 = ptr;
+ int i;
+
+ for (i = 0; i < size / sizeof(uint32_t); i++)
+ ptr32[i] = 0x0;
+}
+
static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec)
{
uint32_t result;
@@ -237,7 +246,7 @@ static int ehci_prepare_qtd(struct device_d *dev,
if (ret)
return ret;
} else {
- memset(td->qt_buffer, 0, sizeof(td->qt_buffer));
+ memzero32(td->qt_buffer, sizeof(td->qt_buffer));
}
return 0;
@@ -318,7 +327,7 @@ ehci_submit_async(struct usb_device *dev, unsigned long
pipe, void *buffer,
qh->qh_endpt2 = cpu_to_hc32(endpt);
qh->qh_curtd = 0;
qh->qt_token = 0;
- memset(qh->qt_buffer, 0, sizeof(qh->qt_buffer));
+ memzero32(qh->qt_buffer, sizeof(qh->qt_buffer));
tdp = >qt_next;
@@ -854,7 +863,7 @@ static int ehci_init(struct usb_host *host)
*/
ehci->periodic_schedules = 0;
periodic = ehci->periodic_queue;
- memset(periodic, 0, sizeof(*periodic));
+ memzero32(periodic, sizeof(*periodic));
periodic->qh_link = cpu_to_hc32(QH_LINK_TERMINATE);
periodic->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
periodic->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
--
2.25.0.rc1
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Re: [PATCH 1/3] serial: cadence: move register definitions into header file
On Mon, Jan 13, 2020 at 08:37:14PM +0100, Lucas Stach wrote: > Signed-off-by: Lucas Stach > --- > drivers/serial/serial_cadence.c | 41 - > include/serial/cadence.h| 37 + > 2 files changed, 42 insertions(+), 36 deletions(-) > create mode 100644 include/serial/cadence.h Applied, thanks Sascha -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH] ARM: zynq: zed: partially revert zynq_cpu_lowlevel_init() chnages
On Mon, Jan 13, 2020 at 08:36:37PM +0100, Lucas Stach wrote: > Calling arm_cpu_lowlevel_init() from zynq_cpu_lowlevel_init() adds a stack > push/pop to the latter function which doesn't work this early in the boot. > > As the BootROM apparently hands proccessor control to us in abort(!?!) > mode, setting up a stack requires duplicating most of arm_cpu_lowlevel_init(). > To get around this catch-22 move the call to arm_cpu_lowlevel_init back into > the board lowlevel start function, so we don't need a stack at all. > > Signed-off-by: Lucas Stach > --- > arch/arm/boards/avnet-zedboard/lowlevel.c | 1 + > arch/arm/mach-zynq/cpu_init.c | 2 -- > 2 files changed, 1 insertion(+), 2 deletions(-) Applied, thanks Sascha -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH 1/2] PCI: layerscape: rename variable
Rename 'arr' to 'msi_map' which is a better name when we add another
array in the next patch.
Signed-off-by: Sascha Hauer
---
drivers/pci/pci-layerscape.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/pci/pci-layerscape.c b/drivers/pci/pci-layerscape.c
index ccdc025c2e..0e41321a9a 100644
--- a/drivers/pci/pci-layerscape.c
+++ b/drivers/pci/pci-layerscape.c
@@ -342,7 +342,7 @@ static int ls_pcie_of_fixup(struct device_node *root, void
*ctx)
struct device_d *dev = pcie->pci.dev;
struct device_node *np;
char *name;
- u32 *arr, phandle;
+ u32 *msi_map, phandle;
int nluts;
int ret, i;
u32 devid, stream_id;
@@ -364,7 +364,7 @@ static int ls_pcie_of_fixup(struct device_node *root, void
*ctx)
return ret;
}
- arr = xmalloc(nluts * sizeof(u32) * 4);
+ msi_map = xmalloc(nluts * sizeof(u32) * 4);
for (i = 0; i < nluts; i++) {
u32 udr = lut_readl(pcie, PCIE_LUT_UDR(i));
@@ -376,10 +376,10 @@ static int ls_pcie_of_fixup(struct device_node *root,
void *ctx)
devid = udr >> 16;
stream_id = ldr & 0x7fff;
- arr[i * 4] = devid;
- arr[i * 4 + 1] = phandle;
- arr[i * 4 + 2] = stream_id;
- arr[i * 4 + 3] = 1;
+ msi_map[i * 4] = devid;
+ msi_map[i * 4 + 1] = phandle;
+ msi_map[i * 4 + 2] = stream_id;
+ msi_map[i * 4 + 3] = 1;
}
/*
@@ -391,7 +391,7 @@ static int ls_pcie_of_fixup(struct device_node *root, void
*ctx)
* [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
*/
- ret = of_property_write_u32_array(np, "msi-map", arr, nluts * 4);
+ ret = of_property_write_u32_array(np, "msi-map", msi_map, nluts * 4);
if (ret)
goto out;
@@ -400,7 +400,7 @@ static int ls_pcie_of_fixup(struct device_node *root, void
*ctx)
ret = 0;
out:
- free(arr);
+ free(msi_map);
return ret;
}
--
2.25.0.rc1
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[PATCH 2/2] PCI: layerscape: Fixup iommu-map properties
The iommu-map properties are needed for proper PCI support under Linux.
Signed-off-by: Sascha Hauer
---
drivers/pci/pci-layerscape.c | 39 +++-
1 file changed, 38 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/pci-layerscape.c b/drivers/pci/pci-layerscape.c
index 0e41321a9a..e20dd55b1f 100644
--- a/drivers/pci/pci-layerscape.c
+++ b/drivers/pci/pci-layerscape.c
@@ -336,13 +336,32 @@ static int __init ls_add_pcie_port(struct ls_pcie *pcie)
return 0;
}
+static phandle ls_pcie_get_iommu_handle(struct device_node *np, phandle
*handle)
+{
+ u32 arr[4];
+ int ret;
+
+ /*
+* We expect an existing "iommu-map" property with bogus values. All we
+* use from it is the phandle to the iommu.
+*/
+ ret = of_property_read_u32_array(np, "iommu-map", arr, 4);
+ if (ret)
+ return -ENOENT;
+
+ *handle = arr[1];
+
+ return 0;
+}
+
static int ls_pcie_of_fixup(struct device_node *root, void *ctx)
{
struct ls_pcie *pcie = ctx;
struct device_d *dev = pcie->pci.dev;
struct device_node *np;
+ phandle iommu_handle = 0;
char *name;
- u32 *msi_map, phandle;
+ u32 *msi_map, *iommu_map, phandle;
int nluts;
int ret, i;
u32 devid, stream_id;
@@ -364,7 +383,14 @@ static int ls_pcie_of_fixup(struct device_node *root, void
*ctx)
return ret;
}
+ ret = ls_pcie_get_iommu_handle(np, _handle);
+ if (ret) {
+ dev_err(pcie->pci.dev, "Unable to get iommu phandle\n");
+ return ret;
+ }
+
msi_map = xmalloc(nluts * sizeof(u32) * 4);
+ iommu_map = xmalloc(nluts * sizeof(u32) * 4);
for (i = 0; i < nluts; i++) {
u32 udr = lut_readl(pcie, PCIE_LUT_UDR(i));
@@ -380,6 +406,11 @@ static int ls_pcie_of_fixup(struct device_node *root, void
*ctx)
msi_map[i * 4 + 1] = phandle;
msi_map[i * 4 + 2] = stream_id;
msi_map[i * 4 + 3] = 1;
+
+ iommu_map[i * 4] = devid;
+ iommu_map[i * 4 + 1] = iommu_handle;
+ iommu_map[i * 4 + 2] = stream_id;
+ iommu_map[i * 4 + 3] = 1;
}
/*
@@ -395,12 +426,18 @@ static int ls_pcie_of_fixup(struct device_node *root,
void *ctx)
if (ret)
goto out;
+ ret = of_property_write_u32_array(np, "iommu-map", iommu_map, nluts *
4);
+ if (ret)
+ goto out;
+
of_device_enable(np);
ret = 0;
out:
free(msi_map);
+ free(iommu_map);
+
return ret;
}
--
2.25.0.rc1
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