Re: [PATCH] nvmem: regmap: Fix nvmem size
After applying this patch the last register is writable, but still not readable. The size is now correct: barebox:/ ls -l /dev/stm32-bsec crw---384 /dev/stm32-bsec This now works: mw -l -d /dev/stm32-bsec 0x017c+4 0x12345678 This still doesn't: barebox:/ md -l -s /dev/stm32-bsec 0x017c+4 read: Invalid argument On 2023-12-19 15:14, Robin van der Gracht wrote: We should add 1 to the max_register index since counting is zero based. i.e. the stm32mp151 bsec has registers 0 - 95 with reg_stride 4. Size should be (95 + 1) * 4 = 384 bytes otherwise we can't access bsec register 95 (last one). Signed-off-by: Robin van der Gracht --- drivers/nvmem/regmap.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/nvmem/regmap.c b/drivers/nvmem/regmap.c index fa5405d7a8..ffc96a310f 100644 --- a/drivers/nvmem/regmap.c +++ b/drivers/nvmem/regmap.c @@ -78,7 +78,7 @@ nvmem_regmap_register_with_pp(struct regmap *map, const char *name, config.priv = map; config.stride = 1; config.word_size = 1; - config.size = regmap_get_max_register(map) * regmap_get_reg_stride(map); + config.size = (regmap_get_max_register(map) + 1) * regmap_get_reg_stride(map); config.cell_post_process = cell_post_process; config.reg_write = nvmem_regmap_write; config.reg_read = nvmem_regmap_read;
Re: [PATCH] mfd: rn5t568: add complete register map to header and use it
Hello Bastian,
On 19.12.23 18:00, Bastian Krause wrote:
> This allows lowlevel board code to use these symbols to perform power
> sequencing with the PBL PMIC helper functions.
>
> Signed-off-by: Bastian Krause
> ---
> drivers/mfd/rn5t568.c | 24 +---
> include/mfd/rn5t568.h | 132 ++
> 2 files changed, 133 insertions(+), 23 deletions(-)
> create mode 100644 include/mfd/rn5t568.h
>
> diff --git a/drivers/mfd/rn5t568.c b/drivers/mfd/rn5t568.c
> index 12de689734d..f1e2eeb0c88 100644
> --- a/drivers/mfd/rn5t568.c
> +++ b/drivers/mfd/rn5t568.c
> @@ -16,29 +16,7 @@
> #include
> #include
> #include
> -
> -#define RN5T568_LSIVER 0x00
> -#define RN5T568_OTPVER 0x01
> -#define RN5T568_PONHIS 0x09
> -# define RN5T568_PONHIS_ON_EXTINPON BIT(3)
> -# define RN5T568_PONHIS_ON_REPWRPON BIT(1)
> -# define RN5T568_PONHIS_ON_PWRONPON BIT(0)
> -#define RN5T568_POFFHIS 0x0a
> -# define RN5T568_POFFHIS_N_OEPOFF BIT(7)
> -# define RN5T568_POFFHIS_DCLIMPOFF BIT(6)
> -# define RN5T568_POFFHIS_WDGPOFF BIT(5)
> -# define RN5T568_POFFHIS_CPUPOFF BIT(4)
> -# define RN5T568_POFFHIS_IODETPOFF BIT(3)
> -# define RN5T568_POFFHIS_VINDETPOFF BIT(2)
> -# define RN5T568_POFFHIS_TSHUTPOFF BIT(1)
> -# define RN5T568_POFFHIS_PWRONPOFF BIT(0)
> -#define RN5T568_SLPCNT 0x0e
> -# define RN5T568_SLPCNT_SWPPWROFF BIT(0)
> -#define RN5T568_REPCNT 0x0f
> -# define RN5T568_REPCNT_OFF_RESETO_16MS 0x30
> -# define RN5T568_REPCNT_OFF_REPWRTIM_1000MS 0x06
> -# define RN5T568_REPCNT_OFF_REPWRON BIT(0)
> -#define RN5T568_MAX_REG 0xbc
> +#include
>
> struct rn5t568 {
> struct restart_handler restart;
> diff --git a/include/mfd/rn5t568.h b/include/mfd/rn5t568.h
> new file mode 100644
> index 000..eff2b6dbe67
> --- /dev/null
> +++ b/include/mfd/rn5t568.h
> @@ -0,0 +1,132 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2014 Beniamino Galvani
> + * Copyright (C) 2016 Toradex AG
> + */
> +
> +#ifndef __MFD_RN5T568_H
> +#define __MFD_RN5T568_H
#include
is missing for the BIT() definitions below. If you are on an older barebox
version,
you'll have to include the fatter on your side, but for
upstreaming,
is preferable.
Cheers,
Ahmad
> +
> +/* RN5T568 registers */
> +enum {
> + RN5T568_LSIVER = 0x00,
> + RN5T568_OTPVER = 0x01,
> + RN5T568_IODAC = 0x02,
> + RN5T568_VINDAC = 0x03,
> + RN5T568_OUT32KEN= 0x05,
> +
> + RN5T568_CPUCNT = 0x06,
> +
> + RN5T568_PSWR= 0x07,
> + RN5T568_PONHIS = 0x09,
> + RN5T568_POFFHIS = 0x0A,
> + RN5T568_WATCHDOG= 0x0B,
> + RN5T568_WATCHDOGCNT = 0x0C,
> + RN5T568_PWRFUNC = 0x0D,
> + RN5T568_SLPCNT = 0x0E,
> + RN5T568_REPCNT = 0x0F,
> + RN5T568_PWRONTIMSET = 0x10,
> + RN5T568_NOETIMSETCNT= 0x11,
> + RN5T568_PWRIREN = 0x12,
> + RN5T568_PWRIRQ = 0x13,
> + RN5T568_PWRMON = 0x14,
> + RN5T568_PWRIRSEL= 0x15,
> +
> + RN5T568_DC1_SLOT= 0x16,
> + RN5T568_DC2_SLOT= 0x17,
> + RN5T568_DC3_SLOT= 0x18,
> + RN5T568_DC4_SLOT= 0x19,
> +
> + RN5T568_LDO1_SLOT = 0x1B,
> + RN5T568_LDO2_SLOT = 0x1C,
> + RN5T568_LDO3_SLOT = 0x1D,
> + RN5T568_LDO4_SLOT = 0x1E,
> + RN5T568_LDO5_SLOT = 0x1F,
> +
> + RN5T568_PSO0_SLOT = 0x25,
> + RN5T568_PSO1_SLOT = 0x26,
> + RN5T568_PSO2_SLOT = 0x27,
> + RN5T568_PSO3_SLOT = 0x28,
> +
> + RN5T568_LDORTC1_SLOT= 0x2A,
> +
> + RN5T568_DC1CTL = 0x2C,
> + RN5T568_DC1CTL2 = 0x2D,
> + RN5T568_DC2CTL = 0x2E,
> + RN5T568_DC2CTL2 = 0x2F,
> + RN5T568_DC3CTL = 0x30,
> + RN5T568_DC3CTL2 = 0x31,
> + RN5T568_DC4CTL = 0x32,
> + RN5T568_DC4CTL2 = 0x33,
> +
> + RN5T568_DC1DAC = 0x36,
> + RN5T568_DC2DAC = 0x37,
> + RN5T568_DC3DAC = 0x38,
> + RN5T568_DC4DAC = 0x39,
> +
> + RN5T568_DC1DAC_SLP = 0x3B,
> + RN5T568_DC2DAC_SLP = 0x3C,
> + RN5T568_DC3DAC_SLP = 0x3D,
> + RN5T568_DC4DAC_SLP = 0x3E,
> +
> + RN5T568_DCIREN = 0x40,
> + RN5T568_DCIRQ = 0x41,
> + RN5T568_DCIRMON = 0x42,
> +
> + RN5T568_LDOEN1 = 0x44,
> + RN5T568_LDOEN2 = 0x45,
> + RN5T568_LDODIS1 = 0x46,
> +
> + RN5T568_LDO1DAC = 0x4C,
> + RN5T568_LDO2DAC = 0x4D,
> + RN5T568_LDO3DAC = 0x4E,
> + RN5T568_LDO4DAC = 0x4F,
> + RN5T568_LDO5DAC = 0x50,
> +
> + RN5T568_LDORTC1DAC = 0x56,
> + RN5T568_LDORTC2DAC = 0x57,
> +
> + RN5T568_LDO1DAC_SLP = 0x58,
> + RN5T568_LDO2DAC_SLP = 0x59,
> + RN5T568_LDO3DAC_SLP = 0x5A,
> + RN5T568_LDO4DAC_SLP = 0x5B,
>
[PATCH] mfd: rn5t568: add complete register map to header and use it
This allows lowlevel board code to use these symbols to perform power
sequencing with the PBL PMIC helper functions.
Signed-off-by: Bastian Krause
---
drivers/mfd/rn5t568.c | 24 +---
include/mfd/rn5t568.h | 132 ++
2 files changed, 133 insertions(+), 23 deletions(-)
create mode 100644 include/mfd/rn5t568.h
diff --git a/drivers/mfd/rn5t568.c b/drivers/mfd/rn5t568.c
index 12de689734d..f1e2eeb0c88 100644
--- a/drivers/mfd/rn5t568.c
+++ b/drivers/mfd/rn5t568.c
@@ -16,29 +16,7 @@
#include
#include
#include
-
-#define RN5T568_LSIVER 0x00
-#define RN5T568_OTPVER 0x01
-#define RN5T568_PONHIS 0x09
-# define RN5T568_PONHIS_ON_EXTINPON BIT(3)
-# define RN5T568_PONHIS_ON_REPWRPON BIT(1)
-# define RN5T568_PONHIS_ON_PWRONPON BIT(0)
-#define RN5T568_POFFHIS 0x0a
-# define RN5T568_POFFHIS_N_OEPOFF BIT(7)
-# define RN5T568_POFFHIS_DCLIMPOFF BIT(6)
-# define RN5T568_POFFHIS_WDGPOFF BIT(5)
-# define RN5T568_POFFHIS_CPUPOFF BIT(4)
-# define RN5T568_POFFHIS_IODETPOFF BIT(3)
-# define RN5T568_POFFHIS_VINDETPOFF BIT(2)
-# define RN5T568_POFFHIS_TSHUTPOFF BIT(1)
-# define RN5T568_POFFHIS_PWRONPOFF BIT(0)
-#define RN5T568_SLPCNT 0x0e
-# define RN5T568_SLPCNT_SWPPWROFF BIT(0)
-#define RN5T568_REPCNT 0x0f
-# define RN5T568_REPCNT_OFF_RESETO_16MS 0x30
-# define RN5T568_REPCNT_OFF_REPWRTIM_1000MS 0x06
-# define RN5T568_REPCNT_OFF_REPWRON BIT(0)
-#define RN5T568_MAX_REG 0xbc
+#include
struct rn5t568 {
struct restart_handler restart;
diff --git a/include/mfd/rn5t568.h b/include/mfd/rn5t568.h
new file mode 100644
index 000..eff2b6dbe67
--- /dev/null
+++ b/include/mfd/rn5t568.h
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2014 Beniamino Galvani
+ * Copyright (C) 2016 Toradex AG
+ */
+
+#ifndef __MFD_RN5T568_H
+#define __MFD_RN5T568_H
+
+/* RN5T568 registers */
+enum {
+ RN5T568_LSIVER = 0x00,
+ RN5T568_OTPVER = 0x01,
+ RN5T568_IODAC = 0x02,
+ RN5T568_VINDAC = 0x03,
+ RN5T568_OUT32KEN= 0x05,
+
+ RN5T568_CPUCNT = 0x06,
+
+ RN5T568_PSWR= 0x07,
+ RN5T568_PONHIS = 0x09,
+ RN5T568_POFFHIS = 0x0A,
+ RN5T568_WATCHDOG= 0x0B,
+ RN5T568_WATCHDOGCNT = 0x0C,
+ RN5T568_PWRFUNC = 0x0D,
+ RN5T568_SLPCNT = 0x0E,
+ RN5T568_REPCNT = 0x0F,
+ RN5T568_PWRONTIMSET = 0x10,
+ RN5T568_NOETIMSETCNT= 0x11,
+ RN5T568_PWRIREN = 0x12,
+ RN5T568_PWRIRQ = 0x13,
+ RN5T568_PWRMON = 0x14,
+ RN5T568_PWRIRSEL= 0x15,
+
+ RN5T568_DC1_SLOT= 0x16,
+ RN5T568_DC2_SLOT= 0x17,
+ RN5T568_DC3_SLOT= 0x18,
+ RN5T568_DC4_SLOT= 0x19,
+
+ RN5T568_LDO1_SLOT = 0x1B,
+ RN5T568_LDO2_SLOT = 0x1C,
+ RN5T568_LDO3_SLOT = 0x1D,
+ RN5T568_LDO4_SLOT = 0x1E,
+ RN5T568_LDO5_SLOT = 0x1F,
+
+ RN5T568_PSO0_SLOT = 0x25,
+ RN5T568_PSO1_SLOT = 0x26,
+ RN5T568_PSO2_SLOT = 0x27,
+ RN5T568_PSO3_SLOT = 0x28,
+
+ RN5T568_LDORTC1_SLOT= 0x2A,
+
+ RN5T568_DC1CTL = 0x2C,
+ RN5T568_DC1CTL2 = 0x2D,
+ RN5T568_DC2CTL = 0x2E,
+ RN5T568_DC2CTL2 = 0x2F,
+ RN5T568_DC3CTL = 0x30,
+ RN5T568_DC3CTL2 = 0x31,
+ RN5T568_DC4CTL = 0x32,
+ RN5T568_DC4CTL2 = 0x33,
+
+ RN5T568_DC1DAC = 0x36,
+ RN5T568_DC2DAC = 0x37,
+ RN5T568_DC3DAC = 0x38,
+ RN5T568_DC4DAC = 0x39,
+
+ RN5T568_DC1DAC_SLP = 0x3B,
+ RN5T568_DC2DAC_SLP = 0x3C,
+ RN5T568_DC3DAC_SLP = 0x3D,
+ RN5T568_DC4DAC_SLP = 0x3E,
+
+ RN5T568_DCIREN = 0x40,
+ RN5T568_DCIRQ = 0x41,
+ RN5T568_DCIRMON = 0x42,
+
+ RN5T568_LDOEN1 = 0x44,
+ RN5T568_LDOEN2 = 0x45,
+ RN5T568_LDODIS1 = 0x46,
+
+ RN5T568_LDO1DAC = 0x4C,
+ RN5T568_LDO2DAC = 0x4D,
+ RN5T568_LDO3DAC = 0x4E,
+ RN5T568_LDO4DAC = 0x4F,
+ RN5T568_LDO5DAC = 0x50,
+
+ RN5T568_LDORTC1DAC = 0x56,
+ RN5T568_LDORTC2DAC = 0x57,
+
+ RN5T568_LDO1DAC_SLP = 0x58,
+ RN5T568_LDO2DAC_SLP = 0x59,
+ RN5T568_LDO3DAC_SLP = 0x5A,
+ RN5T568_LDO4DAC_SLP = 0x5B,
+ RN5T568_LDO5DAC_SLP = 0x5C,
+
+ RN5T568_IOSEL = 0x90,
+ RN5T568_IOOUT = 0x91,
+ RN5T568_GPEDGE1 = 0x92,
+ RN5T568_EN_GPIR = 0x94,
+ RN5T568_IR_GPR = 0x95,
+ RN5T568_IR_GPF = 0x96,
+ RN5T568_MON_IOIN= 0x97,
+ RN5T568_GPLED_FUNC = 0x98,
+ RN5T568_INTPOL = 0x9C,
+
Re: [PATCH] i2c: add pmic_reg_read() for PBL use
Hello Bastian,
On 19.12.23 17:11, Bastian Krause wrote:
> Add a common PMIC read function to PBL which allows easy porting of
> U-Boot's pmic_reg_read() in lowlevel board code.
>
> Signed-off-by: Bastian Krause
> ---
> include/pbl/pmic.h | 21 +
> 1 file changed, 21 insertions(+)
>
> diff --git a/include/pbl/pmic.h b/include/pbl/pmic.h
> index 0f882c5649d..bd0583370ec 100644
> --- a/include/pbl/pmic.h
> +++ b/include/pbl/pmic.h
> @@ -9,6 +9,27 @@ struct pmic_config {
> u8 val;
> };
>
> +static void pmic_reg_read(struct pbl_i2c *i2c, int addr, u8 reg, void *buf)
This should be static inline to avoid warnings for boards that don't use it.
> +{
> + int ret;
> + struct i2c_msg msg[] = {
> + {
> + .addr = addr,
> + .buf = ,
> + .len = 1,
> + }, {
> + .addr = addr,
> + .flags = I2C_M_RD,
> + .buf = buf,
U-Boot has buf of type u32 *. In your barebox implementation, only the
first byte is written, so this leaves 3 bytes potentially uninitialized.
You likely want to change void *buf to u32 *val and then
u8 buf[1];
/* i2c_xfer... */
*val = buf[0];
> + .len = 1,
> + },
> + };
> +
> + ret = pbl_i2c_xfer(i2c, msg, ARRAY_SIZE(msg));
> + if (ret != ARRAY_SIZE(msg))
> + pr_err("Failed to read from pmic@%x: %d\n", addr, ret);
> +}
Cheers,
Ahmad
> +
> static void pmic_reg_write(struct pbl_i2c *i2c, int addr, u8 reg, u8 val)
> {
> int ret;
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0|
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
[PATCH] i2c: add pmic_reg_read() for PBL use
Add a common PMIC read function to PBL which allows easy porting of
U-Boot's pmic_reg_read() in lowlevel board code.
Signed-off-by: Bastian Krause
---
include/pbl/pmic.h | 21 +
1 file changed, 21 insertions(+)
diff --git a/include/pbl/pmic.h b/include/pbl/pmic.h
index 0f882c5649d..bd0583370ec 100644
--- a/include/pbl/pmic.h
+++ b/include/pbl/pmic.h
@@ -9,6 +9,27 @@ struct pmic_config {
u8 val;
};
+static void pmic_reg_read(struct pbl_i2c *i2c, int addr, u8 reg, void *buf)
+{
+ int ret;
+ struct i2c_msg msg[] = {
+ {
+ .addr = addr,
+ .buf = ,
+ .len = 1,
+ }, {
+ .addr = addr,
+ .flags = I2C_M_RD,
+ .buf = buf,
+ .len = 1,
+ },
+ };
+
+ ret = pbl_i2c_xfer(i2c, msg, ARRAY_SIZE(msg));
+ if (ret != ARRAY_SIZE(msg))
+ pr_err("Failed to read from pmic@%x: %d\n", addr, ret);
+}
+
static void pmic_reg_write(struct pbl_i2c *i2c, int addr, u8 reg, u8 val)
{
int ret;
--
2.39.2
[PATCH] nvmem: regmap: Fix nvmem size
We should add 1 to the max_register index since counting is zero based. i.e. the stm32mp151 bsec has registers 0 - 95 with reg_stride 4. Size should be (95 + 1) * 4 = 384 bytes otherwise we can't access bsec register 95 (last one). Signed-off-by: Robin van der Gracht --- drivers/nvmem/regmap.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/nvmem/regmap.c b/drivers/nvmem/regmap.c index fa5405d7a8..ffc96a310f 100644 --- a/drivers/nvmem/regmap.c +++ b/drivers/nvmem/regmap.c @@ -78,7 +78,7 @@ nvmem_regmap_register_with_pp(struct regmap *map, const char *name, config.priv = map; config.stride = 1; config.word_size = 1; - config.size = regmap_get_max_register(map) * regmap_get_reg_stride(map); + config.size = (regmap_get_max_register(map) + 1) * regmap_get_reg_stride(map); config.cell_post_process = cell_post_process; config.reg_write = nvmem_regmap_write; config.reg_read = nvmem_regmap_read; -- 2.40.1
[PATCH] net: remove unused field from struct eth_device
Signed-off-by: Sascha Hauer
---
include/net.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/net.h b/include/net.h
index 83fb4def5d..40287a3503 100644
--- a/include/net.h
+++ b/include/net.h
@@ -49,7 +49,6 @@ struct eth_device {
/* Set promiscuous mode */
int (*set_promisc) (struct eth_device*, bool enable);
- struct eth_device *next;
void *priv;
void *rx_preprocessor_priv;
--
2.39.2
[PATCH] mci: imx-esdhc: add ls1028a support
Signed-off-by: Sascha Hauer
---
drivers/mci/imx-esdhc.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/mci/imx-esdhc.c b/drivers/mci/imx-esdhc.c
index d2a590a967..fb52c7b893 100644
--- a/drivers/mci/imx-esdhc.c
+++ b/drivers/mci/imx-esdhc.c
@@ -408,11 +408,15 @@ static struct esdhc_soc_data usdhc_imx6sx_data = {
.clkidx = "per",
};
-static struct esdhc_soc_data esdhc_ls_data = {
+static struct esdhc_soc_data esdhc_ls_be_data = {
.flags = ESDHC_FLAG_MULTIBLK_NO_INT | ESDHC_FLAG_BIGENDIAN |
ESDHC_FLAG_LAYERSCAPE,
};
+static struct esdhc_soc_data esdhc_ls_le_data = {
+ .flags = ESDHC_FLAG_MULTIBLK_NO_INT | ESDHC_FLAG_LAYERSCAPE,
+};
+
static __maybe_unused struct of_device_id fsl_esdhc_compatible[] = {
{ .compatible = "fsl,imx25-esdhc", .data = _imx25_data },
{ .compatible = "fsl,imx50-esdhc", .data = _imx53_data },
@@ -425,7 +429,8 @@ static __maybe_unused struct of_device_id
fsl_esdhc_compatible[] = {
{ .compatible = "fsl,imx8mm-usdhc", .data = _imx6sx_data },
{ .compatible = "fsl,imx8mn-usdhc", .data = _imx6sx_data },
{ .compatible = "fsl,imx8mp-usdhc", .data = _imx6sx_data },
- { .compatible = "fsl,ls1046a-esdhc",.data = _ls_data },
+ { .compatible = "fsl,ls1028a-esdhc",.data = _ls_le_data },
+ { .compatible = "fsl,ls1046a-esdhc",.data = _ls_be_data },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, fsl_esdhc_compatible);
--
2.39.2
[PATCH 2/2] clk: layerscape: add support for ls1028a
Signed-off-by: Sascha Hauer
---
drivers/clk/clk-qoric.c | 69 +
1 file changed, 69 insertions(+)
diff --git a/drivers/clk/clk-qoric.c b/drivers/clk/clk-qoric.c
index 49859077f6..6c69b5b3f3 100644
--- a/drivers/clk/clk-qoric.c
+++ b/drivers/clk/clk-qoric.c
@@ -143,6 +143,58 @@ static const struct clockgen_muxinfo clockgen2_cmux_cgb = {
},
};
+static const struct clockgen_muxinfo ls1028a_hwa1 = {
+ {
+ { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
+ { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
+ { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
+ { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
+ { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
+ {},
+ { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
+ { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
+ },
+};
+
+static const struct clockgen_muxinfo ls1028a_hwa2 = {
+ {
+ { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
+ { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
+ { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
+ { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
+ { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
+ {},
+ { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
+ { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
+ },
+};
+
+static const struct clockgen_muxinfo ls1028a_hwa3 = {
+ {
+ { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
+ { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
+ { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
+ { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
+ { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
+ {},
+ { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
+ { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
+ },
+};
+
+static const struct clockgen_muxinfo ls1028a_hwa4 = {
+ {
+ { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
+ { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
+ { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
+ { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
+ { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
+ {},
+ { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
+ { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
+ },
+};
+
static const struct clockgen_muxinfo ls1043a_hwa1 = {
{
{},
@@ -217,6 +269,15 @@ static const struct clockgen_chipinfo chipinfo_ls1021a = {
.pll_mask = 0x03,
};
+static const struct clockgen_chipinfo chipinfo_ls1028a = {
+ .compat = "fsl,ls1028a-clockgen",
+ .cmux_groups = { _cmux_cga12 },
+ .hwaccel = { _hwa1, _hwa2, _hwa3, _hwa4
},
+ .cmux_to_group = { 0, 0, 0, 0, -1 },
+ .pll_mask = 0x07,
+ .flags = CG_VER3 | CG_LITTLE_ENDIAN,
+};
+
static const struct clockgen_chipinfo chipinfo_ls1043a = {
.compat = "fsl,ls1043a-clockgen",
.init_periph = t2080_init_periph,
@@ -622,6 +683,11 @@ static void __maybe_unused clockgen_init_ls1021a(struct
device_node *np)
clockgen_init(np, _ls1021a);
}
+static void __maybe_unused clockgen_init_ls1028a(struct device_node *np)
+{
+ clockgen_init(np, _ls1028a);
+}
+
static void __maybe_unused clockgen_init_ls1043a(struct device_node *np)
{
clockgen_init(np, _ls1043a);
@@ -648,6 +714,9 @@ CLK_OF_DECLARE(qoriq_clockgen_ls1012a,
"fsl,ls1012a-clockgen", clockgen_init_ls1
#ifdef CONFIG_ARCH_LS1021
CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen",
clockgen_init_ls1021a);
#endif
+#ifdef CONFIG_ARCH_LS1028
+CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1028a-clockgen",
clockgen_init_ls1028a);
+#endif
#ifdef CONFIG_ARCH_LS1043
CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen",
clockgen_init_ls1043a);
#endif
--
2.39.2
[PATCH 1/2] clk: layerscape: move chipinfo_ls1012a further up
Cosmetic change to keep the chipinfo entries ordered.
Signed-off-by: Sascha Hauer
---
drivers/clk/clk-qoric.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/clk-qoric.c b/drivers/clk/clk-qoric.c
index 895810ccd1..49859077f6 100644
--- a/drivers/clk/clk-qoric.c
+++ b/drivers/clk/clk-qoric.c
@@ -203,6 +203,13 @@ static void __init t2080_init_periph(struct clockgen *cg)
cg->fman[0] = cg->hwaccel[0];
}
+static const struct clockgen_chipinfo chipinfo_ls1012a = {
+ .compat = "fsl,ls1012a-clockgen",
+ .cmux_groups = { _cmux },
+ .cmux_to_group = { 0, -1 },
+ .pll_mask = 0x03,
+};
+
static const struct clockgen_chipinfo chipinfo_ls1021a = {
.compat = "fsl,ls1021a-clockgen",
.cmux_groups = { _cmux },
@@ -238,13 +245,6 @@ static const struct clockgen_chipinfo chipinfo_ls1088a = {
.flags = CG_VER3 | CG_LITTLE_ENDIAN,
};
-static const struct clockgen_chipinfo chipinfo_ls1012a = {
- .compat = "fsl,ls1012a-clockgen",
- .cmux_groups = { _cmux },
- .cmux_to_group = { 0, -1 },
- .pll_mask = 0x03,
-};
-
static const struct clockgen_chipinfo chipinfo_ls2080a = {
.compat = "fsl,ls2080a-clockgen",
.cmux_groups = { _cmux_cga12, _cmux_cgb },
--
2.39.2
[PATCH 0/2] Layerscape LS1028a: add clk support
Adding clk support for LS1028a is straight forward. The changes are directly imported from Linux. Sascha Hauer (2): clk: layerscape: move chipinfo_ls1012a further up clk: layerscape: add support for ls1028a drivers/clk/clk-qoric.c | 83 + 1 file changed, 76 insertions(+), 7 deletions(-) -- 2.39.2
[PATCH 0/2] Layerscape LS1028a: add DDR support
The existing DDR driver can be re-used for LS1028a. We just have to swap the endianess of the register accesses. Sascha Hauer (2): fsl-ddr: remove duplicate prototype fsl-ddr: make endianess runtime decision arch/arm/boards/ls1021aiot/lowlevel.c | 2 +- arch/arm/boards/ls1046ardb/lowlevel.c | 2 +- arch/arm/boards/tqmls1046a/lowlevel.c | 2 +- drivers/ddr/fsl/arm_ddr_gen3.c| 7 ++- drivers/ddr/fsl/fsl_ddr.h | 1 - drivers/ddr/fsl/fsl_ddr_gen4.c| 7 ++- drivers/ddr/fsl/main.c| 13 -- include/soc/fsl/fsl_ddr_sdram.h | 65 --- 8 files changed, 74 insertions(+), 25 deletions(-) -- 2.39.2
[PATCH 2/2] fsl-ddr: make endianess runtime decision
Signed-off-by: Sascha Hauer
---
arch/arm/boards/ls1021aiot/lowlevel.c | 2 +-
arch/arm/boards/ls1046ardb/lowlevel.c | 2 +-
arch/arm/boards/tqmls1046a/lowlevel.c | 2 +-
drivers/ddr/fsl/arm_ddr_gen3.c| 7 ++-
drivers/ddr/fsl/fsl_ddr_gen4.c| 7 ++-
drivers/ddr/fsl/main.c| 13 --
include/soc/fsl/fsl_ddr_sdram.h | 65 ---
7 files changed, 74 insertions(+), 24 deletions(-)
diff --git a/arch/arm/boards/ls1021aiot/lowlevel.c
b/arch/arm/boards/ls1021aiot/lowlevel.c
index f255c425b7..6bba528635 100644
--- a/arch/arm/boards/ls1021aiot/lowlevel.c
+++ b/arch/arm/boards/ls1021aiot/lowlevel.c
@@ -91,7 +91,7 @@ static noinline __noreturn void ls1021aiot_r_entry(void)
udelay(500);
putc_ll('>');
- fsl_ddr_set_memctl_regs([0], 0);
+ fsl_ddr_set_memctl_regs([0], 0, false);
ls1021a_errata_post_ddr();
diff --git a/arch/arm/boards/ls1046ardb/lowlevel.c
b/arch/arm/boards/ls1046ardb/lowlevel.c
index e7544df86a..408e6017f6 100644
--- a/arch/arm/boards/ls1046ardb/lowlevel.c
+++ b/arch/arm/boards/ls1046ardb/lowlevel.c
@@ -209,7 +209,7 @@ static noinline __noreturn void ls1046ardb_r_entry(unsigned
long memsize)
goto err;
}
- memsize = fsl_ddr_sdram(_info);
+ memsize = fsl_ddr_sdram(_info, false);
ls1046a_errata_post_ddr();
diff --git a/arch/arm/boards/tqmls1046a/lowlevel.c
b/arch/arm/boards/tqmls1046a/lowlevel.c
index dc64762433..6a5ad1f83a 100644
--- a/arch/arm/boards/tqmls1046a/lowlevel.c
+++ b/arch/arm/boards/tqmls1046a/lowlevel.c
@@ -108,7 +108,7 @@ static noinline __noreturn void tqmls1046a_r_entry(void)
udelay(500);
putc_ll('>');
- fsl_ddr_set_memctl_regs([0], 0);
+ fsl_ddr_set_memctl_regs([0], 0, false);
ls1046a_errata_post_ddr();
diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c
index a8b96f1261..1cbdb1446f 100644
--- a/drivers/ddr/fsl/arm_ddr_gen3.c
+++ b/drivers/ddr/fsl/arm_ddr_gen3.c
@@ -21,7 +21,7 @@
* Dividing the initialization to two steps to deassert DDR reset signal
* to comply with JEDEC specs for RDIMMs.
*/
-void fsl_ddr_set_memctl_regs(struct fsl_ddr_controller *c, int step)
+void fsl_ddr_set_memctl_regs(struct fsl_ddr_controller *c, int step, bool
little_endian)
{
struct ccsr_ddr __iomem *ddr = c->base;
const fsl_ddr_cfg_regs_t *regs = >fsl_ddr_config_reg;
@@ -30,6 +30,11 @@ void fsl_ddr_set_memctl_regs(struct fsl_ddr_controller *c,
int step)
u32 total_gb_size_per_controller;
int timeout;
+ if (little_endian)
+ ddr_endianess = DDR_ENDIANESS_LE;
+ else
+ ddr_endianess = DDR_ENDIANESS_BE;
+
if (step == 2)
goto step2;
diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index 147ff9916d..19aa4f22a9 100644
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -36,7 +36,7 @@ static void set_wait_for_bits_clear(void *ptr, u32 value, u32
bits)
* Dividing the initialization to two steps to deassert DDR reset signal
* to comply with JEDEC specs for RDIMMs.
*/
-void fsl_ddr_set_memctl_regs(struct fsl_ddr_controller *c, int step)
+void fsl_ddr_set_memctl_regs(struct fsl_ddr_controller *c, int step, bool
little_endian)
{
struct ccsr_ddr __iomem *ddr = c->base;
const fsl_ddr_cfg_regs_t *regs = >fsl_ddr_config_reg;
@@ -53,6 +53,11 @@ void fsl_ddr_set_memctl_regs(struct fsl_ddr_controller *c,
int step)
u32 cs0_bnds, cs1_bnds, cs2_bnds, cs3_bnds, cs0_config;
mod_bnds = regs->cs[0].config & CTLR_INTLV_MASK;
+ if (little_endian)
+ ddr_endianess = DDR_ENDIANESS_LE;
+ else
+ ddr_endianess = DDR_ENDIANESS_BE;
+
if (step == 2)
goto step2;
diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c
index c05f6d52fb..27303fec7e 100644
--- a/drivers/ddr/fsl/main.c
+++ b/drivers/ddr/fsl/main.c
@@ -13,6 +13,8 @@
#include
#include "fsl_ddr.h"
+enum ddr_endianess ddr_endianess;
+
/*
* ASSUMPTIONS:
*- Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller
@@ -378,12 +380,17 @@ static unsigned long long fsl_ddr_compute(struct
fsl_ddr_info *pinfo)
return total_mem;
}
-phys_size_t fsl_ddr_sdram(struct fsl_ddr_info *pinfo)
+phys_size_t fsl_ddr_sdram(struct fsl_ddr_info *pinfo, bool little_endian)
{
unsigned int i;
unsigned long long total_memory;
int deassert_reset = 0;
+ if (little_endian)
+ ddr_endianess = DDR_ENDIANESS_LE;
+ else
+ ddr_endianess = DDR_ENDIANESS_BE;
+
total_memory = fsl_ddr_compute(pinfo);
/* setup 3-way interleaving before enabling DDRC */
@@ -428,14 +435,14 @@ phys_size_t fsl_ddr_sdram(struct fsl_ddr_info *pinfo)
* The following call with step = 1 returns before enabling
* the
[PATCH 1/2] fsl-ddr: remove duplicate prototype
Signed-off-by: Sascha Hauer --- drivers/ddr/fsl/fsl_ddr.h | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/ddr/fsl/fsl_ddr.h b/drivers/ddr/fsl/fsl_ddr.h index e95cea1657..0c1a30a236 100644 --- a/drivers/ddr/fsl/fsl_ddr.h +++ b/drivers/ddr/fsl/fsl_ddr.h @@ -189,7 +189,6 @@ static inline int is_ddr3_4(const memctl_options_t *popts) struct fsl_ddr_info; -phys_size_t fsl_ddr_sdram(struct fsl_ddr_info *pinfo); u32 fsl_ddr_get_intl3r(void); void board_mem_sleep_setup(void); -- 2.39.2
[PATCH] net: fsl_fman: gracefully exit of_fixup()
The fman OF fixup is registered independent of the actual devices, so do not assume there are any "fsl,fman" compatible nodes in the current device tree. Signed-off-by: Sascha Hauer --- drivers/net/fsl-fman.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/net/fsl-fman.c b/drivers/net/fsl-fman.c index ff32fa8fc7..c5fbeeda37 100644 --- a/drivers/net/fsl-fman.c +++ b/drivers/net/fsl-fman.c @@ -1348,7 +1348,12 @@ static int fman_of_fixup(struct device_node *root, void *context) struct device_node *child, *child_bb; fman_bb = of_find_compatible_node(NULL, NULL, "fsl,fman"); + if (!fman_bb) + return 0; + fman = of_find_compatible_node(root, NULL, "fsl,fman"); + if (!fman) + return 0; /* * The dts files in the Linux tree have all network interfaces -- 2.39.2
[PATCH] ARM: fix dmb on ARMv8
Add "sy" argument to the dmb instruction. This is optional for ARMv7,
but mandatory for ARMv8. On ARMv7 "dsb" and "dsb sy" are equivalent,
so use "dsb sy" on both ARMv7 and ARMv8 and drop the unnecessary #ifdef
Signed-off-by: Sascha Hauer
---
arch/arm/include/asm/system.h | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 9e88001533..bf3b7b02e2 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -25,12 +25,8 @@
#if __LINUX_ARM_ARCH__ >= 7
#define isb() __asm__ __volatile__ ("isb" : : : "memory")
-#ifdef CONFIG_CPU_64v8
#define dsb() __asm__ __volatile__ ("dsb sy" : : : "memory")
-#else
-#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
-#endif
-#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
+#define dmb() __asm__ __volatile__ ("dmb sy" : : : "memory")
#elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6
#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
: : "r" (0) : "memory")
--
2.39.2
[PATCH 1/4] pblimage: drop PowerPC support
PowerPC support has never been tested in the pblimage tool and will
hopefully be never needed. Drop its support from pblimage
Signed-off-by: Sascha Hauer
---
scripts/pblimage.c | 22 +-
1 file changed, 5 insertions(+), 17 deletions(-)
diff --git a/scripts/pblimage.c b/scripts/pblimage.c
index df5d7aef69..9489c52b18 100644
--- a/scripts/pblimage.c
+++ b/scripts/pblimage.c
@@ -60,12 +60,6 @@ static uint32_t pbl_cmd_initaddr;
static uint32_t pbi_crc_cmd1;
static uint32_t pbi_crc_cmd2;
-enum arch {
- ARCH_ARM,
- ARCH_POWERPC,
-};
-
-enum arch architecture = ARCH_ARM;
static char *rcwfile;
static char *pbifile;
static char *outfile;
@@ -253,17 +247,11 @@ static int pblimage_check_params(void)
exit(EXIT_FAILURE);
}
- if (architecture == ARCH_ARM) {
- pbi_crc_cmd1 = 0x61;
- pbi_crc_cmd2 = 0;
- pbl_cmd_initaddr = loadaddr & PBL_ADDR_24BIT_MASK;
- pbl_cmd_initaddr |= PBL_ACS_CONT_CMD;
- pbl_cmd_initaddr += image_size;
- } else {
- pbi_crc_cmd1 = 0x13;
- pbi_crc_cmd2 = 0x80;
- pbl_cmd_initaddr = 0x8200;
- }
+ pbi_crc_cmd1 = 0x61;
+ pbi_crc_cmd2 = 0;
+ pbl_cmd_initaddr = loadaddr & PBL_ADDR_24BIT_MASK;
+ pbl_cmd_initaddr |= PBL_ACS_CONT_CMD;
+ pbl_cmd_initaddr += image_size;
next_pbl_cmd = pbl_cmd_initaddr;
return 0;
--
2.39.2
[PATCH 4/4] pblimage: Add LS1028a support
The PBL images for the LS1028a are a bit different from the ones for the
LS1046a, but can be supported in the same pblimage tool. This adds
support for the LS1028a. To accomplish this the SoC type has to be
passed on the command line, so adjust the Makefiles calling pblimage
accordingly.
Signed-off-by: Sascha Hauer
---
images/Makefile.layerscape | 16 ++---
scripts/pblimage.c | 122 -
2 files changed, 116 insertions(+), 22 deletions(-)
diff --git a/images/Makefile.layerscape b/images/Makefile.layerscape
index 062e7263b5..e36dc5000a 100644
--- a/images/Makefile.layerscape
+++ b/images/Makefile.layerscape
@@ -13,30 +13,30 @@ quiet_cmd_lspbl_image = LSPBL-IMG $@
cmd_lspbl_image = $(CPP) $(lspbl_cfg_cpp_flags) -o $(lspbl-rcw-tmp)
$(word 2,$^) ; \
$(CPP) $(lspbl_cfg_cpp_flags) -o $(lspbl-pbi-tmp)
$(word 3,$^) ; \
$(objtree)/scripts/pblimage -o $@ -r $(lspbl-rcw-tmp) \
- -m $($(patsubst $(obj)/%.pblb,PBL_CODE_SIZE_%,$<)) -p
$(lspbl-pbi-tmp) -i $<
+ -c $(2) -m $($(patsubst
$(obj)/%.pblb,PBL_CODE_SIZE_%,$<)) -p $(lspbl-pbi-tmp) -i $<
quiet_cmd_lspbl_spi_image = LSPBL-SPI-IMG $@
cmd_lspbl_spi_image = $(CPP) $(lspbl_cfg_cpp_flags) -o $(lspbl-rcw-tmp)
$(word 2,$^) ; \
$(CPP) $(lspbl_cfg_cpp_flags) -o $(lspbl-pbi-tmp)
$(word 3,$^) ; \
$(objtree)/scripts/pblimage -o $@ -r
$(lspbl-rcw-tmp) -s \
- -m $($(patsubst $(obj)/%.pblb,PBL_CODE_SIZE_%,$<))
-p $(lspbl-pbi-tmp) -i $<
+ -c $(2) -m $($(patsubst
$(obj)/%.pblb,PBL_CODE_SIZE_%,$<)) -p $(lspbl-pbi-tmp) -i $<
pbl-$(CONFIG_MACH_LS1046ARDB) += start_ls1046ardb.pbl
$(obj)/barebox-ls1046ardb-sd.image: $(obj)/start_ls1046ardb.pblb \
$(board)/ls1046ardb/ls1046ardb_rcw_sd.cfg \
$(board)/ls1046ardb/ls1046ardb_pbi.cfg
- $(call if_changed,lspbl_image)
+ $(call if_changed,lspbl_image,ls1046a)
$(obj)/barebox-ls1046ardb-emmc.image: $(obj)/start_ls1046ardb.pblb \
$(board)/ls1046ardb/ls1046ardb_rcw_emmc.cfg \
$(board)/ls1046ardb/ls1046ardb_pbi.cfg
- $(call if_changed,lspbl_image)
+ $(call if_changed,lspbl_image,ls1046a)
$(obj)/barebox-ls1046ardb-qspi.image: $(obj)/start_ls1046ardb.pblb \
$(board)/ls1046ardb/ls1046ardb_rcw_qspi.cfg \
$(board)/ls1046ardb/ls1046ardb_pbi.cfg
- $(call if_changed,lspbl_spi_image)
+ $(call if_changed,lspbl_spi_image,ls1046a)
image-$(CONFIG_MACH_LS1046ARDB) += barebox-ls1046ardb-sd.image
barebox-ls1046ardb-qspi.image \
barebox-ls1046ardb-emmc.image
@@ -46,12 +46,12 @@ pbl-$(CONFIG_MACH_TQMLS1046A) += start_tqmls1046a.pbl
$(obj)/barebox-tqmls1046a-sd.image: $(obj)/start_tqmls1046a.pblb \
$(board)/tqmls1046a/tqmls1046a_rcw_sd__5559.cfg \
$(board)/tqmls1046a/tqmls1046a_pbi.cfg
- $(call if_changed,lspbl_image)
+ $(call if_changed,lspbl_image,ls1046a)
$(obj)/barebox-tqmls1046a-qspi.image: $(obj)/start_tqmls1046a.pblb \
$(board)/tqmls1046a/tqmls1046a_rcw_qspi__5559.cfg \
$(board)/tqmls1046a/tqmls1046a_pbi.cfg
- $(call if_changed,lspbl_spi_image)
+ $(call if_changed,lspbl_spi_image,ls1046a)
image-$(CONFIG_MACH_TQMLS1046A) += barebox-tqmls1046a-sd.image \
barebox-tqmls1046a-qspi.image
@@ -61,6 +61,6 @@ pbl-$(CONFIG_MACH_LS1021AIOT) += start_ls1021aiot.pbl
$(obj)/barebox-ls1021aiot-qspi.image: $(obj)/start_ls1021aiot.pblb \
$(board)/ls1021aiot/ls102xa_rcw_sd_qspi.cfg \
$(board)/ls1021aiot/ls102xa_pbi.cfg
- $(call if_changed,lspbl_spi_image)
+ $(call if_changed,lspbl_spi_image,ls1046a)
image-$(CONFIG_MACH_LS1021AIOT) += barebox-ls1021aiot-qspi.image
diff --git a/scripts/pblimage.c b/scripts/pblimage.c
index e8108bbb17..8cb473d5bc 100644
--- a/scripts/pblimage.c
+++ b/scripts/pblimage.c
@@ -14,6 +14,7 @@
#include
#include
#include
+#include
#include
#include "common.h"
@@ -55,6 +56,32 @@ static int spiimage;
static uint32_t pbi_crc_cmd1;
static uint32_t pbi_crc_cmd2;
+enum soc_type {
+ SOC_TYPE_INVALID,
+ SOC_TYPE_LS1046A,
+ SOC_TYPE_LS1028A,
+};
+
+struct soc_type_entry {
+ const char *name;
+ enum soc_type soc;
+ bool big_endian;
+};
+
+static struct soc_type_entry socs[] = {
+ {
+ .name = "ls1046a",
+ .soc = SOC_TYPE_LS1046A,
+ .big_endian = true,
+ }, {
+ .name = "ls1028a",
+ .soc = SOC_TYPE_LS1028A,
+ .big_endian = false,
+ },
+};
+
+static enum soc_type soc_type;
+
static char *rcwfile;
static char *pbifile;
static char *outfile;
@@ -113,9 +140,16 @@ static void check_get_hexval(const char *filename, int
lineno, char *token)
[PATCH 2/4] pblimage: simplify a bit
next_pbl_cmd is a global static variable that is initialized multiple
times, but used in a single function only. Instead of obfuscating its
usage, just pass its value as a parameter to generate_pbl_cmd().
Signed-off-by: Sascha Hauer
---
scripts/pblimage.c | 23 ---
1 file changed, 8 insertions(+), 15 deletions(-)
diff --git a/scripts/pblimage.c b/scripts/pblimage.c
index 9489c52b18..d0a589f2fe 100644
--- a/scripts/pblimage.c
+++ b/scripts/pblimage.c
@@ -39,10 +39,6 @@
*/
#define BAREBOX_START (128 * 1024)
-/*
- * Initialize to an invalid value.
- */
-static uint32_t next_pbl_cmd = 0x8200;
/*
* need to store all bytes in memory for calculating crc32, then write the
* bytes to image file for PBL boot.
@@ -56,7 +52,6 @@ static int out_fd;
static int in_fd;
static int spiimage;
-static uint32_t pbl_cmd_initaddr;
static uint32_t pbi_crc_cmd1;
static uint32_t pbi_crc_cmd2;
@@ -77,10 +72,8 @@ static uint32_t pbl_crc32(uint32_t in_crc, const char *buf,
uint32_t len)
* "xx" is the offset. Calculate the start offset by subtracting the size
of
* the image from the top of the allowable 24-bit range.
*/
-static void generate_pbl_cmd(void)
+static void generate_pbl_cmd(uint32_t val)
{
- uint32_t val = next_pbl_cmd;
- next_pbl_cmd += 0x40;
int i;
for (i = 3; i >= 0; i--) {
@@ -186,6 +179,7 @@ static void add_end_cmd(void)
static void pbl_load_image(void)
{
int size;
+ unsigned int n;
uint64_t *buf64 = (void *)mem_buf;
/* parse the rcw.cfg file. */
@@ -195,9 +189,12 @@ static void pbl_load_image(void)
if (pbifile)
pbl_parser(pbifile);
- next_pbl_cmd = pbl_cmd_initaddr - image_size;
- while (next_pbl_cmd < pbl_cmd_initaddr) {
- generate_pbl_cmd();
+ for (n = 0; n < image_size; n += 0x40) {
+ uint32_t pbl_cmd;
+
+ pbl_cmd = (loadaddr & PBL_ADDR_24BIT_MASK) | PBL_ACS_CONT_CMD;
+ pbl_cmd += n;
+ generate_pbl_cmd(pbl_cmd);
pbl_fget(64, in_fd);
}
@@ -249,11 +246,7 @@ static int pblimage_check_params(void)
pbi_crc_cmd1 = 0x61;
pbi_crc_cmd2 = 0;
- pbl_cmd_initaddr = loadaddr & PBL_ADDR_24BIT_MASK;
- pbl_cmd_initaddr |= PBL_ACS_CONT_CMD;
- pbl_cmd_initaddr += image_size;
- next_pbl_cmd = pbl_cmd_initaddr;
return 0;
};
--
2.39.2
[PATCH 3/4] pblimage: use roundup() from kernel.h
We already have roundup() defined in linux/kernel.h, so use it instead of adding a local definition. Signed-off-by: Sascha Hauer --- scripts/pblimage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/pblimage.c b/scripts/pblimage.c index d0a589f2fe..e8108bbb17 100644 --- a/scripts/pblimage.c +++ b/scripts/pblimage.c @@ -14,12 +14,12 @@ #include #include #include +#include #include "common.h" #include "common.c" #include "../crypto/crc32.c" -#define roundup(x, y) x) + ((y) - 1)) / (y)) * (y)) #define PBL_ACS_CONT_CMD 0x8100 #define PBL_ADDR_24BIT_MASK0x00ff -- 2.39.2
[PATCH 0/4] Layerscape LS1028a pblimage support
The pblimage tool can be re-used for upcoming LS1028a support. This series contains the necessary changes for the tool. Sascha Hauer (4): pblimage: drop PowerPC support pblimage: simplify a bit pblimage: use roundup() from kernel.h pblimage: Add LS1028a support images/Makefile.layerscape | 16 ++-- scripts/pblimage.c | 149 - 2 files changed, 120 insertions(+), 45 deletions(-) -- 2.39.2
[PATCH 0/6] PCI patches
These patches will be needed for upcoming Layerscape LS1028a support. This SoC has the Ethernet Complex in an Integrated Endpoint Root Complex. Sascha Hauer (6): pci: remove duplicate definition of pci_resource_start pci: Do not register device tree disabled devices pci: layerscape: limit fixup to layerscape controllers pci: fix __pci_bus_find_cap_start pci: implement Enhanced Allocation support pci: implement function level reset drivers/pci/bus.c| 3 + drivers/pci/pci-layerscape.c | 3 + drivers/pci/pci.c| 222 ++- include/linux/pci.h | 6 +- include/linux/pci_regs.h | 50 +++- 5 files changed, 277 insertions(+), 7 deletions(-) -- 2.39.2
[PATCH 4/6] pci: fix __pci_bus_find_cap_start
BIT(7) of dev->hdr_type has unrelated information. Mask out the upper
bit so that the capabilities can properly be found.
Signed-off-by: Sascha Hauer
---
drivers/pci/pci.c| 4 ++--
include/linux/pci_regs.h | 1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 638af9722e..0211fc0081 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -428,7 +428,7 @@ static unsigned int pci_scan_bus(struct pci_bus *bus)
pr_debug("%02x:%02x [%04x:%04x]\n", bus->number, dev->devfn,
dev->vendor, dev->device);
- switch (hdr_type & 0x7f) {
+ switch (hdr_type & PCI_HEADER_TYPE_MASK) {
case PCI_HEADER_TYPE_NORMAL:
if (class == PCI_CLASS_BRIDGE_PCI)
goto bad;
@@ -642,7 +642,7 @@ u8 pci_find_capability(struct pci_dev *dev, int cap)
{
u8 pos;
- pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
+ pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type &
PCI_HEADER_TYPE_MASK);
if (pos)
pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index 2c335f5835..631f218229 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -69,6 +69,7 @@
#define PCI_CACHE_LINE_SIZE0x0c/* 8 bits */
#define PCI_LATENCY_TIMER 0x0d/* 8 bits */
#define PCI_HEADER_TYPE0x0e/* 8 bits */
+#define PCI_HEADER_TYPE_MASK 0x7f
#define PCI_HEADER_TYPE_NORMAL0
#define PCI_HEADER_TYPE_BRIDGE1
#define PCI_HEADER_TYPE_CARDBUS 2
--
2.39.2
[PATCH 6/6] pci: implement function level reset
This will be needed for upcoming LS1028a support. The code is taken from
U-Boot which suffices for our usecase. The kernel code is much more
elaborated here.
Signed-off-by: Sascha Hauer
---
drivers/pci/pci.c | 32
include/linux/pci.h | 2 ++
2 files changed, 34 insertions(+)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index a3e7e70871..84678e40a9 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -553,6 +553,38 @@ pci_of_match_device(struct device *parent, unsigned int
devfn)
return NULL;
}
+/**
+ * pcie_flr - initiate a PCIe function level reset
+ * @dev: device to reset
+ *
+ * Initiate a function level reset on @dev.
+ */
+int pci_flr(struct pci_dev *pdev)
+{
+ u16 val;
+ int pcie_off;
+ u32 cap;
+
+ /* look for PCI Express Capability */
+ pcie_off = pci_find_capability(pdev, PCI_CAP_ID_EXP);
+ if (!pcie_off)
+ return -ENOENT;
+
+ /* check FLR capability */
+ pci_read_config_dword(pdev, pcie_off + PCI_EXP_DEVCAP, );
+ if (!(cap & PCI_EXP_DEVCAP_FLR))
+ return -ENOENT;
+
+ pci_read_config_word(pdev, pcie_off + PCI_EXP_DEVCTL, );
+ val |= PCI_EXP_DEVCTL_BCR_FLR;
+ pci_write_config_word(pdev, pcie_off + PCI_EXP_DEVCTL, val);
+
+ /* wait 100ms, per PCI spec */
+ mdelay(100);
+
+ return 0;
+}
+
static unsigned int pci_scan_bus(struct pci_bus *bus)
{
struct pci_dev *dev;
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 0e907209a7..fe5285116a 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -329,6 +329,8 @@ u8 pci_find_capability(struct pci_dev *dev, int cap);
extern void __iomem *pci_iomap(struct pci_dev *dev, int bar);
+int pci_flr(struct pci_dev *pdev);
+
/*
* The world is not perfect and supplies us with broken PCI devices.
* For at least a part of these bugs we need a work-around, so both
--
2.39.2
[PATCH 3/6] pci: layerscape: limit fixup to layerscape controllers
ls_pcie_fixup() assumes the fixed up device is attached to the layerscape PCI controller. This may not be true when there's another controller active in the system, so limit the execution of the fixup to the right controller only. Signed-off-by: Sascha Hauer --- drivers/pci/pci-layerscape.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/pci-layerscape.c b/drivers/pci/pci-layerscape.c index 0fb742af9a..12a0ec71a7 100644 --- a/drivers/pci/pci-layerscape.c +++ b/drivers/pci/pci-layerscape.c @@ -551,6 +551,9 @@ static void ls_pcie_fixup(struct pci_dev *pcidev) uint32_t devid; int base_bus_num = 0; + if (!of_match_device(ls_pcie_of_match, host->parent)) + return; + stream_id = ls_pcie_next_streamid(lspcie); index = ls_pcie_next_lut_index(lspcie); -- 2.39.2
[PATCH 2/6] pci: Do not register device tree disabled devices
Some PCI devices have device nodes associated with them. Do not register these devices when they are disabled in the device tree. Signed-off-by: Sascha Hauer --- drivers/pci/bus.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/bus.c b/drivers/pci/bus.c index fdd012733a..b6eab56d87 100644 --- a/drivers/pci/bus.c +++ b/drivers/pci/bus.c @@ -114,6 +114,9 @@ int pci_register_device(struct pci_dev *pdev) struct device *dev = >dev; int ret; + if (!of_device_is_available(pdev->dev.of_node)) + return 0; + dev_set_name(dev, "pci-%04x:%04x.", pdev->vendor, pdev->device); dev->bus = _bus; dev->id = DEVICE_ID_DYNAMIC; -- 2.39.2
[PATCH 5/6] pci: implement Enhanced Allocation support
Some PCI devices have their base addresses not defined in the BARs,
but instead have them defined in Enhanced Allocation structures.
Add support for these Enhanced Allocation structures, taken directly
from the Linux Kernel.
Motivation for adding this is the LS1028a SoC which uses Enhanced
Allocation for the Ethernet Subsystem which comes as an integrated
Endpoint Root Complex.
Signed-off-by: Sascha Hauer
---
drivers/pci/pci.c| 186 +++
include/linux/pci_regs.h | 49 ++-
2 files changed, 234 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 0211fc0081..a3e7e70871 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -4,6 +4,7 @@
#include
#include
#include
+#include
static unsigned int pci_scan_bus(struct pci_bus *bus);
@@ -152,6 +153,189 @@ static u32 pci_size(u32 base, u32 maxbase, u32 mask)
return size + 1;
}
+static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop)
+{
+ unsigned long flags = IORESOURCE_PCI_FIXED;
+
+ switch (prop) {
+ case PCI_EA_P_MEM:
+ case PCI_EA_P_VF_MEM:
+ flags |= IORESOURCE_MEM;
+ break;
+ case PCI_EA_P_MEM_PREFETCH:
+ case PCI_EA_P_VF_MEM_PREFETCH:
+ flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
+ break;
+ case PCI_EA_P_IO:
+ flags |= IORESOURCE_IO;
+ break;
+ default:
+ return 0;
+ }
+
+ return flags;
+}
+
+static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei,
+ u8 prop)
+{
+ if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO)
+ return >resource[bei];
+ else if (bei == PCI_EA_BEI_ROM)
+ return >resource[PCI_ROM_RESOURCE];
+ else
+ return NULL;
+}
+
+/* Read an Enhanced Allocation (EA) entry */
+static int pci_ea_read(struct pci_dev *dev, int offset)
+{
+ struct resource *res;
+ int ent_size, ent_offset = offset;
+ resource_size_t start, end;
+ unsigned long flags;
+ u32 dw0, bei, base, max_offset;
+ u8 prop;
+ bool support_64 = (sizeof(resource_size_t) >= 8);
+
+ pci_read_config_dword(dev, ent_offset, );
+ ent_offset += 4;
+
+ /* Entry size field indicates DWORDs after 1st */
+ ent_size = (FIELD_GET(PCI_EA_ES, dw0) + 1) << 2;
+
+ if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */
+ goto out;
+
+ bei = FIELD_GET(PCI_EA_BEI, dw0);
+ prop = FIELD_GET(PCI_EA_PP, dw0);
+
+ /*
+* If the Property is in the reserved range, try the Secondary
+* Property instead.
+*/
+ if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED)
+ prop = FIELD_GET(PCI_EA_SP, dw0);
+ if (prop > PCI_EA_P_BRIDGE_IO)
+ goto out;
+
+ res = pci_ea_get_resource(dev, bei, prop);
+ if (!res) {
+ dev_dbg(>dev, "Unsupported EA entry BEI: %u\n", bei);
+ goto out;
+ }
+
+ flags = pci_ea_flags(dev, prop);
+ if (!flags) {
+ dev_err(>dev, "Unsupported EA properties: %#x\n", prop);
+ goto out;
+ }
+
+ /* Read Base */
+ pci_read_config_dword(dev, ent_offset, );
+ start = (base & PCI_EA_FIELD_MASK);
+ ent_offset += 4;
+
+ /* Read MaxOffset */
+ pci_read_config_dword(dev, ent_offset, _offset);
+ ent_offset += 4;
+
+ /* Read Base MSBs (if 64-bit entry) */
+ if (base & PCI_EA_IS_64) {
+ u32 base_upper;
+
+ pci_read_config_dword(dev, ent_offset, _upper);
+ ent_offset += 4;
+
+ flags |= IORESOURCE_MEM_64;
+
+ /* entry starts above 32-bit boundary, can't use */
+ if (!support_64 && base_upper)
+ goto out;
+
+ if (support_64)
+ start |= ((u64)base_upper << 32);
+ }
+
+ end = start + (max_offset | 0x03);
+
+ /* Read MaxOffset MSBs (if 64-bit entry) */
+ if (max_offset & PCI_EA_IS_64) {
+ u32 max_offset_upper;
+
+ pci_read_config_dword(dev, ent_offset, _offset_upper);
+ ent_offset += 4;
+
+ flags |= IORESOURCE_MEM_64;
+
+ /* entry too big, can't use */
+ if (!support_64 && max_offset_upper)
+ goto out;
+
+ if (support_64)
+ end += ((u64)max_offset_upper << 32);
+ }
+
+ if (end < start) {
+ dev_err(>dev, "EA Entry crosses address boundary\n");
+ goto out;
+ }
+
+ if (ent_size != ent_offset - offset) {
+ dev_err(>dev, "EA Entry Size (%d) does not match length
read (%d)\n",
+ ent_size, ent_offset - offset);
+ goto out;
[PATCH 1/6] pci: remove duplicate definition of pci_resource_start
pci_resource_start is defined twice. Remove the duplicate.
Signed-off-by: Sascha Hauer
---
include/linux/pci.h | 4
1 file changed, 4 deletions(-)
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 98d056624f..0e907209a7 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -201,10 +201,6 @@ struct pci_driver {
#defineto_pci_driver(drv) container_of(drv, struct pci_driver, driver)
-/* these helpers provide future and backwards compatibility
- * for accessing popular PCI BAR info */
-#define pci_resource_start(dev, bar)((dev)->resource[(bar)].start)
-
/**
* DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
* @_table: device table name
--
2.39.2
