Re: [PATCH 1/2] ARM: boards: polyhex-debix: enable HAB support
Hello Marco, On 20.12.23 16:48, Marco Felsch wrote: > On 23-12-20, Ahmad Fatoum wrote: >> Hello Marco, >> >> On 20.12.23 15:54, Marco Felsch wrote: >>> From: Rouven Czerwinski >>> >>> Include the gencsf header to enable the secure-boot images. >>> >>> Signed-off-by: Rouven Czerwinski >> >> Any downside in just doing this for all i.MX8M boards? > > Thought about this too. If HABV4 is not enabled this will have no > impact. I didn't added the support for all boards since some custom > boards may don't want this. What about adding it to all EVK boards? I don't see why some boards wouldn't want this. I say, let's enable it for all. Cheers, Ahmad > > Regards, > Marco > >> Thanks, >> Ahmad >> >>> --- >>> arch/arm/boards/polyhex-debix/flash-header-polyhex-debix.imxcfg | 1 + >>> 1 file changed, 1 insertion(+) >>> >>> diff --git >>> a/arch/arm/boards/polyhex-debix/flash-header-polyhex-debix.imxcfg >>> b/arch/arm/boards/polyhex-debix/flash-header-polyhex-debix.imxcfg >>> index 663bd102e9a2..d619995496ac 100644 >>> --- a/arch/arm/boards/polyhex-debix/flash-header-polyhex-debix.imxcfg >>> +++ b/arch/arm/boards/polyhex-debix/flash-header-polyhex-debix.imxcfg >>> @@ -5,3 +5,4 @@ soc imx8mp >>> loadaddr 0x92 >>> max_load_size 0x3f000 >>> ivtofs 0x0 >>> +#include >> >> -- >> Pengutronix e.K. | | >> Steuerwalder Str. 21 | http://www.pengutronix.de/ | >> 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| >> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | >> >> > -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
Re: [PATCH 1/2] ARM: boards: polyhex-debix: enable HAB support
On 23-12-20, Ahmad Fatoum wrote: > Hello Marco, > > On 20.12.23 15:54, Marco Felsch wrote: > > From: Rouven Czerwinski > > > > Include the gencsf header to enable the secure-boot images. > > > > Signed-off-by: Rouven Czerwinski > > Any downside in just doing this for all i.MX8M boards? Thought about this too. If HABV4 is not enabled this will have no impact. I didn't added the support for all boards since some custom boards may don't want this. What about adding it to all EVK boards? Regards, Marco > Thanks, > Ahmad > > > --- > > arch/arm/boards/polyhex-debix/flash-header-polyhex-debix.imxcfg | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git > > a/arch/arm/boards/polyhex-debix/flash-header-polyhex-debix.imxcfg > > b/arch/arm/boards/polyhex-debix/flash-header-polyhex-debix.imxcfg > > index 663bd102e9a2..d619995496ac 100644 > > --- a/arch/arm/boards/polyhex-debix/flash-header-polyhex-debix.imxcfg > > +++ b/arch/arm/boards/polyhex-debix/flash-header-polyhex-debix.imxcfg > > @@ -5,3 +5,4 @@ soc imx8mp > > loadaddr 0x92 > > max_load_size 0x3f000 > > ivtofs 0x0 > > +#include > > -- > Pengutronix e.K. | | > Steuerwalder Str. 21 | http://www.pengutronix.de/ | > 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | > >
Re: [PATCH 1/2] ARM: boards: polyhex-debix: enable HAB support
Hello Marco, On 20.12.23 15:54, Marco Felsch wrote: > From: Rouven Czerwinski > > Include the gencsf header to enable the secure-boot images. > > Signed-off-by: Rouven Czerwinski Any downside in just doing this for all i.MX8M boards? Thanks, Ahmad > --- > arch/arm/boards/polyhex-debix/flash-header-polyhex-debix.imxcfg | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm/boards/polyhex-debix/flash-header-polyhex-debix.imxcfg > b/arch/arm/boards/polyhex-debix/flash-header-polyhex-debix.imxcfg > index 663bd102e9a2..d619995496ac 100644 > --- a/arch/arm/boards/polyhex-debix/flash-header-polyhex-debix.imxcfg > +++ b/arch/arm/boards/polyhex-debix/flash-header-polyhex-debix.imxcfg > @@ -5,3 +5,4 @@ soc imx8mp > loadaddr 0x92 > max_load_size 0x3f000 > ivtofs 0x0 > +#include -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
[PATCH 2/2] ARM: boards: polyhex-debix: fix file mode for 8g-lpddr4-timing.c
Drop the execution mode from the file. Signed-off-by: Marco Felsch --- arch/arm/boards/polyhex-debix/8g-lpddr4-timing.c | 0 1 file changed, 0 insertions(+), 0 deletions(-) mode change 100755 => 100644 arch/arm/boards/polyhex-debix/8g-lpddr4-timing.c diff --git a/arch/arm/boards/polyhex-debix/8g-lpddr4-timing.c b/arch/arm/boards/polyhex-debix/8g-lpddr4-timing.c old mode 100755 new mode 100644 -- 2.39.2
[PATCH 1/2] ARM: boards: polyhex-debix: enable HAB support
From: Rouven Czerwinski Include the gencsf header to enable the secure-boot images. Signed-off-by: Rouven Czerwinski --- arch/arm/boards/polyhex-debix/flash-header-polyhex-debix.imxcfg | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boards/polyhex-debix/flash-header-polyhex-debix.imxcfg b/arch/arm/boards/polyhex-debix/flash-header-polyhex-debix.imxcfg index 663bd102e9a2..d619995496ac 100644 --- a/arch/arm/boards/polyhex-debix/flash-header-polyhex-debix.imxcfg +++ b/arch/arm/boards/polyhex-debix/flash-header-polyhex-debix.imxcfg @@ -5,3 +5,4 @@ soc imx8mp loadaddr 0x92 max_load_size 0x3f000 ivtofs 0x0 +#include -- 2.39.2
Re: [PATCH v2] nvmem: regmap: Fix nvmem size
Hi Ahmad,
On 2023-12-20 10:00, Ahmad Fatoum wrote:
Hello Robin,
Thanks for the fix.
On 20.12.23 09:29, Robin van der Gracht wrote:
- if (roffset + rbytes > stride * regmap_get_max_register(map))
+ if (roffset + rbytes > regmap_size_bytes(map) * stride)
Shouldn't stride on the right hand side be dropped?
roffset = register index * stride.
I.e. 380 for register with index 95.
For stm32mp1x bsec:
map->format.val_bytes = 4
map->reg_stride = 4
regmap_size_bytes() = map->format.val_bytes * (95 + 1) / map->reg_stride
= 96
So the result with the stride on the right size is correct.
I moved stride from left to right to be consistent with the size
calculation
in nvmem_regmap_register_with_pp()
Kind regards,
Robin
Cheers,
Ahmad
return -EINVAL;
for (i = roffset; i < roffset + rbytes; i += stride) {
@@ -78,7 +78,7 @@ nvmem_regmap_register_with_pp(struct regmap *map,
const char *name,
config.priv = map;
config.stride = 1;
config.word_size = 1;
- config.size = regmap_get_max_register(map) *
regmap_get_reg_stride(map);
+ config.size = regmap_size_bytes(map) * regmap_get_reg_stride(map);
config.cell_post_process = cell_post_process;
config.reg_write = nvmem_regmap_write;
config.reg_read = nvmem_regmap_read;
Re: [PATCH v2] mfd: rn5t568: add complete register map to header and use it
On 20.12.23 11:43, Bastian Krause wrote:
> This allows lowlevel board code to use these symbols to perform power
> sequencing with the PBL PMIC helper functions.
>
> Signed-off-by: Bastian Krause
Reviewed-by: Ahmad Fatoum
> ---
> Changes since (implicit) v1:
> - add missing include of linux/bits.h as suggested by Ahmad
> ---
> drivers/mfd/rn5t568.c | 24 +---
> include/mfd/rn5t568.h | 134 ++
> 2 files changed, 135 insertions(+), 23 deletions(-)
> create mode 100644 include/mfd/rn5t568.h
>
> diff --git a/drivers/mfd/rn5t568.c b/drivers/mfd/rn5t568.c
> index 12de689734d..f1e2eeb0c88 100644
> --- a/drivers/mfd/rn5t568.c
> +++ b/drivers/mfd/rn5t568.c
> @@ -16,29 +16,7 @@
> #include
> #include
> #include
> -
> -#define RN5T568_LSIVER 0x00
> -#define RN5T568_OTPVER 0x01
> -#define RN5T568_PONHIS 0x09
> -# define RN5T568_PONHIS_ON_EXTINPON BIT(3)
> -# define RN5T568_PONHIS_ON_REPWRPON BIT(1)
> -# define RN5T568_PONHIS_ON_PWRONPON BIT(0)
> -#define RN5T568_POFFHIS 0x0a
> -# define RN5T568_POFFHIS_N_OEPOFF BIT(7)
> -# define RN5T568_POFFHIS_DCLIMPOFF BIT(6)
> -# define RN5T568_POFFHIS_WDGPOFF BIT(5)
> -# define RN5T568_POFFHIS_CPUPOFF BIT(4)
> -# define RN5T568_POFFHIS_IODETPOFF BIT(3)
> -# define RN5T568_POFFHIS_VINDETPOFF BIT(2)
> -# define RN5T568_POFFHIS_TSHUTPOFF BIT(1)
> -# define RN5T568_POFFHIS_PWRONPOFF BIT(0)
> -#define RN5T568_SLPCNT 0x0e
> -# define RN5T568_SLPCNT_SWPPWROFF BIT(0)
> -#define RN5T568_REPCNT 0x0f
> -# define RN5T568_REPCNT_OFF_RESETO_16MS 0x30
> -# define RN5T568_REPCNT_OFF_REPWRTIM_1000MS 0x06
> -# define RN5T568_REPCNT_OFF_REPWRON BIT(0)
> -#define RN5T568_MAX_REG 0xbc
> +#include
>
> struct rn5t568 {
> struct restart_handler restart;
> diff --git a/include/mfd/rn5t568.h b/include/mfd/rn5t568.h
> new file mode 100644
> index 000..04b6c832a5d
> --- /dev/null
> +++ b/include/mfd/rn5t568.h
> @@ -0,0 +1,134 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2014 Beniamino Galvani
> + * Copyright (C) 2016 Toradex AG
> + */
> +
> +#ifndef __MFD_RN5T568_H
> +#define __MFD_RN5T568_H
> +
> +#include
> +
> +/* RN5T568 registers */
> +enum {
> + RN5T568_LSIVER = 0x00,
> + RN5T568_OTPVER = 0x01,
> + RN5T568_IODAC = 0x02,
> + RN5T568_VINDAC = 0x03,
> + RN5T568_OUT32KEN= 0x05,
> +
> + RN5T568_CPUCNT = 0x06,
> +
> + RN5T568_PSWR= 0x07,
> + RN5T568_PONHIS = 0x09,
> + RN5T568_POFFHIS = 0x0A,
> + RN5T568_WATCHDOG= 0x0B,
> + RN5T568_WATCHDOGCNT = 0x0C,
> + RN5T568_PWRFUNC = 0x0D,
> + RN5T568_SLPCNT = 0x0E,
> + RN5T568_REPCNT = 0x0F,
> + RN5T568_PWRONTIMSET = 0x10,
> + RN5T568_NOETIMSETCNT= 0x11,
> + RN5T568_PWRIREN = 0x12,
> + RN5T568_PWRIRQ = 0x13,
> + RN5T568_PWRMON = 0x14,
> + RN5T568_PWRIRSEL= 0x15,
> +
> + RN5T568_DC1_SLOT= 0x16,
> + RN5T568_DC2_SLOT= 0x17,
> + RN5T568_DC3_SLOT= 0x18,
> + RN5T568_DC4_SLOT= 0x19,
> +
> + RN5T568_LDO1_SLOT = 0x1B,
> + RN5T568_LDO2_SLOT = 0x1C,
> + RN5T568_LDO3_SLOT = 0x1D,
> + RN5T568_LDO4_SLOT = 0x1E,
> + RN5T568_LDO5_SLOT = 0x1F,
> +
> + RN5T568_PSO0_SLOT = 0x25,
> + RN5T568_PSO1_SLOT = 0x26,
> + RN5T568_PSO2_SLOT = 0x27,
> + RN5T568_PSO3_SLOT = 0x28,
> +
> + RN5T568_LDORTC1_SLOT= 0x2A,
> +
> + RN5T568_DC1CTL = 0x2C,
> + RN5T568_DC1CTL2 = 0x2D,
> + RN5T568_DC2CTL = 0x2E,
> + RN5T568_DC2CTL2 = 0x2F,
> + RN5T568_DC3CTL = 0x30,
> + RN5T568_DC3CTL2 = 0x31,
> + RN5T568_DC4CTL = 0x32,
> + RN5T568_DC4CTL2 = 0x33,
> +
> + RN5T568_DC1DAC = 0x36,
> + RN5T568_DC2DAC = 0x37,
> + RN5T568_DC3DAC = 0x38,
> + RN5T568_DC4DAC = 0x39,
> +
> + RN5T568_DC1DAC_SLP = 0x3B,
> + RN5T568_DC2DAC_SLP = 0x3C,
> + RN5T568_DC3DAC_SLP = 0x3D,
> + RN5T568_DC4DAC_SLP = 0x3E,
> +
> + RN5T568_DCIREN = 0x40,
> + RN5T568_DCIRQ = 0x41,
> + RN5T568_DCIRMON = 0x42,
> +
> + RN5T568_LDOEN1 = 0x44,
> + RN5T568_LDOEN2 = 0x45,
> + RN5T568_LDODIS1 = 0x46,
> +
> + RN5T568_LDO1DAC = 0x4C,
> + RN5T568_LDO2DAC = 0x4D,
> + RN5T568_LDO3DAC = 0x4E,
> + RN5T568_LDO4DAC = 0x4F,
> + RN5T568_LDO5DAC = 0x50,
> +
> + RN5T568_LDORTC1DAC = 0x56,
> + RN5T568_LDORTC2DAC = 0x57,
> +
> + RN5T568_LDO1DAC_SLP = 0x58,
> + RN5T568_LDO2DAC_SLP = 0x59,
> + RN5T568_LDO3DAC_SLP = 0x5A,
> + RN5T568_LDO4DAC_SLP = 0x5B,
> + RN5T568_LDO5DAC_SLP = 0x5C,
> +
> + RN5T568_IOSEL
Re: [PATCH v2] i2c: add pmic_reg_read() for PBL use
On 20.12.23 11:47, Bastian Krause wrote:
> Add a common PMIC read function to PBL which allows easy porting of
> U-Boot's pmic_reg_read() in lowlevel board code.
>
> Signed-off-by: Bastian Krause
Reviewed-by: Ahmad Fatoum
> ---
> Changes since (implicit) v1:
> - make function static inline as suggested by Ahmad
> - change void *buf to u32 *val to resemble's U-Boot's pmic_reg_read() as
> suggested by Ahmad
> ---
> include/pbl/pmic.h | 24
> 1 file changed, 24 insertions(+)
>
> diff --git a/include/pbl/pmic.h b/include/pbl/pmic.h
> index 0f882c5649d..431d46c 100644
> --- a/include/pbl/pmic.h
> +++ b/include/pbl/pmic.h
> @@ -9,6 +9,30 @@ struct pmic_config {
> u8 val;
> };
>
> +static inline void pmic_reg_read(struct pbl_i2c *i2c, int addr, u8 reg, u32
> *val)
> +{
> + int ret;
> + u8 buf[1];
> + struct i2c_msg msg[] = {
> + {
> + .addr = addr,
> + .buf = ,
> + .len = 1,
> + }, {
> + .addr = addr,
> + .flags = I2C_M_RD,
> + .buf = buf,
> + .len = 1,
> + },
> + };
> +
> + ret = pbl_i2c_xfer(i2c, msg, ARRAY_SIZE(msg));
> + if (ret != ARRAY_SIZE(msg))
> + pr_err("Failed to read from pmic@%x: %d\n", addr, ret);
> +
> + *val = buf[0];
> +}
> +
> static void pmic_reg_write(struct pbl_i2c *i2c, int addr, u8 reg, u8 val)
> {
> int ret;
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0|
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
[PATCH v2] i2c: add pmic_reg_read() for PBL use
Add a common PMIC read function to PBL which allows easy porting of
U-Boot's pmic_reg_read() in lowlevel board code.
Signed-off-by: Bastian Krause
---
Changes since (implicit) v1:
- make function static inline as suggested by Ahmad
- change void *buf to u32 *val to resemble's U-Boot's pmic_reg_read() as
suggested by Ahmad
---
include/pbl/pmic.h | 24
1 file changed, 24 insertions(+)
diff --git a/include/pbl/pmic.h b/include/pbl/pmic.h
index 0f882c5649d..431d46c 100644
--- a/include/pbl/pmic.h
+++ b/include/pbl/pmic.h
@@ -9,6 +9,30 @@ struct pmic_config {
u8 val;
};
+static inline void pmic_reg_read(struct pbl_i2c *i2c, int addr, u8 reg, u32
*val)
+{
+ int ret;
+ u8 buf[1];
+ struct i2c_msg msg[] = {
+ {
+ .addr = addr,
+ .buf = ,
+ .len = 1,
+ }, {
+ .addr = addr,
+ .flags = I2C_M_RD,
+ .buf = buf,
+ .len = 1,
+ },
+ };
+
+ ret = pbl_i2c_xfer(i2c, msg, ARRAY_SIZE(msg));
+ if (ret != ARRAY_SIZE(msg))
+ pr_err("Failed to read from pmic@%x: %d\n", addr, ret);
+
+ *val = buf[0];
+}
+
static void pmic_reg_write(struct pbl_i2c *i2c, int addr, u8 reg, u8 val)
{
int ret;
--
2.39.2
[PATCH v2] mfd: rn5t568: add complete register map to header and use it
This allows lowlevel board code to use these symbols to perform power
sequencing with the PBL PMIC helper functions.
Signed-off-by: Bastian Krause
---
Changes since (implicit) v1:
- add missing include of linux/bits.h as suggested by Ahmad
---
drivers/mfd/rn5t568.c | 24 +---
include/mfd/rn5t568.h | 134 ++
2 files changed, 135 insertions(+), 23 deletions(-)
create mode 100644 include/mfd/rn5t568.h
diff --git a/drivers/mfd/rn5t568.c b/drivers/mfd/rn5t568.c
index 12de689734d..f1e2eeb0c88 100644
--- a/drivers/mfd/rn5t568.c
+++ b/drivers/mfd/rn5t568.c
@@ -16,29 +16,7 @@
#include
#include
#include
-
-#define RN5T568_LSIVER 0x00
-#define RN5T568_OTPVER 0x01
-#define RN5T568_PONHIS 0x09
-# define RN5T568_PONHIS_ON_EXTINPON BIT(3)
-# define RN5T568_PONHIS_ON_REPWRPON BIT(1)
-# define RN5T568_PONHIS_ON_PWRONPON BIT(0)
-#define RN5T568_POFFHIS 0x0a
-# define RN5T568_POFFHIS_N_OEPOFF BIT(7)
-# define RN5T568_POFFHIS_DCLIMPOFF BIT(6)
-# define RN5T568_POFFHIS_WDGPOFF BIT(5)
-# define RN5T568_POFFHIS_CPUPOFF BIT(4)
-# define RN5T568_POFFHIS_IODETPOFF BIT(3)
-# define RN5T568_POFFHIS_VINDETPOFF BIT(2)
-# define RN5T568_POFFHIS_TSHUTPOFF BIT(1)
-# define RN5T568_POFFHIS_PWRONPOFF BIT(0)
-#define RN5T568_SLPCNT 0x0e
-# define RN5T568_SLPCNT_SWPPWROFF BIT(0)
-#define RN5T568_REPCNT 0x0f
-# define RN5T568_REPCNT_OFF_RESETO_16MS 0x30
-# define RN5T568_REPCNT_OFF_REPWRTIM_1000MS 0x06
-# define RN5T568_REPCNT_OFF_REPWRON BIT(0)
-#define RN5T568_MAX_REG 0xbc
+#include
struct rn5t568 {
struct restart_handler restart;
diff --git a/include/mfd/rn5t568.h b/include/mfd/rn5t568.h
new file mode 100644
index 000..04b6c832a5d
--- /dev/null
+++ b/include/mfd/rn5t568.h
@@ -0,0 +1,134 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2014 Beniamino Galvani
+ * Copyright (C) 2016 Toradex AG
+ */
+
+#ifndef __MFD_RN5T568_H
+#define __MFD_RN5T568_H
+
+#include
+
+/* RN5T568 registers */
+enum {
+ RN5T568_LSIVER = 0x00,
+ RN5T568_OTPVER = 0x01,
+ RN5T568_IODAC = 0x02,
+ RN5T568_VINDAC = 0x03,
+ RN5T568_OUT32KEN= 0x05,
+
+ RN5T568_CPUCNT = 0x06,
+
+ RN5T568_PSWR= 0x07,
+ RN5T568_PONHIS = 0x09,
+ RN5T568_POFFHIS = 0x0A,
+ RN5T568_WATCHDOG= 0x0B,
+ RN5T568_WATCHDOGCNT = 0x0C,
+ RN5T568_PWRFUNC = 0x0D,
+ RN5T568_SLPCNT = 0x0E,
+ RN5T568_REPCNT = 0x0F,
+ RN5T568_PWRONTIMSET = 0x10,
+ RN5T568_NOETIMSETCNT= 0x11,
+ RN5T568_PWRIREN = 0x12,
+ RN5T568_PWRIRQ = 0x13,
+ RN5T568_PWRMON = 0x14,
+ RN5T568_PWRIRSEL= 0x15,
+
+ RN5T568_DC1_SLOT= 0x16,
+ RN5T568_DC2_SLOT= 0x17,
+ RN5T568_DC3_SLOT= 0x18,
+ RN5T568_DC4_SLOT= 0x19,
+
+ RN5T568_LDO1_SLOT = 0x1B,
+ RN5T568_LDO2_SLOT = 0x1C,
+ RN5T568_LDO3_SLOT = 0x1D,
+ RN5T568_LDO4_SLOT = 0x1E,
+ RN5T568_LDO5_SLOT = 0x1F,
+
+ RN5T568_PSO0_SLOT = 0x25,
+ RN5T568_PSO1_SLOT = 0x26,
+ RN5T568_PSO2_SLOT = 0x27,
+ RN5T568_PSO3_SLOT = 0x28,
+
+ RN5T568_LDORTC1_SLOT= 0x2A,
+
+ RN5T568_DC1CTL = 0x2C,
+ RN5T568_DC1CTL2 = 0x2D,
+ RN5T568_DC2CTL = 0x2E,
+ RN5T568_DC2CTL2 = 0x2F,
+ RN5T568_DC3CTL = 0x30,
+ RN5T568_DC3CTL2 = 0x31,
+ RN5T568_DC4CTL = 0x32,
+ RN5T568_DC4CTL2 = 0x33,
+
+ RN5T568_DC1DAC = 0x36,
+ RN5T568_DC2DAC = 0x37,
+ RN5T568_DC3DAC = 0x38,
+ RN5T568_DC4DAC = 0x39,
+
+ RN5T568_DC1DAC_SLP = 0x3B,
+ RN5T568_DC2DAC_SLP = 0x3C,
+ RN5T568_DC3DAC_SLP = 0x3D,
+ RN5T568_DC4DAC_SLP = 0x3E,
+
+ RN5T568_DCIREN = 0x40,
+ RN5T568_DCIRQ = 0x41,
+ RN5T568_DCIRMON = 0x42,
+
+ RN5T568_LDOEN1 = 0x44,
+ RN5T568_LDOEN2 = 0x45,
+ RN5T568_LDODIS1 = 0x46,
+
+ RN5T568_LDO1DAC = 0x4C,
+ RN5T568_LDO2DAC = 0x4D,
+ RN5T568_LDO3DAC = 0x4E,
+ RN5T568_LDO4DAC = 0x4F,
+ RN5T568_LDO5DAC = 0x50,
+
+ RN5T568_LDORTC1DAC = 0x56,
+ RN5T568_LDORTC2DAC = 0x57,
+
+ RN5T568_LDO1DAC_SLP = 0x58,
+ RN5T568_LDO2DAC_SLP = 0x59,
+ RN5T568_LDO3DAC_SLP = 0x5A,
+ RN5T568_LDO4DAC_SLP = 0x5B,
+ RN5T568_LDO5DAC_SLP = 0x5C,
+
+ RN5T568_IOSEL = 0x90,
+ RN5T568_IOOUT = 0x91,
+ RN5T568_GPEDGE1 = 0x92,
+ RN5T568_EN_GPIR = 0x94,
+ RN5T568_IR_GPR = 0x95,
+ RN5T568_IR_GPF = 0x96,
+
Re: [PATCH v2] nvmem: regmap: Fix nvmem size
Hello Robin,
Thanks for the fix.
On 20.12.23 09:29, Robin van der Gracht wrote:
> - if (roffset + rbytes > stride * regmap_get_max_register(map))
> + if (roffset + rbytes > regmap_size_bytes(map) * stride)
Shouldn't stride on the right hand side be dropped?
Cheers,
Ahmad
> return -EINVAL;
>
> for (i = roffset; i < roffset + rbytes; i += stride) {
> @@ -78,7 +78,7 @@ nvmem_regmap_register_with_pp(struct regmap *map, const
> char *name,
> config.priv = map;
> config.stride = 1;
> config.word_size = 1;
> - config.size = regmap_get_max_register(map) * regmap_get_reg_stride(map);
> + config.size = regmap_size_bytes(map) * regmap_get_reg_stride(map);
> config.cell_post_process = cell_post_process;
> config.reg_write = nvmem_regmap_write;
> config.reg_read = nvmem_regmap_read;
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0|
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
[PATCH v2] nvmem: regmap: Fix nvmem size
We should add 1 to the max_register index since counting is zero based.
i.e. the stm32mp151 bsec has registers 0 - 95 with reg_stride 4.
Size should be (95 + 1) * 4 = 384 bytes otherwise we can't access bsec
register 95 (last one).
regmap_size_bytes() does take the +1 into account so we can use that.
Signed-off-by: Robin van der Gracht
---
v2: Fix the size calculation in nvmem_regmap_read() as well.
drivers/nvmem/regmap.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/nvmem/regmap.c b/drivers/nvmem/regmap.c
index fa5405d7a8..b923c5787d 100644
--- a/drivers/nvmem/regmap.c
+++ b/drivers/nvmem/regmap.c
@@ -38,7 +38,7 @@ static int nvmem_regmap_read(void *ctx, unsigned offset, void
*buf, size_t bytes
skip_bytes = offset & (stride - 1);
rbytes = roundup(bytes + skip_bytes, stride);
- if (roffset + rbytes > stride * regmap_get_max_register(map))
+ if (roffset + rbytes > regmap_size_bytes(map) * stride)
return -EINVAL;
for (i = roffset; i < roffset + rbytes; i += stride) {
@@ -78,7 +78,7 @@ nvmem_regmap_register_with_pp(struct regmap *map, const char
*name,
config.priv = map;
config.stride = 1;
config.word_size = 1;
- config.size = regmap_get_max_register(map) * regmap_get_reg_stride(map);
+ config.size = regmap_size_bytes(map) * regmap_get_reg_stride(map);
config.cell_post_process = cell_post_process;
config.reg_write = nvmem_regmap_write;
config.reg_read = nvmem_regmap_read;
--
2.40.1
