Re: Major memory performance decline from u-boot to barebox
Am Montag, dem 08.07.2024 um 13:41 +0200 schrieb Enrico Scholz: > Lucas Stach writes: > > > > I have a karo tx6s module (imx6s, 512 MiB RAM) which is shipped with an > > > ancient u-boot 2015 bootloader. > > > > > > barebox 2024.07 works out-of-the box on it. But under the booted linux > > > system a see a major regression in memory performance. > > > > The most likely cause is that Barebox applies the workaround for ARM > > erratum 845369, which has a major impact on streaming writes and thus > > both memset and memcpy performance. The old U-Boot probably does not > > include this workaround. > > > > You may check this theory by removing the call to > > enable_arm_errata_845369_war in imx6_cpu_lowlevel_init. > > Thanks; after disabling this workaround, benchmarks are reporting high > numbers again. > Note that while benchmarks are affected heavily, most real workloads don't exhibit a dramatic loss in performance, at least when they don't move a lot of data via the CPU, which is a bad idea on this platform anyway. > Would it make sense to enable this workaround conditionally? E.g. the > imx6s is not affected by this erratum because it has only one core and > no ACP. Yes, this might make sense. The call activating the workaround in imx6_cpu_lowlevel_init could be guarded by reading the number of available CPU cores from the SCU, only installing the workaround if there is more than a single CPU present. Regards, Lucas
Re: Major memory performance decline from u-boot to barebox
Hi Enrico, Am Montag, dem 08.07.2024 um 12:22 +0200 schrieb Enrico Scholz: > Hello, > > I have a karo tx6s module (imx6s, 512 MiB RAM) which is shipped with an > ancient u-boot 2015 bootloader. > > barebox 2024.07 works out-of-the box on it. But under the booted linux > system a see a major regression in memory performance. > > E.g. u-boot has > > > # hdparm -tT /dev/mmcblk3 > > Timing cached reads: 1236 MB in 2.00 seconds = 618.46 MB/sec > > while barebox shows only > > > Timing cached reads:574 MB in 2.00 seconds = 287.08 MB/sec > > > Running tinymembench[1] shows that pure memory read operations are not > affected; e.g. both variants report around > > > NEON read : 1398.5 MB/s > > > But write operations differ by a factor of 4-5: > > > standard memset : 2054.4 MB/s > > on u-boot vs. barebox with > > > standard memset :472.7 MB/s > > > I modified barebox to use the same DCD like u-boot; resulting MMDC > registers are nearly identical[2]. /sys/kernel/debug/clk/clk_summary > is also nearly the same (only LVDS1_SEL (unused) has another parent). > TZASC is not used. GPRx registers are identical. > > Systems are running with linux 6.6 and master on an initrd. > > Disabling L2 cache in linux slows down things, but the relative results > are similar (no difference in read, memset 322.3 MB/s -> 728.5 MB/s). > > Building barebox with CONFIG_MMU disabled makes no difference. > > > Looking at another iMX6 system shows similar bad numbers for barebox. > E.g. an iMX6QP has a memset rate of 613.6 MB/s. But I do not have > u-boot available for comparision. > > > What could be the reason the u-boot is so much faster? Which memory > related settings are carried over from the bootloader to linux? What > could I test else? The most likely cause is that Barebox applies the workaround for ARM erratum 845369, which has a major impact on streaming writes and thus both memset and memcpy performance. The old U-Boot probably does not include this workaround. You may check this theory by removing the call to enable_arm_errata_845369_war in imx6_cpu_lowlevel_init. Regards, Lucas
Re: [PATCH 4/5] ARM: i.MX8MP: don't reparent GIC from BootROM default
Am Freitag, dem 19.04.2024 um 08:13 +0200 schrieb Ahmad Fatoum:
> On i.MX8MP, GIC can run at up to 400 MHz in nominal drive mode and up
> to 500 MHz in overdrive mode. We currently configure unconditionally
> to 100 MHz on i.MX8MP.
>
> The BootROM default is running it on 400 MHz, which works well for us on
> the i.MX8MP, so skip the GIC configuration on the i.MX8MP.
>
> Signed-off-by: Ahmad Fatoum
> ---
> arch/arm/mach-imx/imx8m.c | 16 +---
> 1 file changed, 9 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm/mach-imx/imx8m.c b/arch/arm/mach-imx/imx8m.c
> index 56330cef500c..0966f7fdf076 100644
> --- a/arch/arm/mach-imx/imx8m.c
> +++ b/arch/arm/mach-imx/imx8m.c
> @@ -100,13 +100,6 @@ static void __imx8m_early_clock_init(int cpu_type)
> INTPLL_DIV20_CLKE_MASK;
> writel(val, ana + IMX8MM_CCM_ANALOG_SYS_PLL2_GEN_CTRL);
>
> - /* config GIC to sys_pll2_100m */
> - imx8m_ccgr_clock_disable(IMX8M_CCM_CCGR_GIC);
> - imx8m_clock_set_target_val(IMX8M_GIC_CLK_ROOT,
> -IMX8M_CCM_TARGET_ROOTn_ENABLE |
> -IMX8M_CCM_TARGET_ROOTn_MUX(3));
> - imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_GIC);
> -
> if (cpu_type == IMX_CPU_IMX8MN || cpu_type == IMX_CPU_IMX8MP)
> pll3_freq = 6UL;
> else
> @@ -118,11 +111,20 @@ static void __imx8m_early_clock_init(int cpu_type)
>
> if (cpu_type == IMX_CPU_IMX8MP) {
> /* 8MP ROM already set NOC to 800Mhz, only need to configure
> NOC_IO clk to 600Mhz */
> + /* 8MP ROM already set GIC to 400Mhz, system_pll1_800m with div
> = 2 */
This comment change looks odd. Now it doesn't explain anymore what's
done here and why, but rather explains why the else path isn't executed
on the 8MP.
> imx8m_clock_set_target_val(IMX8M_NOC_IO_CLK_ROOT,
> IMX8M_CCM_TARGET_ROOTn_ENABLE |
> IMX8M_CCM_TARGET_ROOTn_MUX(2));
> + } else {
Maybe move this into a separate condition != IMX_CPU_IMX8MP and move
the comment above here? Leaving the comment about NOC_IO clocks
untouched?
> + /* config GIC to sys_pll2_100m */
> + imx8m_ccgr_clock_disable(IMX8M_CCM_CCGR_GIC);
> + imx8m_clock_set_target_val(IMX8M_GIC_CLK_ROOT,
> +IMX8M_CCM_TARGET_ROOTn_ENABLE |
> +IMX8M_CCM_TARGET_ROOTn_MUX(3));
> + imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_GIC);
> }
>
> +
> clrsetbits_le32(ccm + IMX8M_CCM_TARGET_ROOTn(IMX8M_ARM_A53_CLK_ROOT),
> IMX8M_CCM_TARGET_ROOTn_MUX(7),
> IMX8M_CCM_TARGET_ROOTn_MUX(2));
Re: [PATCH 5/5] ARM: dts: i.MX8MP: Add optional nominal drive mode DTSI
Am Freitag, dem 19.04.2024 um 08:13 +0200 schrieb Ahmad Fatoum:
> Unlike the i.MX8MM and i.MX8MN SoCs added earlier, the device tree for
> the i.MX8MP configures some clocks at frequencies that are only
> validated for overdrive mode, i.e. when VDD_SOC is 950 mV.
>
> Boards may want to run their SoC at the lower voltage of 850 mV though
> to reduce heat generation and power usage. For this to work, clock rates
> need to adhere to the limits of the nominal drive mode.
>
> Add an optional DTSI file which can be included by various boards to run
> in this mode.
>
> Signed-off-by: Ahmad Fatoum
> ---
> arch/arm/dts/imx8mp-nominal.dtsi | 51
> 1 file changed, 51 insertions(+)
> create mode 100644 arch/arm/dts/imx8mp-nominal.dtsi
>
> diff --git a/arch/arm/dts/imx8mp-nominal.dtsi
> b/arch/arm/dts/imx8mp-nominal.dtsi
> new file mode 100644
> index ..a9f46503f656
> --- /dev/null
> +++ b/arch/arm/dts/imx8mp-nominal.dtsi
> @@ -0,0 +1,51 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +
> +&clk {
> + assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
> + <&clk IMX8MP_CLK_A53_CORE>,
> + <&clk IMX8MP_SYS_PLL3>,
> + <&clk IMX8MP_CLK_NOC>,
> + <&clk IMX8MP_CLK_NOC_IO>,
> + <&clk IMX8MP_CLK_GIC>;
> + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
> + <&clk IMX8MP_ARM_PLL_OUT>,
> + <0>,
> + <&clk IMX8MP_SYS_PLL1_800M>,
> + <&clk IMX8MP_SYS_PLL3_OUT>,
> + <&clk IMX8MP_SYS_PLL1_800M>;
> + assigned-clock-rates = <0>, <0>,
> +<6>,
> +<8>,
> +<6>,
> +<4>;
> +};
> +
> +&pgc_hsiomix {
> + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
> + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
> + assigned-clock-rates = <4>;
> +};
> +
> +&pgc_gpumix {
> + assigned-clocks = <&clk IMX8MP_GPU_PLL>,
> + <&clk IMX8MP_CLK_GPU_AXI>,
> + <&clk IMX8MP_CLK_GPU_AHB>;
> + assigned-clock-parents = <0>,
> + <&clk IMX8MP_GPU_PLL_OUT>,
> + <&clk IMX8MP_GPU_PLL_OUT>;
> + assigned-clock-rates = <6>, <6>, <3>;
Use SYS_PLL3 as the parent clock, instead of GPU PLL.
> +};
> +
> +&media_blk_ctrl {
> + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
> + <&clk IMX8MP_CLK_MEDIA_APB>,
> + <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,
> + <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,
> + <&clk IMX8MP_VIDEO_PLL1>;
> + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
> + <&clk IMX8MP_SYS_PLL1_800M>,
> + <&clk IMX8MP_VIDEO_PLL1_OUT>,
> + <&clk IMX8MP_VIDEO_PLL1_OUT>;
> + assigned-clock-rates = <4>, <2>,
> +<0>, <0>, <103950>;
> +};
Re: [PATCH 2/2] mci: arasan: fix build for non-ZynqMP
Am Dienstag, dem 02.04.2024 um 10:33 +0200 schrieb Sascha Hauer: > On Tue, Mar 26, 2024 at 01:34:49PM +0100, Sascha Hauer wrote: > > On Tue, Mar 26, 2024 at 12:50:42PM +0100, Steffen Trumtrar wrote: > > > Registering sdclk only makes sense on the ZynqMP architecture. Guard > > > calling the function with a IS_ENABLED() > > > > > > Signed-off-by: Steffen Trumtrar > > > --- > > > drivers/mci/arasan-sdhci.c | 3 ++- > > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > > > diff --git a/drivers/mci/arasan-sdhci.c b/drivers/mci/arasan-sdhci.c > > > index f01396d7ee..b7dd98049f 100644 > > > --- a/drivers/mci/arasan-sdhci.c > > > +++ b/drivers/mci/arasan-sdhci.c > > > @@ -772,7 +772,8 @@ static int arasan_sdhci_probe(struct device *dev) > > > > > > mci->f_min = 5000 / 256; > > > > > > - arasan_sdhci_register_sdclk(&arasan_sdhci->clk_data, clk_xin, dev); > > > + if (IS_ENABLED(CONFIG_ARCH_ZYNQMP)) > > > + arasan_sdhci_register_sdclk(&arasan_sdhci->clk_data, clk_xin, > > > dev); > > > > CONFIG_ARCH_ZYNQMP being enabled doesn't necessarily mean the code > > actually runs on Zynqmp. Does this need a runtime check for other > > architectures? > > The arasan MMC driver is currently only used on ZynqMP, so it's OK for > now. > That's not true. The driver is also used on the Zynq7000. Regards, Lucas > In Linux the driver the ZynqMP specifics are only used with the > "xlnx,zynqmp-8.9a" > compatible whereas our driver binds to the "arasan,sdhci-8.9a" > compatible. This makes it more clear that this is really a ZynqMP > specific path that is taken here. > > Sascha >
[PATCH] usb: onboard-hub: bail out if peer hub is already probed
Many physical hub chips include multiple logical hubs to handle both
USB and 2 and 3. Both logical hubs will then match the onboard hub
driver, which means we'll end up with two driver instances trying to
control the reset GPIO that is only present once on the physical chip.
As this doesn't make sense, just bail out of the probe function when
the peer-hub is already probed and can be assumed to handle power,
clocks and reset resources of the chip.
Signed-off-by: Lucas Stach
---
drivers/usb/misc/onboard_usb_hub.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/usb/misc/onboard_usb_hub.c
b/drivers/usb/misc/onboard_usb_hub.c
index 6339a3e4ec18..9e94caaa8456 100644
--- a/drivers/usb/misc/onboard_usb_hub.c
+++ b/drivers/usb/misc/onboard_usb_hub.c
@@ -53,8 +53,17 @@ static int onboard_hub_power_on(struct onboard_hub *hub)
static int onboard_hub_probe(struct device *dev)
{
+ struct device_node *peer_node;
+ struct device *peer_dev;
struct onboard_hub *hub;
+ peer_node = of_parse_phandle(dev->of_node, "peer-hub", 0);
+ if (peer_node) {
+ peer_dev = of_find_device_by_node(peer_node);
+ if (peer_dev && peer_dev->priv)
+ return 0;
+ }
+
hub = xzalloc(sizeof(*hub));
hub->pdata = device_get_match_data(dev);
@@ -71,6 +80,7 @@ static int onboard_hub_probe(struct device *dev)
"failed to get reset GPIO\n");
hub->dev = dev;
+ dev->priv = hub;
return onboard_hub_power_on(hub);
}
--
2.44.0
Re: [PATCH v2 2/2] crypto: caam: caamrng: dma map descriptors
Am Freitag, dem 08.03.2024 um 08:35 +0100 schrieb Rouven Czerwinski:
> With DMA API debugging Barebox complains that the descriptors are never
> mapped before a sync. Add the map and unmap function calls.
>
> Signed-off-by: Rouven Czerwinski
> ---
> v2:
> - remove dma_map_sync_single_for_device() calls
> - remove dma_map_single for dma coherent memory
>
> drivers/crypto/caam/caamrng.c | 7 +++
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/crypto/caam/caamrng.c b/drivers/crypto/caam/caamrng.c
> index ea154913ca..03e75d0b7b 100644
> --- a/drivers/crypto/caam/caamrng.c
> +++ b/drivers/crypto/caam/caamrng.c
> @@ -91,6 +91,7 @@ static void rng_done(struct device *jrdev, u32 *desc, u32
> err, void *context)
>
> /* Buffer refilled, invalidate cache */
> dma_sync_single_for_cpu(jrdev, bd->addr, RN_BUF_SIZE, DMA_FROM_DEVICE);
> + dma_unmap_single(jrdev, (unsigned long)desc, desc_bytes(desc),
> DMA_TO_DEVICE);
> }
>
> static inline int submit_job(struct caam_rng_ctx *ctx, int to_current)
> @@ -102,8 +103,7 @@ static inline int submit_job(struct caam_rng_ctx *ctx,
> int to_current)
>
> dev_dbg(jrdev, "submitting job %d\n", !(to_current ^ ctx->current_buf));
>
> - dma_sync_single_for_device(jrdev, (unsigned long)desc, desc_bytes(desc),
> -DMA_TO_DEVICE);
> + dma_map_single(jrdev, (void *)desc, desc_bytes(desc), DMA_TO_DEVICE);
>
> err = caam_jr_enqueue(jrdev, desc, rng_done, ctx);
> if (!err)
> @@ -180,8 +180,7 @@ static inline int rng_create_sh_desc(struct caam_rng_ctx
> *ctx)
>
> ctx->sh_desc_dma = (dma_addr_t)desc;
>
> - dma_sync_single_for_device(ctx->jrdev, (unsigned long)desc,
> desc_bytes(desc),
> -DMA_TO_DEVICE);
> + dma_map_single(ctx->jrdev, desc, desc_bytes(desc), DMA_TO_DEVICE);
dma_map_single returns the DMA address that should be stored in
ctx->sh_desc_dma instead of the simple cast from virtual to DMA address
in the line above.
The other two dma_map/unmap calls in this patch look like a layering
violation. I would argue that those should move down into
caam_jr_enqueue and caam_jr_dequeue, to avoid the equally silly cast
from virt to DMA in those functions.
Regards,
Lucas
>
> print_hex_dump_debug("rng shdesc@: ", DUMP_PREFIX_OFFSET, 16, 4,
> desc, desc_bytes(desc), 1);
Re: [PATCH] dma: debug: detect repeated DMA sync
Am Donnerstag, dem 07.03.2024 um 13:27 +0100 schrieb Ahmad Fatoum:
> Hi,
>
> On 07.03.24 12:20, Rouven Czerwinski wrote:
> > Hi Ahmad,
> >
> > On Thu, 2024-03-07 at 12:14 +0100, Ahmad Fatoum wrote:
> > > dma_map_single will do any necessary cache maintenance to make a buffer
> > > available to a device. Calling debug_dma_sync_single_for_device on such
> > > a buffer is unnecessary, so flag when this happens.
> >
> >
> > AFAIUI It is only incorrect if the buffer is handed of to the device
> > and never touched by the CPU again. If you want to modify a buffer
> > after the device has modified it to let the device work on it again,
> > dma_sync_single_for_device is the correct function.
> >
> > In Essence:
> >
> > Device Access -> dma_sync_single_for_cpu -> CPU modification ->
> > dma_sync_single_for_device -> Device Access
> >
> > The buffer stays mapped to the deivce the whole time. Please correct me
> > if my understanding is wrong.
>
> Your understanding is correct and my patch shouldn't preclude using
> the DMA API that way. What it flags is doing a sync for CPU or a sync
> for device twice in a row without an intervening sync into the
> inverse direction.
>
Yep, the name of the property is a bit confusing, as it's not really
telling if an entry is dma mapped, but rather in which domain CPU/DEV
the entry currently resides. All memory regions start out in the CPU
domain and dma_map/dma_sync_for_device push them into the device
domain, while dma_unmap/dma_sync_for_cpu pull them back into the CPU
domain.
So maybe make this a enum of domains or at least rename to dev_owned or
something along those lines.
Regards,
Lucas
> Cheers,
> Ahmad
>
> >
> > > Signed-off-by: Ahmad Fatoum
> > > ---
> > > drivers/dma/debug.c | 22 --
> > > 1 file changed, 20 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/dma/debug.c b/drivers/dma/debug.c
> > > index b3bfbff9b2f5..b80e35ff5092 100644
> > > --- a/drivers/dma/debug.c
> > > +++ b/drivers/dma/debug.c
> > > @@ -12,6 +12,7 @@ struct dma_debug_entry {
> > > dma_addr_t dev_addr;
> > > size_t size;
> > > int direction;
> > > + bool dev_mapped;
> > > };
> > >
> > > static const char *dir2name[] = {
> > > @@ -121,6 +122,7 @@ void debug_dma_map(struct device *dev, void
> > > *addr,
> > > entry->dev_addr = dev_addr;
> > > entry->size = size;
> > > entry->direction = direction;
> > > + entry->dev_mapped = true;
> > >
> > > list_add(&entry->list, &dma_mappings);
> > >
> > > @@ -159,9 +161,17 @@ void debug_dma_sync_single_for_cpu(struct device
> > > *dev,
> > > struct dma_debug_entry *entry;
> > >
> > > entry = dma_debug_entry_find(dev, dma_handle, size);
> > > - if (!entry)
> > > + if (!entry) {
> > > dma_dev_warn(dev, "sync for CPU of never-mapped %s
> > > buffer 0x%llx+0x%zx!\n",
> > > dir2name[direction], (u64)dma_handle,
> > > size);
> > > + return;
> > > + }
> > > +
> > > + if (!entry->dev_mapped)
> > > + dma_dev_warn(dev, "unexpected sync for CPU of
> > > already CPU-mapped %s buffer 0x%llx+0x%zx!\n",
> > > + dir2name[direction], (u64)dma_handle,
> > > size);
> > > +
> > > + entry->dev_mapped = false;
> > > }
> > >
> > > void debug_dma_sync_single_for_device(struct device *dev,
> > > @@ -177,7 +187,15 @@ void debug_dma_sync_single_for_device(struct
> > > device *dev,
> > > * corruption
> > > */
> > > entry = dma_debug_entry_find(dev, dma_handle, size);
> > > - if (!entry)
> > > + if (!entry) {
> > > dma_dev_warn(dev, "Syncing for device of never-
> > > mapped %s buffer 0x%llx+0x%zx!\n",
> > > dir2name[direction], (u64)dma_handle,
> > > size);
> > > + return;
> > > + }
> > > +
> > > + if (entry->dev_mapped)
> > > + dma_dev_warn(dev, "unexpected sync for device of
> > > already device-mapped %s buffer 0x%llx+0x%zx!\n",
> > > + dir2name[direction], (u64)dma_handle,
> > > size);
> > > +
> > > + entry->dev_mapped = true;
> > > }
> >
> >
>
Re: [PATCH 2/2] crypto: caam: caamrng: map desc and buffer
Am Donnerstag, dem 07.03.2024 um 09:39 +0100 schrieb Rouven Czerwinski: > With DMA API debugging Barebox complains that some buffers are never > mapped before a sync. Add the map and unmap function calls. > > Signed-off-by: Rouven Czerwinski > --- > drivers/crypto/caam/caamrng.c | 4 > 1 file changed, 4 insertions(+) > > diff --git a/drivers/crypto/caam/caamrng.c b/drivers/crypto/caam/caamrng.c > index ea154913ca..1b5713f978 100644 > --- a/drivers/crypto/caam/caamrng.c > +++ b/drivers/crypto/caam/caamrng.c > @@ -91,6 +91,7 @@ static void rng_done(struct device *jrdev, u32 *desc, u32 > err, void *context) > > /* Buffer refilled, invalidate cache */ > dma_sync_single_for_cpu(jrdev, bd->addr, RN_BUF_SIZE, DMA_FROM_DEVICE); > + dma_unmap_single(jrdev, (unsigned long)desc, desc_bytes(desc), > DMA_TO_DEVICE); > } > > static inline int submit_job(struct caam_rng_ctx *ctx, int to_current) > @@ -102,6 +103,7 @@ static inline int submit_job(struct caam_rng_ctx *ctx, > int to_current) > > dev_dbg(jrdev, "submitting job %d\n", !(to_current ^ ctx->current_buf)); > > + dma_map_single(jrdev, (void *)desc, desc_bytes(desc), DMA_TO_DEVICE); > dma_sync_single_for_device(jrdev, (unsigned long)desc, desc_bytes(desc), > DMA_TO_DEVICE); > > @@ -180,6 +182,7 @@ static inline int rng_create_sh_desc(struct caam_rng_ctx > *ctx) > > ctx->sh_desc_dma = (dma_addr_t)desc; > > + dma_map_single(ctx->jrdev, desc, desc_bytes(desc), DMA_TO_DEVICE); > dma_sync_single_for_device(ctx->jrdev, (unsigned long)desc, > desc_bytes(desc), > DMA_TO_DEVICE); Same comment on those syncs as the patch before. > > @@ -210,6 +213,7 @@ static int caam_init_buf(struct caam_rng_ctx *ctx, int > buf_id) > int err; > > bd->buf = dma_alloc_coherent(RN_BUF_SIZE, &bd->addr); > + dma_map_single(ctx->jrdev, (void *)bd->addr, RN_BUF_SIZE, > DMA_FROM_DEVICE); This looks wrong. A device coherent buffer doesn't ever need to be mapped via the streaming DMA API. The DMA debug is probably confused by the bogus dma_sync_single_for_cpu() in rng_done(), which shouldn't be there, as the buffer is allocated from coherent memory and thus doesn't need to be synced. Regards, Lucas > > err = rng_create_job_desc(ctx, buf_id); > if (err)
Re: [PATCH 1/2] crypto: caam: map DMA buffers before sync
Am Donnerstag, dem 07.03.2024 um 09:39 +0100 schrieb Rouven Czerwinski: > With dma api debugging enabled, Barebox complains correctly that the > result and desc buffer are never mapped correctly. Add the correct map > and unmap sequence. > > Signed-off-by: Rouven Czerwinski > --- > drivers/crypto/caam/rng_self_test.c | 4 > 1 file changed, 4 insertions(+) > > diff --git a/drivers/crypto/caam/rng_self_test.c > b/drivers/crypto/caam/rng_self_test.c > index b6fcc3bc09..f5ab974a98 100644 > --- a/drivers/crypto/caam/rng_self_test.c > +++ b/drivers/crypto/caam/rng_self_test.c > @@ -186,6 +186,8 @@ int caam_rng_self_test(struct device *dev, const u8 > caam_era, const u8 rngvid, > > construct_rng_self_test_jobdesc(desc, rng_st_dsc, result, desc_size); > > + dma_map_single(dev, desc, desc_size * sizeof(*desc), DMA_TO_DEVICE); > + dma_map_single(dev, result, result_size * sizeof(*result), > DMA_FROM_DEVICE); > dma_sync_single_for_device(dev, (unsigned long)desc, > desc_size * sizeof(*desc), DMA_TO_DEVICE); > dma_sync_single_for_device(dev, (unsigned long)result, While harmless, those syncs are not needed anymore after the dma_map is added, as they do the same cache maintenance operations as the map right before. Regards, Lucas > @@ -218,6 +220,8 @@ int caam_rng_self_test(struct device *dev, const u8 > caam_era, const u8 rngvid, > ret = 0; > > err: > + dma_unmap_single(dev, (dma_addr_t)desc, desc_size * sizeof(*desc), > DMA_TO_DEVICE); > + dma_unmap_single(dev, (dma_addr_t)result, result_size * > sizeof(*result), DMA_FROM_DEVICE); > dma_free(desc); > dma_free(result); > return ret;
Re: [PATCH 1/2] net: macb: fix dma_alloc for rx_buffer
Am Dienstag, dem 28.11.2023 um 17:29 +0100 schrieb Steffen Trumtrar:
> rx_buffer gets dma_alloc'ed but is never dma_map'ed and therefor not
> flushed before it is initially used.
>
> Map the rx_buffer when the macb is initialized and unmap it on ether_halt.
>
> While at it, cleanup the dma_alloc_coherent rx_ring/tx_ring, too.
>
> Signed-off-by: Steffen Trumtrar
> ---
> drivers/net/macb.c | 37 -
> 1 file changed, 28 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/net/macb.c b/drivers/net/macb.c
> index 260c1e806a..92f78f7253 100644
> --- a/drivers/net/macb.c
> +++ b/drivers/net/macb.c
> @@ -63,10 +63,13 @@ struct macb_device {
> unsigned inttx_head;
>
> void*rx_buffer;
> + dma_addr_t rx_buffer_phys;
> void*tx_buffer;
> void*rx_packet_buf;
> struct macb_dma_desc*rx_ring;
> + dma_addr_t rx_ring_phys;
> struct macb_dma_desc*tx_ring;
> + dma_addr_t tx_ring_phys;
> struct macb_dma_desc*gem_q1_descs;
>
> int rx_buffer_size;
> @@ -181,7 +184,7 @@ static int gem_recv(struct eth_device *edev)
> barrier();
> status = macb->rx_ring[macb->rx_tail].ctrl;
> length = MACB_BFEXT(RX_FRMLEN, status);
> - buffer = macb->rx_buffer + macb->rx_buffer_size * macb->rx_tail;
> + buffer = (void *)macb->rx_buffer_phys + macb->rx_buffer_size *
> macb->rx_tail;
> dma_sync_single_for_cpu(macb->dev, (unsigned long)buffer,
> length,
> DMA_FROM_DEVICE);
> net_receive(edev, buffer, length);
> @@ -221,7 +224,7 @@ static int macb_recv(struct eth_device *edev)
> }
>
> if (status & MACB_BIT(RX_EOF)) {
> - buffer = macb->rx_buffer + macb->rx_buffer_size *
> macb->rx_tail;
> + buffer = (void *)macb->rx_buffer_phys +
> macb->rx_buffer_size * macb->rx_tail;
> length = MACB_BFEXT(RX_FRMLEN, status);
> if (wrapped) {
> unsigned int headlen, taillen;
> @@ -232,12 +235,12 @@ static int macb_recv(struct eth_device *edev)
> dma_sync_single_for_cpu(macb->dev, (unsigned
> long)buffer,
> headlen,
> DMA_FROM_DEVICE);
> memcpy(macb->rx_packet_buf, buffer, headlen);
> - dma_sync_single_for_cpu(macb->dev, (unsigned
> long)macb->rx_buffer,
> + dma_sync_single_for_cpu(macb->dev, (unsigned
> long)macb->rx_buffer_phys,
You can drop all those (unsigned long) casts in calls to
dma_sync_single, now that you are passing a argument of the proper
dma_addr_t type.
> taillen,
> DMA_FROM_DEVICE);
> memcpy(macb->rx_packet_buf + headlen,
> macb->rx_buffer, taillen);
> dma_sync_single_for_device(macb->dev, (unsigned
> long)buffer,
> headlen,
> DMA_FROM_DEVICE);
> - dma_sync_single_for_device(macb->dev, (unsigned
> long)macb->rx_buffer,
> + dma_sync_single_for_device(macb->dev, (unsigned
> long)macb->rx_buffer_phys,
> taillen,
> DMA_FROM_DEVICE);
> net_receive(edev, macb->rx_packet_buf, length);
> } else {
> @@ -377,7 +380,7 @@ static int gmac_init_dummy_tx_queues(struct macb_device
> *macb)
> return 0;
> }
>
> -static void macb_init(struct macb_device *macb)
> +static int macb_init(struct macb_device *macb)
> {
> unsigned long paddr, val = 0;
> int i;
> @@ -386,6 +389,11 @@ static void macb_init(struct macb_device *macb)
>* macb_halt should have been called at some point before now,
>* so we'll assume the controller is idle.
>*/
> + macb->rx_buffer_phys = dma_map_single(macb->dev, macb->rx_buffer,
> + macb->rx_buffer_size *
> macb->rx_ring_size,
> + DMA_TO_DEVICE);
The RX buffer is used to hold data written by the device, so it must be
mapped with DMA_FROM_DEVICE.
Regards,
Lucas
> + if (dma_mapping_error(macb->dev, macb->rx_buffer_phys))
> + return -EFAULT;
>
> /* initialize DMA descriptors */
> paddr = (ulong)macb->rx_buffer;
> @@ -442,6 +450,7 @@ static void macb_init(struct macb_device *macb)
>
> macb_or_gem_writel(macb, USRIO, val);
>
> + return 0;
> }
>
> static void macb_halt(struct eth_device *edev)
> @@ -460,6 +469,13 @@ static void macb_halt(struct eth_de
Re: RK3568 some question
Am Freitag, dem 13.10.2023 um 11:12 +0300 schrieb Alexander Shiyan: > Hello. > [...] > I'm not too familiar with the PCI subsystem, but after briefly looking > at the code, > I saw in the setup_device() function the line: > pci_write_config_dword(dev, pci_base_address_0, 0xfffe); > On Linux and u-boot this value is ~0. > The question is, are we doing the right thing here? We can change this to be consistent with Linux, but in practice it probably won't matter, as this bit signifies if the BAR is a memory or IO resource and is hardcoded in any real device and not dependent on writing ones to the BAR register to return the correct value. Regards, Lucas
Re: [PATCH 2/2] ARM: i.MX8M: esdctl: split memory banks for devices with >4G
Am Donnerstag, dem 31.08.2023 um 15:05 +0200 schrieb Marco Felsch:
> At the moment the whole available memory is added to one single memory
> bank "ram0". This can cause barebox chainload issues on devices with a
> huge amount of memory like the i.MX8MP-EVK which has 6G of RAM if the
> barebox pbl binary is to large.
>
> The reason for this issues is that memory_bank_first_find_space()
> returns the memory area with the largest amount of free space on the
> first memory bank. So in case of Debix SOM-A 8G and i.MX8MP-EVK 6G this
> is the area crossing the 4G boundary. This cause the barebox pbl code to
> trigger a MMU exception once the early MMU gets enabled which is
> configured for sizes <=4G.
>
> Split the memory space into two memory banks: "ram0" and "ram1" to fix
> this issue.
>
> Signed-off-by: Marco Felsch
> ---
> arch/arm/mach-imx/esdctl.c | 18 ++
> 1 file changed, 14 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c
> index 54c62c47338e..de23b6433355 100644
> --- a/arch/arm/mach-imx/esdctl.c
> +++ b/arch/arm/mach-imx/esdctl.c
> @@ -510,16 +510,26 @@ static resource_size_t imx8m_ddrc_sdram_size(void
> __iomem *ddrc, unsigned buswid
> reduced_adress_space, mstr);
> }
>
> +static int _imx8m_ddrc_add_mem(void *mmdcbase, struct imx_esdctl_data *data,
> +unsigned int buswidth)
> +{
> + resource_size_t size = imx8m_ddrc_sdram_size(mmdcbase, buswidth);
> + resource_size_t size0, size1;
> +
> + size0 = min_t(resource_size_t, SZ_4G - MX8M_DDR_CSD1_BASE_ADDR, size);
> + size1 = size - size0;
> +
> + return add_mem(data->base0, size0, SZ_4G, size1, true);
It's quite bogus to call add_mem from the imx8 code here. add_mem
explicitly deals with different chip selects on the same memory
controller and it's whole purpose is to do the opposite of what you are
trying to achieve here: merging multiple regions into a single memory
bank.
Please just call arm_add_mem_device two times from this little helper
function you are adding here.
However, given that we ignore memory beyond the 4G mark in other parts
of barebox as well, wouldn't it make sense to just clamp the memory to
32bit addresses in memory_bank_first_find_space?
Regards,
Lucas
> +}
> +
> static int imx8m_ddrc_add_mem(void *mmdcbase, struct imx_esdctl_data *data)
> {
> - return arm_add_mem_device("ram0", data->base0,
> -imx8m_ddrc_sdram_size(mmdcbase, 32));
> + return _imx8m_ddrc_add_mem(mmdcbase, data, 32);
> }
>
> static int imx8mn_ddrc_add_mem(void *mmdcbase, struct imx_esdctl_data *data)
> {
> - return arm_add_mem_device("ram0", data->base0,
> -imx8m_ddrc_sdram_size(mmdcbase, 16));
> + return _imx8m_ddrc_add_mem(mmdcbase, data, 16);
> }
>
> static resource_size_t imx7d_ddrc_sdram_size(void __iomem *ddrc)
Re: [PATCH v2] ARM: add Skov i'MX8MP based board support
Am Montag, dem 14.08.2023 um 11:45 +0200 schrieb Oleksij Rempel: > Add basic support for the Skov i'MX8MP based system. i.MX8MP > This is initial support and will be extended later at least with board version > detection. > > The compatible used in the board file is for barebox specific generic > devicetree which is expected to work with all Skov i'MX8M based boards. i.MX8MP > > Signed-off-by: Oleksij Rempel > Reviewed-by: Ahmad Fatoum > --- > changes v2: > - remove board dependency on DSA and KSZ9477 drivers > - add notice about generic board support > > arch/arm/boards/Makefile |1 + > arch/arm/boards/skov-imx8m/Makefile |4 + This board is designed exclusively around the i.MX8MP, with no plan for using any other chip from the i.MX8M family, so I guess the directory name could reflect that. Regards, Lucas
Re: LS1021A performance
Hi Renaud, Am Donnerstag, dem 30.03.2023 um 13:31 + schrieb Renaud Barbier: > > > > Can you compare SHA256 instead and see if the difference is still as stark? > > Make sure that CONFIG_DIGEST_SHA256_ARM is enabled. > The SHA256 is enabled. SHA256 on a 1 MB file: > Barebox: 843ms > Linux: > [root@openware]# time sha256sum /tmp/mtd0 > eef67a3327e3eaa50ee7b1dad87901465f00d76a6308e360a2fedab82c79f493 /tmp/mtd0 > > real0m0.059s > user0m0.056s > sys 0m0.001s > > On another note, the boot loader using the LS1021A is much slower than using > the PPC P1014. > I compare those two as we used the LS1021A as a replacement for P1014 on a > board (same peripherals, same boot sequence) > The P1014 reach the prompt in 200ms while the LS1021 takes 700ms. > > Also, I noticed that the pageflags is different for the DDR memory on Barebox > and Linux as seen by the Lauterbach: > Barebox: write-back/no allocate > Linux : Inner:write-back/allocate outer: write-back/allocate > Could that mean the L2 cache Is not used? > > > > Do barebox and Linux run at the same CPU frequency? > According to the Lauterbach, clock ratio have not changed in the clocking > registers > > As the LS1021A is based on a Cortex A7 your board lowlevel init needs to call cortex_a7_lowlevel_init() for the caches to work properly. It's probably a good idea to add a ls1021 lowlevel init function which calls both of those functions together, like imx6ul_cpu_lowlevel_init(). Regards, Lucas > > Cheers, > > Ahmad > > > > > > > > Cheers, > > > Renaud > > > > > > > > > > > > > > > > -- > > Pengutronix e.K. | | > > Steuerwalder Str. 21 | > > https://urldefense.com/v3/__http://www.pengutronix.de/__;!!HKOSU0g!D > > 4uFepgqngTTHamr_7tlQeQoRJqSLL8npxTFBWFF- > > kjpZuHgzi1quS6EE1ecjCKr_O_FJGPfkAnWXQyfONKJxqgrtQQ$ | > > 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| > > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | >
Re: imx8 - gpc: Support IMX8 Lite
Hi Hans Christian,
Am Mittwoch, dem 15.03.2023 um 08:05 +0100 schrieb Hans Christian Lonstad:
> IMX8 Lite lacks some functionality and hence the corresponding
> power domains (8, 11, 12, 13).
> This results in Barebox error messages and unfortunately a failed
> Linux kernel boot.
> Add a "Lite" specific table selected using device tree compatible
> clause.
>
> Note that this should probably be related to the feature controller.
Yes, the lite versions of the SoC are usually just fused down versions
of the SoC and the fuses should tell you which features are actually
available. Please try to use the feature controller to disable the non
existent features/DT nodes. Adding a specific compatible and all this
code not look like the right way to go to me.
Regards,
Lucas
>
> Signed-off-by: Hans Christian Lonstad
>
> diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
> index b662363f79..40998c42c5 100644
> --- a/drivers/soc/imx/gpcv2.c
> +++ b/drivers/soc/imx/gpcv2.c
> @@ -1053,6 +1053,192 @@ static const struct imx_pgc_domain
> imx8mp_pgc_domains[] = {
> },
> };
>
> +static const struct imx_pgc_domain imx8mpl_pgc_domains[] = {
> + [IMX8MP_POWER_DOMAIN_MIPI_PHY1] = {
> + .genpd = {
> + .name = "mipi-phy1",
> + },
> + .bits = {
> + .pxx = IMX8MP_MIPI_PHY1_SW_Pxx_REQ,
> + .map = IMX8MP_MIPI_PHY1_A53_DOMAIN,
> + },
> + .pgc = BIT(IMX8MP_PGC_MIPI1),
> + },
> +
> + [IMX8MP_POWER_DOMAIN_PCIE_PHY] = {
> + .genpd = {
> + .name = "pcie-phy1",
> + },
> + .bits = {
> + .pxx = IMX8MP_PCIE_PHY_SW_Pxx_REQ,
> + .map = IMX8MP_PCIE_PHY_A53_DOMAIN,
> + },
> + .pgc = BIT(IMX8MP_PGC_PCIE),
> + },
> +
> + [IMX8MP_POWER_DOMAIN_USB1_PHY] = {
> + .genpd = {
> + .name = "usb-otg1",
> + },
> + .bits = {
> + .pxx = IMX8MP_USB1_PHY_Pxx_REQ,
> + .map = IMX8MP_USB1_PHY_A53_DOMAIN,
> + },
> + .pgc = BIT(IMX8MP_PGC_USB1),
> + },
> +
> + [IMX8MP_POWER_DOMAIN_USB2_PHY] = {
> + .genpd = {
> + .name = "usb-otg2",
> + },
> + .bits = {
> + .pxx = IMX8MP_USB2_PHY_Pxx_REQ,
> + .map = IMX8MP_USB2_PHY_A53_DOMAIN,
> + },
> + .pgc = BIT(IMX8MP_PGC_USB2),
> + },
> +
> + [IMX8MP_POWER_DOMAIN_MLMIX] = {
> + .genpd = {
> + .name = "mlmix",
> + },
> + .bits = {
> + .pxx = IMX8MP_MLMIX_Pxx_REQ,
> + .map = IMX8MP_MLMIX_A53_DOMAIN,
> + .hskreq = IMX8MP_MLMIX_PWRDNREQN,
> + .hskack = IMX8MP_MLMIX_PWRDNACKN,
> + },
> + .pgc = BIT(IMX8MP_PGC_MLMIX),
> + .keep_clocks = true,
> + },
> +
> + [IMX8MP_POWER_DOMAIN_AUDIOMIX] = {
> + .genpd = {
> + .name = "audiomix",
> + },
> + .bits = {
> + .pxx = IMX8MP_AUDIOMIX_Pxx_REQ,
> + .map = IMX8MP_AUDIOMIX_A53_DOMAIN,
> + .hskreq = IMX8MP_AUDIOMIX_PWRDNREQN,
> + .hskack = IMX8MP_AUDIOMIX_PWRDNACKN,
> + },
> + .pgc = BIT(IMX8MP_PGC_AUDIOMIX),
> + .keep_clocks = true,
> + },
> +
> + [IMX8MP_POWER_DOMAIN_GPU2D] = {
> + .genpd = {
> + .name = "gpu2d",
> + },
> + .bits = {
> + .pxx = IMX8MP_GPU_2D_Pxx_REQ,
> + .map = IMX8MP_GPU2D_A53_DOMAIN,
> + },
> + .pgc = BIT(IMX8MP_PGC_GPU2D),
> + },
> +
> + [IMX8MP_POWER_DOMAIN_GPUMIX] = {
> + .genpd = {
> + .name = "gpumix",
> + },
> + .bits = {
> + .pxx = IMX8MP_GPU_SHARE_LOGIC_Pxx_REQ,
> + .map = IMX8MP_GPUMIX_A53_DOMAIN,
> + .hskreq = IMX8MP_GPUMIX_PWRDNREQN,
> + .hskack = IMX8MP_GPUMIX_PWRDNACKN,
> + },
> + .pgc = BIT(IMX8MP_PGC_GPUMIX),
> + .keep_clocks = true,
> + },
> +
> + [IMX8MP_POWER_DOMAIN_GPU3D] = {
> + .genpd = {
> + .name = "gpu3d",
> + },
> + .bits = {
> + .pxx = IMX8MP_GPU_3D_Pxx_REQ,
> + .map = IMX8MP_GPU3D_A53_DOMAIN,
> + },
> + .pgc = BIT(IMX8MP_PGC_GPU3D),
> + },
> +
> + [IMX8MP_POWER_DOMAIN_MEDIAMIX] = {
> + .genpd = {
> + .name = "mediamix",
> + },
> + .bits = {
> + .pxx = IMX8MP_MED
Re: [PATCH] ARM: dts: i.MX8MP: remove memory node
Am Sonntag, dem 12.03.2023 um 17:29 +0100 schrieb Marco Felsch:
> since commit f083fffe52 ("ARM: dts: i.MX8MP: add DDRC compatibles") we
> make use of the esdctl driver. This cause the below error since barebox
> try to add the memory twice.
>
> > imx-esdctl 3d40.memory-control...@3d40.of: probe failed: Device or
> > resource busy
> > initcall imx_esdctl_driver_init+0x0/0x2c failed: No such device
>
I wonder why I didn't hit this. Probably some probe order thing.
> Remove the memory node to fix this.
>
> This behaviour was seen on a i.mx8mp-evk but the
> imx8mp-tqma8mpql-mba8mpxl also has a memory node and includes the
> barebox.dtsi.
>
> Fixes: f083fffe52 ("ARM: dts: i.MX8MP: add DDRC compatibles")
> Signed-off-by: Marco Felsch
> ---
> arch/arm/dts/imx8mp-evk.dts| 2 ++
> arch/arm/dts/imx8mp-tqma8mpql-mba8mpxl.dts | 2 ++
> 2 files changed, 4 insertions(+)
>
> diff --git a/arch/arm/dts/imx8mp-evk.dts b/arch/arm/dts/imx8mp-evk.dts
> index 0acc3731d5..c7e1f35d2d 100644
> --- a/arch/arm/dts/imx8mp-evk.dts
> +++ b/arch/arm/dts/imx8mp-evk.dts
> @@ -30,6 +30,8 @@
> };
> };
>
> +/delete-node/ &{/memory@4000};
> +
Why not add this to arch/arm/dts/imx8mp.dtsi?
Regards,
Lucas
> ðphy1 {
> reset-assert-us = <15000>;
> reset-deassert-us = <10>;
> diff --git a/arch/arm/dts/imx8mp-tqma8mpql-mba8mpxl.dts
> b/arch/arm/dts/imx8mp-tqma8mpql-mba8mpxl.dts
> index 6e81f58e27..bf23e40489 100644
> --- a/arch/arm/dts/imx8mp-tqma8mpql-mba8mpxl.dts
> +++ b/arch/arm/dts/imx8mp-tqma8mpql-mba8mpxl.dts
> @@ -24,6 +24,8 @@
> };
> };
>
> +/delete-node/ &{/memory@4000};
> +
> &usdhc2 {
> #address-cells = <1>;
> #size-cells = <1>;
[PATCH v2 2/2] ARM: i.MX8MP: add initial Polyhex DEBIX Model A support
From: Ahmad Fatoum
The Polyhex DEBIX Model A is an i.MX8MP based Rpi form factor board.
This commit imports the v6 of the Linux device tree[1], and the timings
from the vendor U-Boot[2] and combines it with existing barebox i.MX8MP
support.
[1]:
https://lore.kernel.org/all/20221213152024.2638377-4-dan.sca...@ideasonboard.com/
[2]:
https://github.com/debix-tech/uboot/blob/lf_v2021.04/board/freescale/imx8mp_evk/lpddr4_timing.c
Signed-off-by: Ahmad Fatoum
[lst: cleaned up WIP patch]
Signed-off-by: Lucas Stach
---
arch/arm/boards/Makefile |1 +
arch/arm/boards/polyhex-debix/Makefile|4 +
arch/arm/boards/polyhex-debix/board.c | 48 +
.../flash-header-polyhex-debix.imxcfg |7 +
arch/arm/boards/polyhex-debix/lowlevel.c | 138 ++
arch/arm/boards/polyhex-debix/lpddr4-timing.c | 1849 +
arch/arm/dts/Makefile |1 +
.../arm/dts/imx8mp-debix-model-a-upstream.dts | 506 +
arch/arm/dts/imx8mp-debix-model-a.dts | 68 +
arch/arm/mach-imx/Kconfig | 10 +
images/Makefile.imx |5 +
11 files changed, 2637 insertions(+)
create mode 100644 arch/arm/boards/polyhex-debix/Makefile
create mode 100644 arch/arm/boards/polyhex-debix/board.c
create mode 100644
arch/arm/boards/polyhex-debix/flash-header-polyhex-debix.imxcfg
create mode 100644 arch/arm/boards/polyhex-debix/lowlevel.c
create mode 100644 arch/arm/boards/polyhex-debix/lpddr4-timing.c
create mode 100644 arch/arm/dts/imx8mp-debix-model-a-upstream.dts
create mode 100644 arch/arm/dts/imx8mp-debix-model-a.dts
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index 5006ebb5..f92094d15b1e 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -113,6 +113,7 @@ obj-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) +=
plathome-openblocks-a6/
obj-$(CONFIG_MACH_PM9261) += pm9261/
obj-$(CONFIG_MACH_PM9263) += pm9263/
obj-$(CONFIG_MACH_PM9G45) += pm9g45/
+obj-$(CONFIG_MACH_POLYHEX_DEBIX) += polyhex-debix/
obj-$(CONFIG_MACH_PROTONIC_IMX6) += protonic-imx6/
obj-$(CONFIG_MACH_PROTONIC_IMX8M) += protonic-imx8m/
obj-$(CONFIG_MACH_PROTONIC_STM32MP1) += protonic-stm32mp1/
diff --git a/arch/arm/boards/polyhex-debix/Makefile
b/arch/arm/boards/polyhex-debix/Makefile
new file mode 100644
index ..35d8640087b1
--- /dev/null
+++ b/arch/arm/boards/polyhex-debix/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+obj-y += board.o
+lwl-y += lowlevel.o lpddr4-timing.o
diff --git a/arch/arm/boards/polyhex-debix/board.c
b/arch/arm/boards/polyhex-debix/board.c
new file mode 100644
index ..8a8f286ea5e2
--- /dev/null
+++ b/arch/arm/boards/polyhex-debix/board.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+static int polyhex_debix_probe(struct device *dev)
+{
+ int emmc_bbu_flag = 0;
+ int sd_bbu_flag = 0;
+ u32 val;
+
+ if (bootsource_get() == BOOTSOURCE_MMC && bootsource_get_instance() ==
1) {
+ of_device_enable_path("/chosen/environment-sd");
+ sd_bbu_flag = BBU_HANDLER_FLAG_DEFAULT;
+ } else {
+ of_device_enable_path("/chosen/environment-emmc");
+ emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT;
+ }
+
+ imx8m_bbu_internal_mmc_register_handler("SD", "/dev/mmc1.barebox",
sd_bbu_flag);
+ imx8m_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc2",
emmc_bbu_flag);
+
+ /* Enable RGMII TX clk output */
+ val = readl(MX8MP_IOMUXC_GPR_BASE_ADDR + MX8MP_IOMUXC_GPR1);
+ val |= MX8MP_IOMUXC_GPR1_ENET1_RGMII_EN;
+ writel(val, MX8MP_IOMUXC_GPR_BASE_ADDR + MX8MP_IOMUXC_GPR1);
+
+ return 0;
+}
+
+static const struct of_device_id polyhex_debix_of_match[] = {
+ { .compatible = "polyhex,imx8mp-debix" },
+ { /* Sentinel */ }
+};
+BAREBOX_DEEP_PROBE_ENABLE(polyhex_debix_of_match);
+
+static struct driver polyhex_debix_board_driver = {
+ .name = "board-imx8mp-debix",
+ .probe = polyhex_debix_probe,
+ .of_compatible = polyhex_debix_of_match,
+};
+coredevice_platform_driver(polyhex_debix_board_driver);
diff --git a/arch/arm/boards/polyhex-debix/flash-header-polyhex-debix.imxcfg
b/arch/arm/boards/polyhex-debix/flash-header-polyhex-debix.imxcfg
new file mode 100644
index ..663bd102e9a2
--- /dev/null
+++ b/arch/arm/boards/polyhex-debix/flash-header-polyhex-debix.imxcfg
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+soc imx8mp
+
+loadaddr 0x92
+max_load_size 0x3f000
+ivtofs 0x0
diff --git a/arch/arm/boards/polyhex-debix/lowlevel.c
b/arch/arm/boards/polyhex-debix/lowlevel.c
n
[PATCH v2 1/2] ddr: imx8m: add support for 3720 MHz DDR rate
From: Ahmad Fatoum
Signed-off-by: Ahmad Fatoum
Signed-off-by: Lucas Stach
---
drivers/ddr/imx8m/ddrphy_utils.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/ddr/imx8m/ddrphy_utils.c b/drivers/ddr/imx8m/ddrphy_utils.c
index 98e6ae648aed..7f863a1736c6 100644
--- a/drivers/ddr/imx8m/ddrphy_utils.c
+++ b/drivers/ddr/imx8m/ddrphy_utils.c
@@ -17,6 +17,7 @@
* clock / 2, which is therefor transfer rate / 4. */
enum ddr_rate {
DDR_4000,
+ DDR_3720,
DDR_3200,
DDR_3000,
DDR_2600, /* Unused */
@@ -52,6 +53,7 @@ static const struct imx8mm_fracpll_config {
bool valid;
} imx8mm_fracpll_table[DDR_NUM_RATES] = {
[DDR_4000] = { .valid = true, .r1 = MDIV(250) | PDIV(3) | SDIV(1), .r2
= 0 },
+ [DDR_3720] = { .valid = true, .r1 = MDIV(310) | PDIV(2) | SDIV(2), .r2
= 0 },
[DDR_3200] = { .valid = true, .r1 = MDIV(300) | PDIV(9) | SDIV(0), .r2
= 0 },
[DDR_3000] = { .valid = true, .r1 = MDIV(250) | PDIV(8) | SDIV(0), .r2
= 0 },
[DDR_2600] = { .valid = true, .r1 = MDIV(325) | PDIV(3) | SDIV(2), .r2
= 0 },
@@ -335,6 +337,7 @@ void ddrphy_init_set_dfi_clk(unsigned int drate_mhz, enum
ddrc_type type)
switch (drate_mhz) {
case 4000: drate = DDR_4000; break;
+ case 3720: drate = DDR_3720; break;
case 3200: drate = DDR_3200; break;
case 3000: drate = DDR_3000; break;
case 2400: drate = DDR_2400; break;
--
2.39.1
[PATCH v3 1/3] ARM: i.MX8M: esdctl: use common compatible to detect i.MX8MQ/MM/MP DDRC
All i.MX8M* DDRC nodes are compatible to "fsl,imx8m-ddrc". As the memory
size detection works the same on most of them, with the only exception
being the i.MX8MN, which only has a 16bit data bus, there is no need to
match the more specific compatibles for i.MX8MQ/MM/MP.
Signed-off-by: Lucas Stach
Reviewed-by: Marco Felsch
---
arch/arm/mach-imx/esdctl.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c
index a704250297bb..29e992933421 100644
--- a/arch/arm/mach-imx/esdctl.c
+++ b/arch/arm/mach-imx/esdctl.c
@@ -652,7 +652,7 @@ static __maybe_unused struct imx_esdctl_data vf610_data = {
.add_mem = vf610_ddrmc_add_mem,
};
-static __maybe_unused struct imx_esdctl_data imx8mq_data = {
+static __maybe_unused struct imx_esdctl_data imx8m_data = {
.base0 = MX8M_DDR_CSD1_BASE_ADDR,
.add_mem = imx8m_ddrc_add_mem,
};
@@ -732,14 +732,11 @@ static __maybe_unused struct of_device_id
imx_esdctl_dt_ids[] = {
.compatible = "fsl,vf610-ddrmc",
.data = &vf610_data
}, {
- .compatible = "fsl,imx8mm-ddrc",
- .data = &imx8mq_data
+ .compatible = "fsl,imx8m-ddrc",
+ .data = &imx8m_data
}, {
.compatible = "fsl,imx8mn-ddrc",
.data = &imx8mn_data
- }, {
- .compatible = "fsl,imx8mq-ddrc",
- .data = &imx8mq_data
}, {
.compatible = "fsl,imx7d-ddrc",
.data = &imx7d_data
--
2.39.1
[PATCH v3 3/3] ARM: dts: i.MX8MP: remove DSP and DSP reserved memory nodes
The reserved memory for the DSP collides with the Barebox malloc area
in some DRAM configuration. This causes the malloc region reservation
to fail, with all kinds of resulting fallout.
Remove the DSP and DSP reserved memory nodes from the Barebox DT to
work around this issue. This means the DSP won't be usable if the
system is booted with the Barebox builtin DT, but that seems like the
best option so far.
Signed-off-by: Lucas Stach
---
arch/arm/dts/imx8mp.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi
index 778e84318ce7..6962d11e853a 100644
--- a/arch/arm/dts/imx8mp.dtsi
+++ b/arch/arm/dts/imx8mp.dtsi
@@ -10,6 +10,13 @@
};
};
+/*
+ * The DSP reserved memory will collide with the Barebox malloc area for some
+ * DRAM sizes, even though the DSP itself is disabled in most configurations.
+ */
+/delete-node/ &dsp;
+/delete-node/ &dsp_reserved;
+
&edacmc {
compatible = "fsl,imx8mp-ddrc", "fsl,imx8m-ddrc", "snps,ddrc-3.80a";
};
--
2.39.1
[PATCH v3 2/3] ARM: dts: i.MX8MP: add DDRC compatibles
The upstream DT currently only provides the Synopsis core compatible
for the DDRC node. Extend this with more machine specific compatibles
to allow our memory size detection to work.
Signed-off-by: Lucas Stach
Reviewed-by: Marco Felsch
---
arch/arm/dts/imx8mp.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi
index 5da79f13d339..778e84318ce7 100644
--- a/arch/arm/dts/imx8mp.dtsi
+++ b/arch/arm/dts/imx8mp.dtsi
@@ -10,6 +10,10 @@
};
};
+&edacmc {
+ compatible = "fsl,imx8mp-ddrc", "fsl,imx8m-ddrc", "snps,ddrc-3.80a";
+};
+
feat: &ocotp {
#feature-cells = <1>;
barebox,feature-controller;
--
2.39.1
[PATCH 2/2] ARM: i.MX8MP: add initial Polyhex DEBIX Model A support
From: Ahmad Fatoum
The Polyhex DEBIX Model A is an i.MX8MP based Rpi form factor board.
This commit imports the v4 of the Linux device tree[1], and the timings
from the vendor U-Boot[2] and combines it with existing barebox i.MX8MP
support.
[1]:
https://lore.kernel.org/all/20221017151050.2321919-1-dan.sca...@ideasonboard.com/
[2]:
https://github.com/debix-tech/uboot/blob/lf_v2021.04/board/freescale/imx8mp_evk/lpddr4_timing.c
Signed-off-by: Ahmad Fatoum
[lst: cleaned up WIP patch]
Signed-off-by: Lucas Stach
---
arch/arm/boards/Makefile |1 +
arch/arm/boards/polyhex-debix/Makefile|4 +
arch/arm/boards/polyhex-debix/board.c | 49 +
.../flash-header-polyhex-debix.imxcfg |7 +
arch/arm/boards/polyhex-debix/lowlevel.c | 138 ++
arch/arm/boards/polyhex-debix/lpddr4-timing.c | 1849 +
arch/arm/dts/Makefile |1 +
.../arm/dts/imx8mp-debix-model-a-upstream.dts | 529 +
arch/arm/dts/imx8mp-debix-model-a.dts | 68 +
arch/arm/mach-imx/Kconfig | 10 +
images/Makefile.imx |5 +
11 files changed, 2661 insertions(+)
create mode 100644 arch/arm/boards/polyhex-debix/Makefile
create mode 100644 arch/arm/boards/polyhex-debix/board.c
create mode 100644
arch/arm/boards/polyhex-debix/flash-header-polyhex-debix.imxcfg
create mode 100644 arch/arm/boards/polyhex-debix/lowlevel.c
create mode 100644 arch/arm/boards/polyhex-debix/lpddr4-timing.c
create mode 100644 arch/arm/dts/imx8mp-debix-model-a-upstream.dts
create mode 100644 arch/arm/dts/imx8mp-debix-model-a.dts
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index 5006ebb5..f92094d15b1e 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -113,6 +113,7 @@ obj-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) +=
plathome-openblocks-a6/
obj-$(CONFIG_MACH_PM9261) += pm9261/
obj-$(CONFIG_MACH_PM9263) += pm9263/
obj-$(CONFIG_MACH_PM9G45) += pm9g45/
+obj-$(CONFIG_MACH_POLYHEX_DEBIX) += polyhex-debix/
obj-$(CONFIG_MACH_PROTONIC_IMX6) += protonic-imx6/
obj-$(CONFIG_MACH_PROTONIC_IMX8M) += protonic-imx8m/
obj-$(CONFIG_MACH_PROTONIC_STM32MP1) += protonic-stm32mp1/
diff --git a/arch/arm/boards/polyhex-debix/Makefile
b/arch/arm/boards/polyhex-debix/Makefile
new file mode 100644
index ..35d8640087b1
--- /dev/null
+++ b/arch/arm/boards/polyhex-debix/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+obj-y += board.o
+lwl-y += lowlevel.o lpddr4-timing.o
diff --git a/arch/arm/boards/polyhex-debix/board.c
b/arch/arm/boards/polyhex-debix/board.c
new file mode 100644
index ..849dc0f6c1d1
--- /dev/null
+++ b/arch/arm/boards/polyhex-debix/board.c
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+static int polyhex_debix_probe(struct device_d *dev)
+{
+ int emmc_bbu_flag = 0;
+ int sd_bbu_flag = 0;
+ u32 val;
+
+ if (bootsource_get() == BOOTSOURCE_MMC && bootsource_get_instance() ==
1) {
+ of_device_enable_path("/chosen/environment-sd");
+ sd_bbu_flag = BBU_HANDLER_FLAG_DEFAULT;
+ } else {
+ of_device_enable_path("/chosen/environment-emmc");
+ emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT;
+ }
+
+ imx8m_bbu_internal_mmc_register_handler("SD", "/dev/mmc1.barebox",
sd_bbu_flag);
+ imx8m_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc2",
emmc_bbu_flag);
+
+ /* Enable RGMII TX clk output */
+ val = readl(MX8MP_IOMUXC_GPR_BASE_ADDR + MX8MP_IOMUXC_GPR1);
+ val |= MX8MP_IOMUXC_GPR1_ENET1_RGMII_EN;
+ writel(val, MX8MP_IOMUXC_GPR_BASE_ADDR + MX8MP_IOMUXC_GPR1);
+
+ return 0;
+}
+
+static const struct of_device_id polyhex_debix_of_match[] = {
+ { .compatible = "polyhex,imx8mp-debix-model-a" },
+ { .compatible = "polyhex,imx8mp-debix-model-b" },
+ { /* Sentinel */ }
+};
+BAREBOX_DEEP_PROBE_ENABLE(polyhex_debix_of_match);
+
+static struct driver_d polyhex_debix_board_driver = {
+ .name = "board-imx8mp-debix",
+ .probe = polyhex_debix_probe,
+ .of_compatible = polyhex_debix_of_match,
+};
+coredevice_platform_driver(polyhex_debix_board_driver);
diff --git a/arch/arm/boards/polyhex-debix/flash-header-polyhex-debix.imxcfg
b/arch/arm/boards/polyhex-debix/flash-header-polyhex-debix.imxcfg
new file mode 100644
index ..663bd102e9a2
--- /dev/null
+++ b/arch/arm/boards/polyhex-debix/flash-header-polyhex-debix.imxcfg
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+soc imx8mp
+
+loadaddr 0x92
+max_load_size 0x3f000
+ivtofs 0x0
diff --git a/arch/ar
[PATCH 1/2] ddr: imx8m: add support for 3720 MHz DDR rate
From: Ahmad Fatoum
Signed-off-by: Ahmad Fatoum
---
drivers/ddr/imx8m/ddrphy_utils.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/ddr/imx8m/ddrphy_utils.c b/drivers/ddr/imx8m/ddrphy_utils.c
index 98e6ae648aed..7f863a1736c6 100644
--- a/drivers/ddr/imx8m/ddrphy_utils.c
+++ b/drivers/ddr/imx8m/ddrphy_utils.c
@@ -17,6 +17,7 @@
* clock / 2, which is therefor transfer rate / 4. */
enum ddr_rate {
DDR_4000,
+ DDR_3720,
DDR_3200,
DDR_3000,
DDR_2600, /* Unused */
@@ -52,6 +53,7 @@ static const struct imx8mm_fracpll_config {
bool valid;
} imx8mm_fracpll_table[DDR_NUM_RATES] = {
[DDR_4000] = { .valid = true, .r1 = MDIV(250) | PDIV(3) | SDIV(1), .r2
= 0 },
+ [DDR_3720] = { .valid = true, .r1 = MDIV(310) | PDIV(2) | SDIV(2), .r2
= 0 },
[DDR_3200] = { .valid = true, .r1 = MDIV(300) | PDIV(9) | SDIV(0), .r2
= 0 },
[DDR_3000] = { .valid = true, .r1 = MDIV(250) | PDIV(8) | SDIV(0), .r2
= 0 },
[DDR_2600] = { .valid = true, .r1 = MDIV(325) | PDIV(3) | SDIV(2), .r2
= 0 },
@@ -335,6 +337,7 @@ void ddrphy_init_set_dfi_clk(unsigned int drate_mhz, enum
ddrc_type type)
switch (drate_mhz) {
case 4000: drate = DDR_4000; break;
+ case 3720: drate = DDR_3720; break;
case 3200: drate = DDR_3200; break;
case 3000: drate = DDR_3000; break;
case 2400: drate = DDR_2400; break;
--
2.39.1
[PATCH v2 3/3] ARM: dts: i.MX8MP: add DDRC compatibles
The upstream DT currently only provides the Synopsis core compatible
for the DDRC node. Extend this with more machine specific compatibles
to allow our memory size detection to work.
Signed-off-by: Lucas Stach
---
arch/arm/dts/imx8mp.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi
index 5da79f13d339..778e84318ce7 100644
--- a/arch/arm/dts/imx8mp.dtsi
+++ b/arch/arm/dts/imx8mp.dtsi
@@ -10,6 +10,10 @@
};
};
+&edacmc {
+ compatible = "fsl,imx8mp-ddrc", "fsl,imx8m-ddrc", "snps,ddrc-3.80a";
+};
+
feat: &ocotp {
#feature-cells = <1>;
barebox,feature-controller;
--
2.39.1
[PATCH v2 1/3] ARM: i.MX8M: esdctl: limit i.MX8MP early memory size
Limit detected early memory size to 1GB on i.MX8MP, as the default DT
has a reserved memory region at 0x9240, which will conflict with
our malloc area in some configurations. Until we can properly parse
and exclude the reserved memory regions in the PBL, just avoid getting
near that DRAM address by limiting the detected size.
Signed-off-by: Lucas Stach
---
arch/arm/mach-imx/esdctl.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c
index a704250297bb..043de477a77d 100644
--- a/arch/arm/mach-imx/esdctl.c
+++ b/arch/arm/mach-imx/esdctl.c
@@ -947,7 +947,17 @@ void __noreturn imx8mn_barebox_entry(void *boarddata)
void __noreturn imx8mp_barebox_entry(void *boarddata)
{
- imx8m_barebox_entry(boarddata, 32);
+ /*
+* Limit detected early memory size to 1GB on i.MX8MP, as the default
+* DT has a reserved memory region at 0x9240, which will conflict
+* with our malloc area in some configurations. Until we can properly
+* parse and exclude the reserved memory regions in the PBL, just avoid
+* getting near that DRAM address by limiting the detected size.
+*/
+ barebox_arm_entry(MX8M_DDR_CSD1_BASE_ADDR,
+ min_t(resource_size_t, SZ_1G,
+ imx8m_barebox_earlymem_size(32)),
+ boarddata);
}
void __noreturn imx8mq_barebox_entry(void *boarddata)
--
2.39.1
[PATCH v2 2/3] ARM: i.MX8M: esdctl: use common compatible to detect i.MX8MQ/MM/MP DDRC
All i.MX8M* DDRC nodes are compatible to "fsl,imx8m-ddrc". As the memory
size detection works the same on most of them, with the only exception
being the i.MX8MM, which only has a 16bit data bus, there is no need to
match the more specific compatibles for i.MX8MQ/MM/MP.
Signed-off-by: Lucas Stach
---
arch/arm/mach-imx/esdctl.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c
index 043de477a77d..fc6db25de9e4 100644
--- a/arch/arm/mach-imx/esdctl.c
+++ b/arch/arm/mach-imx/esdctl.c
@@ -652,7 +652,7 @@ static __maybe_unused struct imx_esdctl_data vf610_data = {
.add_mem = vf610_ddrmc_add_mem,
};
-static __maybe_unused struct imx_esdctl_data imx8mq_data = {
+static __maybe_unused struct imx_esdctl_data imx8m_data = {
.base0 = MX8M_DDR_CSD1_BASE_ADDR,
.add_mem = imx8m_ddrc_add_mem,
};
@@ -732,14 +732,11 @@ static __maybe_unused struct of_device_id
imx_esdctl_dt_ids[] = {
.compatible = "fsl,vf610-ddrmc",
.data = &vf610_data
}, {
- .compatible = "fsl,imx8mm-ddrc",
- .data = &imx8mq_data
+ .compatible = "fsl,imx8m-ddrc",
+ .data = &imx8m_data
}, {
.compatible = "fsl,imx8mn-ddrc",
.data = &imx8mn_data
- }, {
- .compatible = "fsl,imx8mq-ddrc",
- .data = &imx8mq_data
}, {
.compatible = "fsl,imx7d-ddrc",
.data = &imx7d_data
--
2.39.1
Re: [PATCH] ARM: i.MX8MP-EVK: increase VDD_ARM to OD voltage
Am Dienstag, dem 07.02.2023 um 10:54 +0100 schrieb Ahmad Fatoum:
> Hello Lucas,
>
> On 06.02.23 21:59, Lucas Stach wrote:
> > The Linux kernel or whatever is started from Barebox might switch the
> > ARM frequency to OD level, without first reprogramming the PMIC as
> > required. This might lead to system instability. To avoid this,
> > increase VDD_ARM to OD level. When the kernel handles the PMIC properly
> > it will drop the voltage back to ND level when appropriate.
> >
> > Signed-off-by: Lucas Stach
> > ---
> > arch/arm/boards/nxp-imx8mp-evk/lowlevel.c | 6 ++
> > 1 file changed, 6 insertions(+)
> >
> > diff --git a/arch/arm/boards/nxp-imx8mp-evk/lowlevel.c
> > b/arch/arm/boards/nxp-imx8mp-evk/lowlevel.c
> > index 3cb24df1ca3f..d6fc32e65b61 100644
> > --- a/arch/arm/boards/nxp-imx8mp-evk/lowlevel.c
> > +++ b/arch/arm/boards/nxp-imx8mp-evk/lowlevel.c
> > @@ -61,6 +61,12 @@ static struct pmic_config pca9450_cfg[] = {
> > { PCA9450_BUCK1OUT_DVS0, 0x1C },
> > { PCA9450_BUCK1OUT_DVS1, 0x14 },
> > { PCA9450_BUCK1CTRL, 0x59 },
> > + /*
> > +* Increase VDD_ARM to 0.95V to avoid issues in case software after
> > +* Barebox switches to the OD ARM frequency without reprogramming the
> > +* PMIC first.
> > +*/
> > + { PCA9450_BUCK2OUT_DVS0, 0x1C },
>
> We use the same PMIC on nxp-imx8mn-evk and newer nxp-imx8mm-evk
> as well. Should we do this there too? Do we need to change something
> for the i.MX8M boards using Rohm PMICs?
>
Yep, I just checked: both 8MM and 8MN use the same 0.95V ARM voltage
for the OD mode. While I think it's not much a problem in practice as
the kernel does handle the PMIC before trying to switch ARM frequency
in all usual setups, better safe than sorry and put the ARM voltage
into OD on all system.
I'll send separate patches for that.
Regards,
Lucas
Re: [PATCH 2/3] ARM: i.MX8M: esdctl: use common compatible to detect i.MX8M* DDRC
Am Dienstag, dem 07.02.2023 um 11:24 +0100 schrieb Marco Felsch:
> Hi Lucas,
>
> On 23-02-06, Lucas Stach wrote:
> > All i.MX8M* DDRC nodes are compatible to "fsl,imx8m-ddrc". As the memory
> > size detection works the same on all of them, there is no need to match
> > the more specific compatible.
> >
> > Signed-off-by: Lucas Stach
> > ---
> > arch/arm/mach-imx/esdctl.c | 8 +---
> > 1 file changed, 1 insertion(+), 7 deletions(-)
> >
> > diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c
> > index 043de477a77d..2a2bc5205301 100644
> > --- a/arch/arm/mach-imx/esdctl.c
> > +++ b/arch/arm/mach-imx/esdctl.c
> > @@ -732,13 +732,7 @@ static __maybe_unused struct of_device_id
> > imx_esdctl_dt_ids[] = {
> > .compatible = "fsl,vf610-ddrmc",
> > .data = &vf610_data
> > }, {
> > - .compatible = "fsl,imx8mm-ddrc",
> > - .data = &imx8mq_data
> > - }, {
> > - .compatible = "fsl,imx8mn-ddrc",
> > - .data = &imx8mn_data
>
> The i.MX8M Nano uses a 16bit bus width according the data. I don't have
> the datasheet right now to check this. But this commit will change it to
> 32 bit, is this allowed?
Argh, thanks for catching that! This change was a bit overzealous.
Regards,
Lucas
>
> Regards,
> Marco
>
> > - }, {
> > - .compatible = "fsl,imx8mq-ddrc",
> > + .compatible = "fsl,imx8m-ddrc",
> > .data = &imx8mq_data
> > }, {
> > .compatible = "fsl,imx7d-ddrc",
> > --
> > 2.39.1
> >
> >
> >
[PATCH 2/3] ARM: i.MX8M: esdctl: use common compatible to detect i.MX8M* DDRC
All i.MX8M* DDRC nodes are compatible to "fsl,imx8m-ddrc". As the memory
size detection works the same on all of them, there is no need to match
the more specific compatible.
Signed-off-by: Lucas Stach
---
arch/arm/mach-imx/esdctl.c | 8 +---
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c
index 043de477a77d..2a2bc5205301 100644
--- a/arch/arm/mach-imx/esdctl.c
+++ b/arch/arm/mach-imx/esdctl.c
@@ -732,13 +732,7 @@ static __maybe_unused struct of_device_id
imx_esdctl_dt_ids[] = {
.compatible = "fsl,vf610-ddrmc",
.data = &vf610_data
}, {
- .compatible = "fsl,imx8mm-ddrc",
- .data = &imx8mq_data
- }, {
- .compatible = "fsl,imx8mn-ddrc",
- .data = &imx8mn_data
- }, {
- .compatible = "fsl,imx8mq-ddrc",
+ .compatible = "fsl,imx8m-ddrc",
.data = &imx8mq_data
}, {
.compatible = "fsl,imx7d-ddrc",
--
2.39.1
[PATCH 1/3] ARM: i.MX8M: esdctl: limit i.MX8MP early memory size
Limit detected early memory size to 1GB on i.MX8MP, as the default DT
has a reserved memory region at 0x9240, which will conflict with
our malloc area in some configurations. Until we can properly parse
and exclude the reserved memory regions in the PBL, just avoid getting
near that DRAM address by limiting the detected size.
Signed-off-by: Lucas Stach
---
arch/arm/mach-imx/esdctl.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c
index a704250297bb..043de477a77d 100644
--- a/arch/arm/mach-imx/esdctl.c
+++ b/arch/arm/mach-imx/esdctl.c
@@ -947,7 +947,17 @@ void __noreturn imx8mn_barebox_entry(void *boarddata)
void __noreturn imx8mp_barebox_entry(void *boarddata)
{
- imx8m_barebox_entry(boarddata, 32);
+ /*
+* Limit detected early memory size to 1GB on i.MX8MP, as the default
+* DT has a reserved memory region at 0x9240, which will conflict
+* with our malloc area in some configurations. Until we can properly
+* parse and exclude the reserved memory regions in the PBL, just avoid
+* getting near that DRAM address by limiting the detected size.
+*/
+ barebox_arm_entry(MX8M_DDR_CSD1_BASE_ADDR,
+ min_t(resource_size_t, SZ_1G,
+ imx8m_barebox_earlymem_size(32)),
+ boarddata);
}
void __noreturn imx8mq_barebox_entry(void *boarddata)
--
2.39.1
[PATCH 3/3] ARM: dts: i.MX8MP: add DDRC compatibles
The upstream DT currently only provides the Synopsis core compatible
for the DDRC node. Extend this with more machine specific compatibles
to allow our memory size detection to work.
Signed-off-by: Lucas Stach
---
arch/arm/dts/imx8mp.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi
index 5da79f13d339..778e84318ce7 100644
--- a/arch/arm/dts/imx8mp.dtsi
+++ b/arch/arm/dts/imx8mp.dtsi
@@ -10,6 +10,10 @@
};
};
+&edacmc {
+ compatible = "fsl,imx8mp-ddrc", "fsl,imx8m-ddrc", "snps,ddrc-3.80a";
+};
+
feat: &ocotp {
#feature-cells = <1>;
barebox,feature-controller;
--
2.39.1
[PATCH] ARM: i.MX8MP-EVK: increase VDD_ARM to OD voltage
The Linux kernel or whatever is started from Barebox might switch the
ARM frequency to OD level, without first reprogramming the PMIC as
required. This might lead to system instability. To avoid this,
increase VDD_ARM to OD level. When the kernel handles the PMIC properly
it will drop the voltage back to ND level when appropriate.
Signed-off-by: Lucas Stach
---
arch/arm/boards/nxp-imx8mp-evk/lowlevel.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boards/nxp-imx8mp-evk/lowlevel.c
b/arch/arm/boards/nxp-imx8mp-evk/lowlevel.c
index 3cb24df1ca3f..d6fc32e65b61 100644
--- a/arch/arm/boards/nxp-imx8mp-evk/lowlevel.c
+++ b/arch/arm/boards/nxp-imx8mp-evk/lowlevel.c
@@ -61,6 +61,12 @@ static struct pmic_config pca9450_cfg[] = {
{ PCA9450_BUCK1OUT_DVS0, 0x1C },
{ PCA9450_BUCK1OUT_DVS1, 0x14 },
{ PCA9450_BUCK1CTRL, 0x59 },
+ /*
+* Increase VDD_ARM to 0.95V to avoid issues in case software after
+* Barebox switches to the OD ARM frequency without reprogramming the
+* PMIC first.
+*/
+ { PCA9450_BUCK2OUT_DVS0, 0x1C },
/* set WDOG_B_CFG to cold reset */
{ PCA9450_RESET_CTRL, 0xA1 },
};
--
2.39.1
Re: [PATCH] clk: imx8mp: add USB suspend clock
Am Freitag, dem 03.02.2023 um 08:55 +0100 schrieb Sascha Hauer:
> On Thu, Feb 02, 2023 at 01:05:24PM +0100, Lucas Stach wrote:
> > Linux added another USB clock to properly describe the controller root
> > and suspend clocks. As new DTs are using this clock to keep the shared
> > gate enabled, access to the USB controller will hang Barebox without
> > support for this clock.
> >
> > Fixes: 0d682a2997a8 ("dts: update to v6.2-rc5")
> > Signed-off-by: Lucas Stach
> > ---
> > drivers/clk/imx/clk-imx8mp.c | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
> > index a1611be1833e..40578c2a4bd6 100644
> > --- a/drivers/clk/imx/clk-imx8mp.c
> > +++ b/drivers/clk/imx/clk-imx8mp.c
> > @@ -665,7 +665,8 @@ static int imx8mp_clocks_init(struct device_node
> > *ccm_np)
> > hws[IMX8MP_CLK_UART2_ROOT] = imx_clk_hw_gate4("uart2_root_clk",
> > "uart2", ccm_base + 0x44a0, 0);
> > hws[IMX8MP_CLK_UART3_ROOT] = imx_clk_hw_gate4("uart3_root_clk",
> > "uart3", ccm_base + 0x44b0, 0);
> > hws[IMX8MP_CLK_UART4_ROOT] = imx_clk_hw_gate4("uart4_root_clk",
> > "uart4", ccm_base + 0x44c0, 0);
> > - hws[IMX8MP_CLK_USB_ROOT] = imx_clk_hw_gate4("usb_root_clk", "osc_32k",
> > ccm_base + 0x44d0, 0);
> > + hws[IMX8MP_CLK_USB_ROOT] = imx_clk_hw_gate2_shared2("usb_root_clk",
> > "hsio_axi", ccm_base + 0x44d0, 0);
> > + hws[IMX8MP_CLK_USB_SUSP] = imx_clk_hw_gate2_shared2("usb_suspend_clk",
> > "osc_32k", ccm_base + 0x44d0, 0);
>
> Do old dts files work with this change? In other words, can I apply this
> directly to master or do I have to squash this change into the commit
> that changes imx8mp.dtsi to use this clock?
>
As the old clock ID is still supported from the clock driver after this
change and operates the same gate, it should be fine to apply this
patch to master.
Regards,
Lucas
[PATCH 5/5] ARM: dts: i.MX8MP: drop OCOTP MAC address provider
Now that the MAC address can be read properly through the
NVMEM framework, there is no need for the custom Barebox
MAC address provider anymore. Both FEC and EQOS network
interfaces already reference the proper nvmem cells to fetch
their MAC address from OCOTP.
Signed-off-by: Lucas Stach
---
arch/arm/dts/imx8mp-evk.dts| 4
arch/arm/dts/imx8mp-tqma8mpql-mba8mpxl.dts | 4
2 files changed, 8 deletions(-)
diff --git a/arch/arm/dts/imx8mp-evk.dts b/arch/arm/dts/imx8mp-evk.dts
index d992b14882a3..28d8c5f9292e 100644
--- a/arch/arm/dts/imx8mp-evk.dts
+++ b/arch/arm/dts/imx8mp-evk.dts
@@ -68,7 +68,3 @@
reg = <0xe 0x2>;
};
};
-
-&ocotp {
- barebox,provide-mac-address = <&fec 0x640>;
-};
diff --git a/arch/arm/dts/imx8mp-tqma8mpql-mba8mpxl.dts
b/arch/arm/dts/imx8mp-tqma8mpql-mba8mpxl.dts
index c47e7285a703..6e81f58e2786 100644
--- a/arch/arm/dts/imx8mp-tqma8mpql-mba8mpxl.dts
+++ b/arch/arm/dts/imx8mp-tqma8mpql-mba8mpxl.dts
@@ -53,7 +53,3 @@
reg = <0xe 0x2>;
};
};
-
-&ocotp {
- barebox,provide-mac-address = <&fec 0x640>;
-};
--
2.39.1
[PATCH 3/5] nvmem: regmap: allow to register with post processing
Add a new registration function that allows to fill the cell_post_process
function pointer.
Signed-off-by: Lucas Stach
---
drivers/nvmem/regmap.c | 10 +-
include/linux/nvmem-provider.h | 9 +
2 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/nvmem/regmap.c b/drivers/nvmem/regmap.c
index 56611819a2b4..58b3fe647b28 100644
--- a/drivers/nvmem/regmap.c
+++ b/drivers/nvmem/regmap.c
@@ -58,7 +58,9 @@ static struct nvmem_bus nvmem_regmap_bus = {
.write = nvmem_regmap_write,
};
-struct nvmem_device *nvmem_regmap_register(struct regmap *map, const char
*name)
+struct nvmem_device *
+nvmem_regmap_register_with_pp(struct regmap *map, const char *name,
+ nvmem_cell_post_process_t cell_post_process)
{
struct nvmem_config config = {};
@@ -73,6 +75,12 @@ struct nvmem_device *nvmem_regmap_register(struct regmap
*map, const char *name)
config.word_size = 1;
config.size = regmap_get_max_register(map) * regmap_get_reg_stride(map);
config.bus = &nvmem_regmap_bus;
+ config.cell_post_process = cell_post_process;
return nvmem_register(&config);
}
+
+struct nvmem_device *nvmem_regmap_register(struct regmap *map, const char
*name)
+{
+ return nvmem_regmap_register_with_pp(map, name, NULL);
+}
diff --git a/include/linux/nvmem-provider.h b/include/linux/nvmem-provider.h
index 2f130e51791c..43fe49648e66 100644
--- a/include/linux/nvmem-provider.h
+++ b/include/linux/nvmem-provider.h
@@ -47,6 +47,8 @@ struct cdev;
struct nvmem_device *nvmem_register(const struct nvmem_config *cfg);
struct nvmem_device *nvmem_regmap_register(struct regmap *regmap, const char
*name);
+struct nvmem_device *nvmem_regmap_register_with_pp(struct regmap *regmap,
+ const char *name, nvmem_cell_post_process_t cell_post_process);
struct nvmem_device *nvmem_partition_register(struct cdev *cdev);
#else
@@ -61,6 +63,13 @@ static inline struct nvmem_device
*nvmem_regmap_register(struct regmap *regmap,
return ERR_PTR(-ENOSYS);
}
+static inline struct nvmem_device *
+nvmem_regmap_register_with_pp(struct regmap *regmap, const char *name,
+ nvmem_cell_post_process_t cell_post_process)
+{
+ return ERR_PTR(-ENOSYS);
+}
+
static inline struct nvmem_device *nvmem_partition_register(struct cdev *cdev)
{
return ERR_PTR(-ENOSYS);
--
2.39.1
[PATCH 4/5] nvmem: ocotp: add post processing for MAC cells
Add a nvmem post process callback to swap the MAC address as required
when read via nvmem.
Signed-off-by: Lucas Stach
---
drivers/nvmem/ocotp.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/nvmem/ocotp.c b/drivers/nvmem/ocotp.c
index 78c9f9726db0..b478ece30680 100644
--- a/drivers/nvmem/ocotp.c
+++ b/drivers/nvmem/ocotp.c
@@ -641,6 +641,21 @@ static struct regmap_bus imx_ocotp_regmap_bus = {
.reg_read = imx_ocotp_reg_read,
};
+static int imx_ocotp_cell_pp(void *context, const char *id, unsigned int
offset,
+void *data, size_t bytes)
+{
+ /* Deal with some post processing of nvmem cell data */
+ if (id && !strcmp(id, "mac-address")) {
+ u8 *buf = data;
+ int i;
+
+ for (i = 0; i < bytes/2; i++)
+ swap(buf[i], buf[bytes - i - 1]);
+ }
+
+ return 0;
+}
+
static int imx_ocotp_init_dt(struct ocotp_priv *priv)
{
char mac[MAC_BYTES];
@@ -731,7 +746,8 @@ static int imx_ocotp_probe(struct device *dev)
if (IS_ERR(priv->map))
return PTR_ERR(priv->map);
- nvmem = nvmem_regmap_register(priv->map, "imx-ocotp");
+ nvmem = nvmem_regmap_register_with_pp(priv->map, "imx-ocotp",
+ imx_ocotp_cell_pp);
if (IS_ERR(nvmem))
return PTR_ERR(nvmem);
--
2.39.1
[PATCH 1/5] nvmem: add support for post processing
This is a port of the Linux commit 5008062f1c3f ("nvmem: core: add nvmem
cell post processing callback"). It looks a little different, as Linux
switched to create nvmem cells at registration time, effectively
deduplicating the cells, but then needed to introduce nvmem_cells_entry
to be able to store the lookup name, which is used by the post-processing.
As Barebox simply created a nvmem cell per lookup, as Linux did before
e888d445ac33 ("nvmem: resolve cells from DT at registration time"), we
can simply store the lookup name in the cell.
Signed-off-by: Lucas Stach
---
drivers/nvmem/core.c | 12
include/linux/nvmem-provider.h | 6 ++
2 files changed, 18 insertions(+)
diff --git a/drivers/nvmem/core.c b/drivers/nvmem/core.c
index cd3328a650d6..e0110296f87b 100644
--- a/drivers/nvmem/core.c
+++ b/drivers/nvmem/core.c
@@ -26,10 +26,12 @@ struct nvmem_device {
boolread_only;
struct cdev cdev;
void*priv;
+ nvmem_cell_post_process_t cell_post_process;
};
struct nvmem_cell {
const char *name;
+ const char *id;
int offset;
int bytes;
int bit_offset;
@@ -145,6 +147,7 @@ static struct nvmem_cell *nvmem_find_cell(const char
*cell_id)
static void nvmem_cell_drop(struct nvmem_cell *cell)
{
list_del(&cell->node);
+ kfree(cell->id);
kfree(cell);
}
@@ -209,6 +212,7 @@ struct nvmem_device *nvmem_register(const struct
nvmem_config *config)
np = config->cdev ? config->cdev->device_node : config->dev->of_node;
nvmem->dev.of_node = np;
nvmem->priv = config->priv;
+ nvmem->cell_post_process = config->cell_post_process;
if (config->read_only || !config->bus->write ||
of_property_read_bool(np, "read-only"))
nvmem->read_only = true;
@@ -417,6 +421,7 @@ struct nvmem_cell *of_nvmem_cell_get(struct device_node *np,
cell->offset = be32_to_cpup(addr++);
cell->bytes = be32_to_cpup(addr);
cell->name = cell_np->name;
+ cell->id = kstrdup_const(name, GFP_KERNEL);
addr = of_get_property(cell_np, "bits", &len);
if (addr && len == (2 * sizeof(u32))) {
@@ -534,6 +539,13 @@ static int __nvmem_cell_read(struct nvmem_device *nvmem,
if (cell->bit_offset || cell->nbits)
nvmem_shift_read_buffer_in_place(cell, buf);
+ if (nvmem->cell_post_process) {
+ rc = nvmem->cell_post_process(nvmem->priv, cell->id,
+ cell->offset, buf, cell->bytes);
+ if (rc)
+ return rc;
+ }
+
*len = cell->bytes;
return 0;
diff --git a/include/linux/nvmem-provider.h b/include/linux/nvmem-provider.h
index 1d4e1b75b204..2f130e51791c 100644
--- a/include/linux/nvmem-provider.h
+++ b/include/linux/nvmem-provider.h
@@ -22,6 +22,11 @@ struct nvmem_bus {
int (*read)(void *ctx, unsigned int reg, void *val, size_t val_size);
};
+/* used for vendor specific post processing of cell data */
+typedef int (*nvmem_cell_post_process_t)(void *priv, const char *id,
+unsigned int offset, void *buf,
+size_t bytes);
+
struct nvmem_config {
struct device *dev;
const char *name;
@@ -32,6 +37,7 @@ struct nvmem_config {
int size;
const struct nvmem_bus *bus;
void*priv;
+ nvmem_cell_post_process_t cell_post_process;
};
struct regmap;
--
2.39.1
[PATCH 2/5] nvmem: ocotp: switch to nvmem_regmap_register
Signed-off-by: Lucas Stach
---
drivers/nvmem/ocotp.c | 30 +-
1 file changed, 1 insertion(+), 29 deletions(-)
diff --git a/drivers/nvmem/ocotp.c b/drivers/nvmem/ocotp.c
index e75fac75eab8..78c9f9726db0 100644
--- a/drivers/nvmem/ocotp.c
+++ b/drivers/nvmem/ocotp.c
@@ -131,7 +131,6 @@ struct ocotp_priv {
struct regmap_config map_config;
const struct imx_ocotp_data *data;
int mac_offset_idx;
- struct nvmem_config config;
};
static struct ocotp_priv *imx_ocotp;
@@ -682,20 +681,6 @@ static int imx_ocotp_init_dt(struct ocotp_priv *priv)
return imx8m_feat_ctrl_init(priv->dev.parent, tester4,
priv->data->feat);
}
-static int imx_ocotp_write(void *ctx, unsigned offset, const void *val, size_t
bytes)
-{
- struct ocotp_priv *priv = ctx;
-
- return regmap_bulk_write(priv->map, offset, val, bytes);
-}
-
-static int imx_ocotp_read(void *ctx, unsigned offset, void *val, size_t bytes)
-{
- struct ocotp_priv *priv = ctx;
-
- return regmap_bulk_read(priv->map, offset, val, bytes);
-}
-
static void imx_ocotp_set_unique_machine_id(void)
{
uint32_t unique_id_parts[UNIQUE_ID_NUM];
@@ -709,11 +694,6 @@ static void imx_ocotp_set_unique_machine_id(void)
machine_id_set_hashable(unique_id_parts, sizeof(unique_id_parts));
}
-static const struct nvmem_bus imx_ocotp_nvmem_bus = {
- .write = imx_ocotp_write,
- .read = imx_ocotp_read,
-};
-
static int imx_ocotp_probe(struct device *dev)
{
struct resource *iores;
@@ -751,15 +731,7 @@ static int imx_ocotp_probe(struct device *dev)
if (IS_ERR(priv->map))
return PTR_ERR(priv->map);
- priv->config.name = "imx-ocotp";
- priv->config.dev = dev;
- priv->config.priv = priv;
- priv->config.stride = 4;
- priv->config.word_size = 4;
- priv->config.size = data->num_regs;
- priv->config.bus = &imx_ocotp_nvmem_bus;
-
- nvmem = nvmem_register(&priv->config);
+ nvmem = nvmem_regmap_register(priv->map, "imx-ocotp");
if (IS_ERR(nvmem))
return PTR_ERR(nvmem);
--
2.39.1
[PATCH] clk: imx8mp: add USB suspend clock
Linux added another USB clock to properly describe the controller root
and suspend clocks. As new DTs are using this clock to keep the shared
gate enabled, access to the USB controller will hang Barebox without
support for this clock.
Fixes: 0d682a2997a8 ("dts: update to v6.2-rc5")
Signed-off-by: Lucas Stach
---
drivers/clk/imx/clk-imx8mp.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index a1611be1833e..40578c2a4bd6 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -665,7 +665,8 @@ static int imx8mp_clocks_init(struct device_node *ccm_np)
hws[IMX8MP_CLK_UART2_ROOT] = imx_clk_hw_gate4("uart2_root_clk",
"uart2", ccm_base + 0x44a0, 0);
hws[IMX8MP_CLK_UART3_ROOT] = imx_clk_hw_gate4("uart3_root_clk",
"uart3", ccm_base + 0x44b0, 0);
hws[IMX8MP_CLK_UART4_ROOT] = imx_clk_hw_gate4("uart4_root_clk",
"uart4", ccm_base + 0x44c0, 0);
- hws[IMX8MP_CLK_USB_ROOT] = imx_clk_hw_gate4("usb_root_clk", "osc_32k",
ccm_base + 0x44d0, 0);
+ hws[IMX8MP_CLK_USB_ROOT] = imx_clk_hw_gate2_shared2("usb_root_clk",
"hsio_axi", ccm_base + 0x44d0, 0);
+ hws[IMX8MP_CLK_USB_SUSP] = imx_clk_hw_gate2_shared2("usb_suspend_clk",
"osc_32k", ccm_base + 0x44d0, 0);
hws[IMX8MP_CLK_USB_PHY_ROOT] = imx_clk_hw_gate4("usb_phy_root_clk",
"usb_phy_ref", ccm_base + 0x44f0, 0);
hws[IMX8MP_CLK_USDHC1_ROOT] = imx_clk_hw_gate4("usdhc1_root_clk",
"usdhc1", ccm_base + 0x4510, 0);
hws[IMX8MP_CLK_USDHC2_ROOT] = imx_clk_hw_gate4("usdhc2_root_clk",
"usdhc2", ccm_base + 0x4520, 0);
--
2.39.1
Re: [PATCH 2/3] ARM: dts: i.MX8MP: move MAC address description to common location
Am Mittwoch, dem 11.01.2023 um 21:13 +0100 schrieb Ahmad Fatoum:
> On 11.01.23 21:00, Lucas Stach wrote:
> > Hi Ahmad,
> >
> > Am Mittwoch, dem 11.01.2023 um 20:03 +0100 schrieb Ahmad Fatoum:
> > > Hello Lucas,
> > >
> > > On 11.01.23 19:21, Lucas Stach wrote:
> > > > All i.MX8MP boards should consult the common fuse locations for the
> > > > MAC address of the network interfaces. Also add the second location
> > > > for the EQOS network interface.
> > >
> > > Do we really want to extend use of this binding? The upstream kernel
> > > DT already has nvmem-cells for the MAC addresses and we have support
> > > for reading that out.
> > >
> > I thought about this too, but...
> >
> > > Only thing missing is the equivalent of
> > >
> > > Linux commit d0221a780cbc ("nvmem: imx-ocotp: add support for post
> > > processing")
> > >
> > This isn't the only thing missing. To handle the second MAC address via
> > NMEM, we would need to add unaligned read/write support to the OCOTP
> > driver. The currently used regmap_read/write_bulk API does only work
> > with register aligned accesses. The benefit of NVMEM didn't look that
> > tempting anymore when looking at the cost of the necessary OCOTP driver
> > changes, so I choose to go with the more minimal change.
>
> You can switch the driver over to use nvmem_regmap_register(), which will
> take care of the alignment for you. I still think it's worth it.
>
Thanks, didn't know about this one. I'll take a stab at converting the
OCOTP driver.
Regards,
Lucas
> Cheers,
> Ahmad
>
> >
> > Regards,
> > Lucas
> >
> > > Cheers,
> > > Ahmad
> > >
> > > >
> > > > Signed-off-by: Lucas Stach
> > > > ---
> > > > arch/arm/dts/imx8mp-evk.dts| 4
> > > > arch/arm/dts/imx8mp-tqma8mpql-mba8mpxl.dts | 4
> > > > arch/arm/dts/imx8mp.dtsi | 1 +
> > > > 3 files changed, 1 insertion(+), 8 deletions(-)
> > > >
> > > > diff --git a/arch/arm/dts/imx8mp-evk.dts b/arch/arm/dts/imx8mp-evk.dts
> > > > index d992b14882a3..28d8c5f9292e 100644
> > > > --- a/arch/arm/dts/imx8mp-evk.dts
> > > > +++ b/arch/arm/dts/imx8mp-evk.dts
> > > > @@ -68,7 +68,3 @@
> > > > reg = <0xe 0x2>;
> > > > };
> > > > };
> > > > -
> > > > -&ocotp {
> > > > - barebox,provide-mac-address = <&fec 0x640>;
> > > > -};
> > > > diff --git a/arch/arm/dts/imx8mp-tqma8mpql-mba8mpxl.dts
> > > > b/arch/arm/dts/imx8mp-tqma8mpql-mba8mpxl.dts
> > > > index c47e7285a703..6e81f58e2786 100644
> > > > --- a/arch/arm/dts/imx8mp-tqma8mpql-mba8mpxl.dts
> > > > +++ b/arch/arm/dts/imx8mp-tqma8mpql-mba8mpxl.dts
> > > > @@ -53,7 +53,3 @@
> > > > reg = <0xe 0x2>;
> > > > };
> > > > };
> > > > -
> > > > -&ocotp {
> > > > - barebox,provide-mac-address = <&fec 0x640>;
> > > > -};
> > > > diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi
> > > > index 5da79f13d339..379fa49d6042 100644
> > > > --- a/arch/arm/dts/imx8mp.dtsi
> > > > +++ b/arch/arm/dts/imx8mp.dtsi
> > > > @@ -13,6 +13,7 @@
> > > > feat: &ocotp {
> > > > #feature-cells = <1>;
> > > > barebox,feature-controller;
> > > > + barebox,provide-mac-address = <&fec 0x640 &eqos 0x650>;
> > > > };
> > > >
> > > > &pgc_mipi_phy1 {
> > >
> >
> >
>
Re: [PATCH 2/3] ARM: dts: i.MX8MP: move MAC address description to common location
Hi Ahmad,
Am Mittwoch, dem 11.01.2023 um 20:03 +0100 schrieb Ahmad Fatoum:
> Hello Lucas,
>
> On 11.01.23 19:21, Lucas Stach wrote:
> > All i.MX8MP boards should consult the common fuse locations for the
> > MAC address of the network interfaces. Also add the second location
> > for the EQOS network interface.
>
> Do we really want to extend use of this binding? The upstream kernel
> DT already has nvmem-cells for the MAC addresses and we have support
> for reading that out.
>
I thought about this too, but...
> Only thing missing is the equivalent of
>
> Linux commit d0221a780cbc ("nvmem: imx-ocotp: add support for post
> processing")
>
This isn't the only thing missing. To handle the second MAC address via
NMEM, we would need to add unaligned read/write support to the OCOTP
driver. The currently used regmap_read/write_bulk API does only work
with register aligned accesses. The benefit of NVMEM didn't look that
tempting anymore when looking at the cost of the necessary OCOTP driver
changes, so I choose to go with the more minimal change.
Regards,
Lucas
> Cheers,
> Ahmad
>
> >
> > Signed-off-by: Lucas Stach
> > ---
> > arch/arm/dts/imx8mp-evk.dts| 4
> > arch/arm/dts/imx8mp-tqma8mpql-mba8mpxl.dts | 4
> > arch/arm/dts/imx8mp.dtsi | 1 +
> > 3 files changed, 1 insertion(+), 8 deletions(-)
> >
> > diff --git a/arch/arm/dts/imx8mp-evk.dts b/arch/arm/dts/imx8mp-evk.dts
> > index d992b14882a3..28d8c5f9292e 100644
> > --- a/arch/arm/dts/imx8mp-evk.dts
> > +++ b/arch/arm/dts/imx8mp-evk.dts
> > @@ -68,7 +68,3 @@
> > reg = <0xe 0x2>;
> > };
> > };
> > -
> > -&ocotp {
> > - barebox,provide-mac-address = <&fec 0x640>;
> > -};
> > diff --git a/arch/arm/dts/imx8mp-tqma8mpql-mba8mpxl.dts
> > b/arch/arm/dts/imx8mp-tqma8mpql-mba8mpxl.dts
> > index c47e7285a703..6e81f58e2786 100644
> > --- a/arch/arm/dts/imx8mp-tqma8mpql-mba8mpxl.dts
> > +++ b/arch/arm/dts/imx8mp-tqma8mpql-mba8mpxl.dts
> > @@ -53,7 +53,3 @@
> > reg = <0xe 0x2>;
> > };
> > };
> > -
> > -&ocotp {
> > - barebox,provide-mac-address = <&fec 0x640>;
> > -};
> > diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi
> > index 5da79f13d339..379fa49d6042 100644
> > --- a/arch/arm/dts/imx8mp.dtsi
> > +++ b/arch/arm/dts/imx8mp.dtsi
> > @@ -13,6 +13,7 @@
> > feat: &ocotp {
> > #feature-cells = <1>;
> > barebox,feature-controller;
> > + barebox,provide-mac-address = <&fec 0x640 &eqos 0x650>;
> > };
> >
> > &pgc_mipi_phy1 {
>
[PATCH 1/3] nvmem: ocotp: add support for second MAC address on i.MX8MP
i.MX8MP has the same quirk as the i.MX6UL: the MAC address for the
second ethernet interface is stored at an unaligned location and thus
needs to be handled by skipping the first 2 bytes from the OCOTP
register.
Signed-off-by: Lucas Stach
---
drivers/nvmem/ocotp.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/nvmem/ocotp.c b/drivers/nvmem/ocotp.c
index 7cc2b3b3db58..9d4d6e91db74 100644
--- a/drivers/nvmem/ocotp.c
+++ b/drivers/nvmem/ocotp.c
@@ -88,6 +88,7 @@
#define MAC_OFFSET_0 (0x22 * 4)
#define IMX6UL_MAC_OFFSET_1(0x23 * 4)
#define MAC_OFFSET_1 (0x24 * 4)
+#define IMX8MP_MAC_OFFSET_1(0x25 * 4)
#define MAX_MAC_OFFSETS2
#define MAC_BYTES 8
#define UNIQUE_ID_NUM 2
@@ -598,7 +599,7 @@ static int imx_ocotp_read_mac(const struct imx_ocotp_data
*data,
if (ret < 0)
return ret;
- if (offset != IMX6UL_MAC_OFFSET_1)
+ if (offset != IMX6UL_MAC_OFFSET_1 && offset != IMX8MP_MAC_OFFSET_1)
data->format_mac(mac, buf, OCOTP_HW_TO_MAC);
else
data->format_mac(mac, buf + 2, OCOTP_HW_TO_MAC);
@@ -624,7 +625,8 @@ static int imx_ocotp_set_mac(struct param_d *param, void
*priv)
if (ret < 0)
return ret;
- if (ethaddr->offset != IMX6UL_MAC_OFFSET_1)
+ if (ethaddr->offset != IMX6UL_MAC_OFFSET_1 &&
+ ethaddr->offset != IMX8MP_MAC_OFFSET_1)
ethaddr->data->format_mac(buf, ethaddr->value,
OCOTP_MAC_TO_HW);
else
@@ -898,7 +900,7 @@ static struct imx_ocotp_data imx8mp_ocotp_data = {
.num_regs = 1024,
.addr_to_offset = imx6sl_addr_to_offset,
.mac_offsets_num = 2,
- .mac_offsets = { 0x90, 0x96 },
+ .mac_offsets = { 0x90, 0x94 },
.format_mac = imx_ocotp_format_mac,
.feat = &imx8mp_featctrl_data,
};
--
2.39.0
[PATCH 3/3] net: eqos: add i.MX8MP support
This adds the platform glue for the Designware EQOS ethernet interface
as implemented on the i.MX8MP SoC.
Signed-off-by: Lucas Stach
---
drivers/net/Kconfig | 8 ++
drivers/net/Makefile | 1 +
drivers/net/designware_imx8.c | 194 ++
3 files changed, 203 insertions(+)
create mode 100644 drivers/net/designware_imx8.c
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 2dafd9c7a8b9..e871b7e11af7 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -107,6 +107,14 @@ config DRIVER_NET_DESIGNWARE_EQOS
This option enables support for the Synopsys
Designware Ethernet Quality-of-Service (GMAC4).
+config DRIVER_NET_DESIGNWARE_IMX8
+ bool "Designware EQOS i.MX8 Ethernet driver"
+ depends on HAS_DMA && COMMON_CLK && OFTREE && (ARCH_IMX8M ||
COMPILE_TEST)
+ select DRIVER_NET_DESIGNWARE_EQOS
+ help
+ This option enables support for the Designware EQOS MAC implemented on
+ the NXP i.MX8 SoCs.
+
config DRIVER_NET_DESIGNWARE_STM32
bool "STM32 Designware Ethernet driver"
depends on HAS_DMA && COMMON_CLK && OFTREE && (ARCH_STM32MP ||
COMPILE_TEST)
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 7ff330a2bf42..6a44a12bf88a 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_DRIVER_NET_DESIGNWARE_GENERIC) +=
designware_generic.o
obj-$(CONFIG_DRIVER_NET_DESIGNWARE_SOCFPGA) += designware_socfpga.o
obj-$(CONFIG_DRIVER_NET_DESIGNWARE_STARFIVE) += designware_starfive.o
obj-$(CONFIG_DRIVER_NET_DESIGNWARE_EQOS) += designware_eqos.o
+obj-$(CONFIG_DRIVER_NET_DESIGNWARE_IMX8) += designware_imx8.o
obj-$(CONFIG_DRIVER_NET_DESIGNWARE_STM32) += designware_stm32.o
obj-$(CONFIG_DRIVER_NET_DESIGNWARE_TEGRA186) += designware_tegra186.o
obj-$(CONFIG_DRIVER_NET_DESIGNWARE_ROCKCHIP) += designware_rockchip.o
diff --git a/drivers/net/designware_imx8.c b/drivers/net/designware_imx8.c
new file mode 100644
index ..e64fc57c3e13
--- /dev/null
+++ b/drivers/net/designware_imx8.c
@@ -0,0 +1,194 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "designware_eqos.h"
+
+#define GPR_ENET_QOS_INTF_MODE_MASKGENMASK(21, 16)
+#define GPR_ENET_QOS_INTF_SEL_MII (0x0 << 16)
+#define GPR_ENET_QOS_INTF_SEL_RGMII(0x1 << 16)
+#define GPR_ENET_QOS_INTF_SEL_RMII (0x4 << 16)
+#define GPR_ENET_QOS_CLK_GEN_ENBIT(19)
+#define GPR_ENET_QOS_CLK_TX_CLK_SELBIT(20)
+#define GPR_ENET_QOS_RGMII_EN BIT(21)
+
+
+struct eqos_imx8_priv {
+ struct device_d *dev;
+ struct clk_bulk_data *clks;
+ int num_clks;
+ struct regmap *intf_regmap;
+ u32 intf_reg_off;
+ bool rmii_refclk_ext;
+};
+
+enum { CLK_STMMACETH, CLK_PCLK, CLK_PTP_REF, CLK_TX};
+static const struct clk_bulk_data imx8_clks[] = {
+ [CLK_STMMACETH] = { .id = "stmmaceth" },
+ [CLK_PCLK] = { .id = "pclk" },
+ [CLK_PTP_REF] = { .id = "ptp_ref" },
+ [CLK_TX]= { .id = "tx" },
+};
+
+static unsigned long eqos_get_csr_clk_rate_imx8(struct eqos *eqos)
+{
+ struct eqos_imx8_priv *priv = eqos->priv;
+
+ return clk_get_rate(priv->clks[CLK_PCLK].clk);
+}
+
+
+static void eqos_adjust_link_imx8(struct eth_device *edev)
+{
+ struct eqos *eqos = edev->priv;
+ struct eqos_imx8_priv *priv = eqos->priv;
+ unsigned long rate;
+ int ret;
+
+ switch (edev->phydev->speed) {
+ case SPEED_10:
+ rate = 250;
+ break;
+ case SPEED_100:
+ rate = 2500;
+ break;
+ case SPEED_1000:
+ rate = 12500;
+ break;
+ default:
+ dev_err(priv->dev, "unknown speed value for GMAC speed=%d",
+ edev->phydev->speed);
+ return;
+ }
+
+ ret = clk_set_rate(priv->clks[CLK_TX].clk, rate);
+ if (ret)
+ dev_err(priv->dev, "set TX clk rate %ld failed %d\n",
+ rate, ret);
+
+ eqos_adjust_link(edev);
+}
+
+static void eqos_imx8_set_interface_mode(struct eqos *eqos)
+{
+ struct eqos_imx8_priv *priv = eqos->priv;
+ struct device_node *np = priv->dev->device_node;
+ int val;
+
+ if (!of_device_is_compatible(np, "nxp,imx8mp-dwmac-eqos"))
+ return;
+
+ switch (eqos->interface) {
+ case PHY_INTERFACE_MODE_MII:
+ val = GPR_ENET_QOS_INTF_SEL_MII;
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ val = GPR_ENET_QOS_INTF_SEL_RMII;
+ val |= (priv->rmii_refclk_ext ? 0 :
GPR_ENET_QOS_CLK_TX_CLK_SEL
[PATCH 2/3] ARM: dts: i.MX8MP: move MAC address description to common location
All i.MX8MP boards should consult the common fuse locations for the
MAC address of the network interfaces. Also add the second location
for the EQOS network interface.
Signed-off-by: Lucas Stach
---
arch/arm/dts/imx8mp-evk.dts| 4
arch/arm/dts/imx8mp-tqma8mpql-mba8mpxl.dts | 4
arch/arm/dts/imx8mp.dtsi | 1 +
3 files changed, 1 insertion(+), 8 deletions(-)
diff --git a/arch/arm/dts/imx8mp-evk.dts b/arch/arm/dts/imx8mp-evk.dts
index d992b14882a3..28d8c5f9292e 100644
--- a/arch/arm/dts/imx8mp-evk.dts
+++ b/arch/arm/dts/imx8mp-evk.dts
@@ -68,7 +68,3 @@
reg = <0xe 0x2>;
};
};
-
-&ocotp {
- barebox,provide-mac-address = <&fec 0x640>;
-};
diff --git a/arch/arm/dts/imx8mp-tqma8mpql-mba8mpxl.dts
b/arch/arm/dts/imx8mp-tqma8mpql-mba8mpxl.dts
index c47e7285a703..6e81f58e2786 100644
--- a/arch/arm/dts/imx8mp-tqma8mpql-mba8mpxl.dts
+++ b/arch/arm/dts/imx8mp-tqma8mpql-mba8mpxl.dts
@@ -53,7 +53,3 @@
reg = <0xe 0x2>;
};
};
-
-&ocotp {
- barebox,provide-mac-address = <&fec 0x640>;
-};
diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi
index 5da79f13d339..379fa49d6042 100644
--- a/arch/arm/dts/imx8mp.dtsi
+++ b/arch/arm/dts/imx8mp.dtsi
@@ -13,6 +13,7 @@
feat: &ocotp {
#feature-cells = <1>;
barebox,feature-controller;
+ barebox,provide-mac-address = <&fec 0x640 &eqos 0x650>;
};
&pgc_mipi_phy1 {
--
2.39.0
[PATCH 1/4] ARM: imx8m: allow ddr_get_firmware to be called from other units
Signed-off-by: Lucas Stach
---
include/soc/imx8m/ddr.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/soc/imx8m/ddr.h b/include/soc/imx8m/ddr.h
index 2149ae432554..0b3c4d47e39d 100644
--- a/include/soc/imx8m/ddr.h
+++ b/include/soc/imx8m/ddr.h
@@ -389,7 +389,7 @@ extern struct dram_timing_info dram_timing;
void ddr_get_firmware_lpddr4(void);
void ddr_get_firmware_ddr(void);
-static void ddr_get_firmware(enum dram_type dram_type)
+static inline void ddr_get_firmware(enum dram_type dram_type)
{
if (dram_type == DRAM_TYPE_LPDDR4)
ddr_get_firmware_lpddr4();
--
2.38.1
[PATCH 4/4] ARM: phytec-som-imx8mq: include DDR firmware in image
This board uses the legacy DRAM initialization and doesn't call
imx8mq_ddr_init(), so there is no point where the DRAM firmware is
referenced from the image. Fix this by calling ddr_get_firmware()
from the legacy DRAM init.
Fixes: e770d18108de ("ARM: i.MX8M: include only necessary ddrphy firmwares in
image")
Signed-off-by: Lucas Stach
---
arch/arm/boards/phytec-som-imx8mq/ddrphy_train.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boards/phytec-som-imx8mq/ddrphy_train.c
b/arch/arm/boards/phytec-som-imx8mq/ddrphy_train.c
index 2c84a0f5fd5a..2ed6578093af 100644
--- a/arch/arm/boards/phytec-som-imx8mq/ddrphy_train.c
+++ b/arch/arm/boards/phytec-som-imx8mq/ddrphy_train.c
@@ -12,6 +12,8 @@
void ddr_cfg_phy(void) {
unsigned int tmp, tmp_t;
+ ddr_get_firmware(DRAM_TYPE_LPDDR4);
+
//Init DDRPHY register...
reg32_write(0x3c080440,0x2);
reg32_write(0x3c080444,0x3);
--
2.38.1
[PATCH 3/4] ARM: zii-imx8mq-dev: include DDR firmware in image
This board uses the legacy DRAM initialization and doesn't call
imx8mq_ddr_init(), so there is no point where the DRAM firmware is
referenced from the image. Fix this by calling ddr_get_firmware()
from the legacy DRAM init.
Fixes: e770d18108de ("ARM: i.MX8M: include only necessary ddrphy firmwares in
image")
Signed-off-by: Lucas Stach
---
arch/arm/boards/zii-imx8mq-dev/ddrphy_train.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boards/zii-imx8mq-dev/ddrphy_train.c
b/arch/arm/boards/zii-imx8mq-dev/ddrphy_train.c
index d2c73fc7ce22..e8577369dc8b 100644
--- a/arch/arm/boards/zii-imx8mq-dev/ddrphy_train.c
+++ b/arch/arm/boards/zii-imx8mq-dev/ddrphy_train.c
@@ -11,6 +11,8 @@
void ddr_cfg_phy(void) {
unsigned int tmp, tmp_t;
+ ddr_get_firmware(DRAM_TYPE_LPDDR4);
+
//Init DDRPHY register...
reg32_write(0x3c080440,0x2);
reg32_write(0x3c080444,0x3);
--
2.38.1
[PATCH 2/4] ARM: nxp-imx8mq-evk: include DDR firmware in image
This board uses the legacy DRAM initialization and doesn't call
imx8mq_ddr_init(), so there is no point where the DRAM firmware is
referenced from the image. Fix this by calling ddr_get_firmware()
from the legacy DRAM init.
Fixes: e770d18108de ("ARM: i.MX8M: include only necessary ddrphy firmwares in
image")
Signed-off-by: Lucas Stach
---
arch/arm/boards/nxp-imx8mq-evk/ddrphy_train.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boards/nxp-imx8mq-evk/ddrphy_train.c
b/arch/arm/boards/nxp-imx8mq-evk/ddrphy_train.c
index d2c73fc7ce22..e8577369dc8b 100644
--- a/arch/arm/boards/nxp-imx8mq-evk/ddrphy_train.c
+++ b/arch/arm/boards/nxp-imx8mq-evk/ddrphy_train.c
@@ -11,6 +11,8 @@
void ddr_cfg_phy(void) {
unsigned int tmp, tmp_t;
+ ddr_get_firmware(DRAM_TYPE_LPDDR4);
+
//Init DDRPHY register...
reg32_write(0x3c080440,0x2);
reg32_write(0x3c080444,0x3);
--
2.38.1
Re: [PATCH v2 3/5] ARM: socfpga: achilles: use ENTRY_FUNCTION_WITHSTACK
Am Freitag, dem 08.07.2022 um 08:24 +0200 schrieb Steffen Trumtrar:
> From: Steffen Trumtrar
>
> Use the newer function ENTRY_FUNCTION_WITHSTACK.
>
> Signed-off-by: Steffen Trumtrar
> ---
> arch/arm/boards/reflex-achilles/lowlevel.c | 15 ++-
> 1 file changed, 6 insertions(+), 9 deletions(-)
>
> diff --git a/arch/arm/boards/reflex-achilles/lowlevel.c
> b/arch/arm/boards/reflex-achilles/lowlevel.c
> index 162cd58c58..0fc94fc2b1 100644
> --- a/arch/arm/boards/reflex-achilles/lowlevel.c
> +++ b/arch/arm/boards/reflex-achilles/lowlevel.c
> @@ -31,12 +31,16 @@
>
> extern char __dtb_z_socfpga_arria10_achilles_start[];
>
> -static noinline void achilles_start(void)
> +#define ARRIA10_STACKTOP ARRIA10_OCRAM_ADDR + SZ_256K
> +
> +ENTRY_FUNCTION_WITHSTACK(start_socfpga_achilles_xload, ARRIA10_STACKTOP, r0,
> r1, r2)
> {
> int pbl_index = 0;
> int barebox = 0;
> int bitstream = 0;
>
> + arm_cpu_lowlevel_init();
Drive-by comment, as I've spotted it in the context of this patch: the
Arria10 CPU is a Cortex A9, which has quite a few known errata, some of
which need to be worked around in the bootloader. You might want to
consider adding a SoC specific cpu lowlevel init function, like the
ones for i.MX6 and Zynq, to apply the relevant workarounds.
Regards,
Lucas
> + arm_setup_stack(ARRIA10_OCRAM_ADDR + SZ_256K);
>
> relocate_to_current_adr();
> setup_c();
> @@ -75,13 +79,6 @@ static noinline void achilles_start(void)
> arria10_start_image(barebox);
> }
>
> -ENTRY_FUNCTION(start_socfpga_achilles_xload, r0, r1, r2)
> -{
> - arm_cpu_lowlevel_init();
> - arm_setup_stack(ARRIA10_OCRAM_ADDR + SZ_256K);
> - achilles_start();
> -}
> -
> ENTRY_FUNCTION(start_socfpga_achilles, r0, r1, r2)
> {
> void *fdt;
> @@ -91,7 +88,7 @@ ENTRY_FUNCTION(start_socfpga_achilles, r0, r1, r2)
> barebox_arm_entry(0x0, SZ_2G + SZ_1G, fdt);
> }
>
> -ENTRY_FUNCTION(start_socfpga_achilles_bringup, r0, r1, r2)
> +ENTRY_FUNCTION_WITHSTACK(start_socfpga_achilles_bringup, ARRIA10_STACKTOP,
> r0, r1, r2)
> {
> void *fdt;
>
Re: [PATCH v2] ARM: i.MX8MP: adapt atf bl31 base addr
Am Montag, dem 04.07.2022 um 16:27 +0200 schrieb Marco Felsch:
> The usptream TF-A was shifting around the base address from version to
> version. But finally with upstream TF-A v2.7 it is correctly set to
> 0x97. This change was done since the first official silicon has an
> SRAM size of 576KB where as the tapeout version A1 (pre-silicion) had
> only 512KB.
Now this doesn't match the commit message in the TF-A, which claims
that tapeout A0 (pre-release silicon) had 512K SRAM, while it was
extended to 576KB in the A1 tapeout, which is the current mass produced
version.
>
> The upstream TF-A has adapt it in verion v2.5 so the BL31 blob is at the
^ adapted ^version
> end of the SRAM. Unfortunately they had (accidental) reverted back to
Who is they? "Unfortunately it was reverted back..."
> 0x96 in v2.6. They noticed that and changed (again) back to 0x97.
> with v2.7.
>
> This commit also adapts the documentation for the i.MX8MP-EVK to
> reference the upstream TF-A. The new warning should point out that we
> strongly recommended to use versions from v2.7 onwards, due to the
^ recommend
> version mess explained above.
>
> Signed-off-by: Marco Felsch
> ---
> Changelog:
>
> v2:
> - fix commit message ger/eng mixup and mention tapeout version A1
>
> Documentation/boards/imx/nxp-imx8mp-evk.rst | 11 +++
> arch/arm/mach-imx/include/mach/atf.h| 2 +-
> 2 files changed, 8 insertions(+), 5 deletions(-)
>
> diff --git a/Documentation/boards/imx/nxp-imx8mp-evk.rst
> b/Documentation/boards/imx/nxp-imx8mp-evk.rst
> index 366c1de500..1074992f2f 100644
> --- a/Documentation/boards/imx/nxp-imx8mp-evk.rst
> +++ b/Documentation/boards/imx/nxp-imx8mp-evk.rst
> @@ -40,15 +40,18 @@ As a last step of this process those files need to be
> placed in
> firmware/${f}; \
>done
>
> -Get and Build the ARM Trusted firmware
> ---
> +Get and Build the Trusted Firmware A
> +
>
> -Get ATF from https://source.codeaurora.org/external/imx/imx-atf, branch
> -imx_5.4.3_2.0.0::
> +Get TF-A from https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/
> and
> +checkout version v2.7::
>
>make PLAT=imx8mp bl31
>cp build/imx8mp/release/bl31.bin ${barebox_srctree}/imx8mp-bl31.bin
>
> +.. warning:: It is important to use a version >= v2.7 else your system
> + might not boot.
This doesn't tell anyone what's going on, I think we can bother the
reader with the details: "It is important to use a version >= v2.7, as
Barebox expects the BL31 SRAM load address used from this release
onwards."
> +
> Build Barebox
> -
>
> diff --git a/arch/arm/mach-imx/include/mach/atf.h
> b/arch/arm/mach-imx/include/mach/atf.h
> index 09396f4646..bc400ddbad 100644
> --- a/arch/arm/mach-imx/include/mach/atf.h
> +++ b/arch/arm/mach-imx/include/mach/atf.h
> @@ -10,7 +10,7 @@
>
> #define MX8MM_ATF_BL31_BASE_ADDR 0x0092
> #define MX8MN_ATF_BL31_BASE_ADDR 0x0096
> -#define MX8MP_ATF_BL31_BASE_ADDR 0x0096
> +#define MX8MP_ATF_BL31_BASE_ADDR 0x0097
> #define MX8MQ_ATF_BL31_BASE_ADDR 0x0091
> #define MX8M_ATF_BL33_BASE_ADDR 0x4020
> #define MX8MM_ATF_BL33_BASE_ADDR MX8M_ATF_BL33_BASE_ADDR
Re: [PATCH] ARM: i.MX8MP: adapt atf bl31 base addr
Am Montag, dem 04.07.2022 um 14:33 +0200 schrieb Marco Felsch:
> The usptream TF-A was shifting around the base address from version to
> version. But finally with upstream TF-A v2.7 it is correctly set to
> 0x97. This change was done since the final silicium has an SRAM size
^ silicon
> of 576KB where as the pre-silicium had only 512KB.
Please specify the tapeout version (A1) here.
pre-silicon is a very different thing than a pre-release tapeout.
>
> The upstream TF-A has adapt it in verion v2.5 so the BL31 blob is at the
> end of the SRAM. Unfortunately they had (accidental) reverted back to
> 0x96 in v2.6. They noticed that and changed (again) back to 0x97.
> with v2.7.
>
> This commit also adapts the documentation for the i.MX8MP-EVK to
> reference the upstream TF-A. The new warning should point out that we
> strongly recommended to use versions from v2.7 onwards, due to the
> version mess explained above.
>
> Signed-off-by: Marco Felsch
> ---
> Documentation/boards/imx/nxp-imx8mp-evk.rst | 11 +++
> arch/arm/mach-imx/include/mach/atf.h| 2 +-
> 2 files changed, 8 insertions(+), 5 deletions(-)
>
> diff --git a/Documentation/boards/imx/nxp-imx8mp-evk.rst
> b/Documentation/boards/imx/nxp-imx8mp-evk.rst
> index 366c1de500..1074992f2f 100644
> --- a/Documentation/boards/imx/nxp-imx8mp-evk.rst
> +++ b/Documentation/boards/imx/nxp-imx8mp-evk.rst
> @@ -40,15 +40,18 @@ As a last step of this process those files need to be
> placed in
> firmware/${f}; \
>done
>
> -Get and Build the ARM Trusted firmware
> ---
> +Get and Build the Trusted Firmware A
> +
>
> -Get ATF from https://source.codeaurora.org/external/imx/imx-atf, branch
> -imx_5.4.3_2.0.0::
> +Get TF-A from https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/
> and
> +checkout version v2.7::
>
>make PLAT=imx8mp bl31
>cp build/imx8mp/release/bl31.bin ${barebox_srctree}/imx8mp-bl31.bin
>
> +.. warning:: It is important to use a version >= v2.7 else your system
> + might not boot.
> +
> Build Barebox
> -
>
> diff --git a/arch/arm/mach-imx/include/mach/atf.h
> b/arch/arm/mach-imx/include/mach/atf.h
> index 09396f4646..bc400ddbad 100644
> --- a/arch/arm/mach-imx/include/mach/atf.h
> +++ b/arch/arm/mach-imx/include/mach/atf.h
> @@ -10,7 +10,7 @@
>
> #define MX8MM_ATF_BL31_BASE_ADDR 0x0092
> #define MX8MN_ATF_BL31_BASE_ADDR 0x0096
> -#define MX8MP_ATF_BL31_BASE_ADDR 0x0096
> +#define MX8MP_ATF_BL31_BASE_ADDR 0x0097
> #define MX8MQ_ATF_BL31_BASE_ADDR 0x0091
> #define MX8M_ATF_BL33_BASE_ADDR 0x4020
> #define MX8MM_ATF_BL33_BASE_ADDR MX8M_ATF_BL33_BASE_ADDR
[PATCH 1/2] arm: imx8mq: re-enable DDRC for Barebox
With Linux 5.18 the DDRC is disabled for most boards in the upstream
DT, as it isn't used. Barebox however needs the DDRC node to be enabled
as it has a driver to read the memory size from the controller and ends
up with no available RAM without this driver being present.
Signed-off-by: Lucas Stach
---
arch/arm/dts/imx8mq-ddrc.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/imx8mq-ddrc.dtsi b/arch/arm/dts/imx8mq-ddrc.dtsi
index 1df39151a1cd..6961477eef38 100644
--- a/arch/arm/dts/imx8mq-ddrc.dtsi
+++ b/arch/arm/dts/imx8mq-ddrc.dtsi
@@ -8,3 +8,7 @@
/delete-node/ memory@4000;
};
+&ddrc {
+ status = "okay";
+};
+
--
2.36.1
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[PATCH 2/2] ARM: mnt-reform: switch to upstream DT
Now that all the necessary bits are upstream, we drop most of
the Barebox DT for this board.
Signed-off-by: Lucas Stach
---
arch/arm/dts/imx8mq-mnt-reform2.dts | 164 +---
1 file changed, 1 insertion(+), 163 deletions(-)
diff --git a/arch/arm/dts/imx8mq-mnt-reform2.dts
b/arch/arm/dts/imx8mq-mnt-reform2.dts
index 5a65324b3c75..deb31abe5414 100644
--- a/arch/arm/dts/imx8mq-mnt-reform2.dts
+++ b/arch/arm/dts/imx8mq-mnt-reform2.dts
@@ -6,17 +6,12 @@
/dts-v1/;
-#include
+#include
#include "imx8mq.dtsi"
#include "imx8mq-ddrc.dtsi"
/ {
- model = "MNT Reform2";
- compatible = "mntre,reform2", "fsl,imx8mq";
-
chosen {
- stdout-path = &uart1;
-
environment-emmc {
compatible = "barebox,environment";
device-path = &usdhc1, "partname:barebox-environment";
@@ -29,86 +24,13 @@
status = "disabled";
};
};
-
- pcie1_refclk: pcie1-refclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <1>;
- };
-};
-
-&fec1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_fec1>;
- phy-mode = "rgmii-id";
- phy-handle = <ðphy0>;
- status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy0: ethernet-phy@4 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <4>;
- interrupts = <&gpio1 11 IRQ_TYPE_LEVEL_LOW>;
- reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
- };
- };
};
&ocotp {
barebox,provide-mac-address = <&fec1 0x640>;
};
-&pcie1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcie1>;
- reset-gpio = <&gpio3 23 GPIO_ACTIVE_LOW>;
- clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
-<&clk IMX8MQ_CLK_PCIE2_AUX>,
-<&clk IMX8MQ_CLK_PCIE2_PHY>,
-<&pcie1_refclk>;
- clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
- status = "okay";
-};
-
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- status = "okay";
-};
-
-&usb3_phy0 {
- status = "okay";
-};
-
-&usb3_phy1 {
- status = "okay";
-};
-
-&usb_dwc3_0 {
- status = "okay";
- dr_mode = "host";
-};
-
-&usb_dwc3_1 {
- status = "okay";
- dr_mode = "host";
-};
-
&usdhc1 {
- assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
- assigned-clock-rates = <4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc1>;
- bus-width = <8>;
- no-mmc-hs400;
- non-removable;
- no-sd;
- no-sdio;
- status = "okay";
-
#address-cells = <1>;
#size-cells = <1>;
@@ -124,14 +46,6 @@
};
&usdhc2 {
- assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
- assigned-clock-rates = <2>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc2>;
- bus-width = <4>;
- no-1-8-v;
- status = "okay";
-
#address-cells = <1>;
#size-cells = <1>;
@@ -145,79 +59,3 @@
reg = <0xe 0x2>;
};
};
-
-&wdog1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wdog>;
- fsl,ext-reset-output;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_fec1: fec1grp {
- fsl,pins = <
- MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
- MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
- MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
- MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
- MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
- MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
- MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
- MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
- MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
- MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC
[PATCH] ARM: nxp-imx8mq-evk: install Barebox into eMMC boot partitions
Switch the Barebox update handler to install Barebox in the eMMC boot
partitions, which is preferred due to the capability to do atomic
updates.
Signed-off-by: Lucas Stach
---
arch/arm/boards/nxp-imx8mq-evk/board.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boards/nxp-imx8mq-evk/board.c
b/arch/arm/boards/nxp-imx8mq-evk/board.c
index c28107cb1751..8d88bfe8c249 100644
--- a/arch/arm/boards/nxp-imx8mq-evk/board.c
+++ b/arch/arm/boards/nxp-imx8mq-evk/board.c
@@ -40,7 +40,7 @@ static int nxp_imx8mq_evk_init(void)
barebox_set_hostname("imx8mq-evk");
flags = bootsource_get_instance() == 0 ? BBU_HANDLER_FLAG_DEFAULT : 0;
- imx8m_bbu_internal_mmc_register_handler("eMMC", "/dev/mmc0.barebox",
flags);
+ imx8m_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc0", flags);
flags = bootsource_get_instance() == 1 ? BBU_HANDLER_FLAG_DEFAULT : 0;
imx8m_bbu_internal_mmc_register_handler("SD", "/dev/mmc1.barebox",
flags);
--
2.36.1
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Re: [PATCH] ARM: imx: esdctl: fix LPDDR4 size calculation
Hi Teresa,
Am Freitag, dem 20.05.2022 um 14:16 + schrieb Teresa Remmet:
> Hello Lucas,
>
> Am Freitag, dem 13.05.2022 um 16:16 +0200 schrieb Lucas Stach:
> > The DDRC only uses the DEVICE_CONFIG field for memory types other
> > than
> > LPDDR4. While LPDDR4 always has a bus width of x32, the script aid
>
> this is not true for i.MX8M Nano. This SoC has only x16. This is
> probably why reading the register worked for Joacim on imx8mn.
> So there is some more checking needed.
>
Does the 8MN really use the DEVICE_CONFIG to configure the LPDDR4 bus
to 16bit width, or does it use the DATA_BUS_WIDTH control to limit the
bus to 16bit?
The register programming aid spreadsheet for the 8MN claims that
DEVICE_CONFIG has no effect on LPDDR4 memory, same as for all other
i.M8M* variants. But then the spreadsheet may have copy-and-paste
issues. So maybe we do in fact need to know that native bus width of
controller implementation on the specific SoC to get things right for
LPDDR4?
Regards,
Lucas
> Regards,
> Teresa
>
> > generates the value for a x16 bus, as this was apparently used for
> > the
> > controller validation. This resulted in the calculated DRAM size to
> > be
> > halved on boards with LPDDR4 memory.
> >
> > Fixes: d8d5778ee8c2 ("ARM: imx: Correct mem size calculation for
> > 4/8/16/32 bit bus width")
> > Signed-off-by: Lucas Stach
> > ---
> > arch/arm/mach-imx/esdctl.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c
> > index d3dbfff423da..4c8765c193d0 100644
> > --- a/arch/arm/mach-imx/esdctl.c
> > +++ b/arch/arm/mach-imx/esdctl.c
> > @@ -392,7 +392,7 @@ imx_ddrc_sdram_size(void __iomem *ddrc, const u32
> > addrmap[],
> > }
> >
> > /* Bus width in bytes, 0 means half byte or 4-bit mode */
> > - if (is_imx8)
> > + if (is_imx8 && !(mstr & DDRC_MSTR_LPDDR4))
> > width = (1 << FIELD_GET(DDRC_MSTR_DEVICE_CONFIG, mstr))
> > > > 1;
> > else
> > width = 4;
> --
> PHYTEC Messtechnik GmbH | Robert-Koch-Str. 39 | 55129 Mainz, Germany
>
> Geschäftsführer: Dipl.-Ing. Michael Mitezki, Dipl.-Ing. Bodo Huber |
> Handelsregister Mainz HRB 4656 | Finanzamt Mainz | St.Nr. 266500608, DE
> 149059855
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[PATCH] of: address: treat absent dma-ranges as 1:1 translation
Some DTs use dma-ranges in child busses without this property being present
in the parent bus. To avoid failing the address translation, do the same as
the Linux kernel and treat absence of this property as a 1:1 translation.
Signed-off-by: Lucas Stach
---
drivers/of/address.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/of/address.c b/drivers/of/address.c
index 67e8062f5d17..4eafce376d36 100644
--- a/drivers/of/address.c
+++ b/drivers/of/address.c
@@ -301,10 +301,13 @@ static int of_translate_one(struct device_node *parent,
struct of_bus *bus,
*
* As far as we know, this damage only exists on Apple machines, so
* This code is only enabled on powerpc. --gcl
+*
+* This quirk also applies for 'dma-ranges' which frequently exist in
+* child nodes without 'dma-ranges' in the parent nodes. --RobH
*/
ranges = of_get_property(parent, rprop, &rlen);
#if !defined(CONFIG_PPC)
- if (ranges == NULL) {
+ if (ranges == NULL && strcmp(rprop, "dma-ranges")) {
pr_vdebug("OF: no ranges; cannot translate\n");
return 1;
}
--
2.35.3
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[PATCH] ARM: imx: esdctl: fix LPDDR4 size calculation
The DDRC only uses the DEVICE_CONFIG field for memory types other than
LPDDR4. While LPDDR4 always has a bus width of x32, the script aid
generates the value for a x16 bus, as this was apparently used for the
controller validation. This resulted in the calculated DRAM size to be
halved on boards with LPDDR4 memory.
Fixes: d8d5778ee8c2 ("ARM: imx: Correct mem size calculation for 4/8/16/32 bit
bus width")
Signed-off-by: Lucas Stach
---
arch/arm/mach-imx/esdctl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c
index d3dbfff423da..4c8765c193d0 100644
--- a/arch/arm/mach-imx/esdctl.c
+++ b/arch/arm/mach-imx/esdctl.c
@@ -392,7 +392,7 @@ imx_ddrc_sdram_size(void __iomem *ddrc, const u32 addrmap[],
}
/* Bus width in bytes, 0 means half byte or 4-bit mode */
- if (is_imx8)
+ if (is_imx8 && !(mstr & DDRC_MSTR_LPDDR4))
width = (1 << FIELD_GET(DDRC_MSTR_DEVICE_CONFIG, mstr)) >> 1;
else
width = 4;
--
2.35.3
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Re: [PATCH] ARM: OMAP: debug_ll: Use Kconfig UART base address
Am Donnerstag, dem 05.05.2022 um 10:36 +0300 schrieb Alexander Shiyan:
> Signed-off-by: Alexander Shiyan
Is this really a change in the right direction? The way it is currently
done seems to mix well with overall multi-image theme of Barebox. By
using a Kconfig for that, the setting will most likely be wrong for a
subset of boards in a multi-image build.
Regards,
Lucas
> ---
> arch/arm/boards/afi-gf/lowlevel.c| 2 +-
> arch/arm/boards/beagle/lowlevel.c| 2 +-
> arch/arm/boards/beaglebone/lowlevel.c| 2 +-
> arch/arm/boards/myirtech-x335x/lowlevel.c| 2 +-
> arch/arm/boards/phytec-som-am335x/lowlevel.c | 2 +-
> arch/arm/boards/vscom-baltos/lowlevel.c | 2 +-
> arch/arm/boards/wago-pfc-am35xx/lowlevel.c | 2 +-
> arch/arm/mach-omap/include/mach/debug_ll.h | 43
> 8 files changed, 33 insertions(+), 24 deletions(-)
>
> diff --git a/arch/arm/boards/afi-gf/lowlevel.c
> b/arch/arm/boards/afi-gf/lowlevel.c
> index de40f6c5af..9e86b29b2d 100644
> --- a/arch/arm/boards/afi-gf/lowlevel.c
> +++ b/arch/arm/boards/afi-gf/lowlevel.c
> @@ -230,7 +230,7 @@ static noinline int gf_sram_init(void)
>
> am33xx_uart_soft_reset((void *)AM33XX_UART2_BASE);
> am33xx_enable_uart2_pin_mux();
> - omap_uart_lowlevel_init((void *)AM33XX_UART2_BASE);
> + omap_uart_lowlevel_init();
> putc_ll('>');
>
> barebox_arm_entry(0x8000, SZ_256M, fdt);
> diff --git a/arch/arm/boards/beagle/lowlevel.c
> b/arch/arm/boards/beagle/lowlevel.c
> index 683ab552f4..c64a2114d4 100644
> --- a/arch/arm/boards/beagle/lowlevel.c
> +++ b/arch/arm/boards/beagle/lowlevel.c
> @@ -196,7 +196,7 @@ static noinline int beagle_board_init(void)
>
> mux_config();
>
> - omap_uart_lowlevel_init((void *)OMAP3_UART3_BASE);
> + omap_uart_lowlevel_init();
>
> /* Dont reconfigure SDRAM while running in SDRAM! */
> if (!in_sdram)
> diff --git a/arch/arm/boards/beaglebone/lowlevel.c
> b/arch/arm/boards/beaglebone/lowlevel.c
> index 544e396e03..365ba64a79 100644
> --- a/arch/arm/boards/beaglebone/lowlevel.c
> +++ b/arch/arm/boards/beaglebone/lowlevel.c
> @@ -139,7 +139,7 @@ static noinline int beaglebone_sram_init(void)
>
> am33xx_uart_soft_reset((void *)AM33XX_UART0_BASE);
> am33xx_enable_uart0_pin_mux();
> - omap_uart_lowlevel_init((void *)AM33XX_UART0_BASE);
> + omap_uart_lowlevel_init();
> putc_ll('>');
>
> barebox_arm_entry(0x8000, sdram_size, fdt);
> diff --git a/arch/arm/boards/myirtech-x335x/lowlevel.c
> b/arch/arm/boards/myirtech-x335x/lowlevel.c
> index 1a883da203..da47300d81 100644
> --- a/arch/arm/boards/myirtech-x335x/lowlevel.c
> +++ b/arch/arm/boards/myirtech-x335x/lowlevel.c
> @@ -98,7 +98,7 @@ ENTRY_FUNCTION(start_am33xx_myirtech_sram, bootinfo, r1, r2)
> if (IS_ENABLED(CONFIG_DEBUG_LL)) {
> am33xx_uart_soft_reset(IOMEM(AM33XX_UART0_BASE));
> am33xx_enable_uart0_pin_mux();
> - omap_uart_lowlevel_init(IOMEM(AM33XX_UART0_BASE));
> + omap_uart_lowlevel_init();
> putc_ll('>');
> }
>
> diff --git a/arch/arm/boards/phytec-som-am335x/lowlevel.c
> b/arch/arm/boards/phytec-som-am335x/lowlevel.c
> index bffb3ad880..e4f3edd211 100644
> --- a/arch/arm/boards/phytec-som-am335x/lowlevel.c
> +++ b/arch/arm/boards/phytec-som-am335x/lowlevel.c
> @@ -172,7 +172,7 @@ static noinline void physom_board_init(void *fdt, int
> sdram, int module_family)
>
> am33xx_uart_soft_reset((void *)AM33XX_UART0_BASE);
> am33xx_enable_uart0_pin_mux();
> - omap_uart_lowlevel_init((void *)AM33XX_UART0_BASE);
> + omap_uart_lowlevel_init();
> putc_ll('>');
>
> am335x_barebox_entry(fdt);
> diff --git a/arch/arm/boards/vscom-baltos/lowlevel.c
> b/arch/arm/boards/vscom-baltos/lowlevel.c
> index 7da2f92efb..2401cf20c4 100644
> --- a/arch/arm/boards/vscom-baltos/lowlevel.c
> +++ b/arch/arm/boards/vscom-baltos/lowlevel.c
> @@ -104,7 +104,7 @@ static noinline void baltos_sram_init(void)
>
> am33xx_uart_soft_reset((void *)AM33XX_UART0_BASE);
> am33xx_enable_uart0_pin_mux();
> - omap_uart_lowlevel_init((void *)AM33XX_UART0_BASE);
> + omap_uart_lowlevel_init();
> putc_ll('>');
>
> am335x_barebox_entry(fdt);
> diff --git a/arch/arm/boards/wago-pfc-am35xx/lowlevel.c
> b/arch/arm/boards/wago-pfc-am35xx/lowlevel.c
> index 7da8fd0331..6a7f350dda 100644
> --- a/arch/arm/boards/wago-pfc-am35xx/lowlevel.c
> +++ b/arch/arm/boards/wago-pfc-am35xx/lowlevel.c
> @@ -185,7 +185,7 @@ static noinline void pfc200_board_init(void)
>
> if (IS_ENABLED(CONFIG_DEBUG_LL)) {
> am33xx_uart_soft_reset(IOMEM(OMAP3_UART3_BASE));
> - omap_uart_lowlevel_init(IOMEM(OMAP3_UART3_BASE));
> + omap_uart_lowlevel_init();
> putc_ll('>');
> }
>
> diff --git a/arch/arm/mach-omap/include/mach/debug_ll.h
> b/arch/arm/mach-omap/include/mach/debu
Re: [PATCH] usb: xhci: Honor transfer timeouts
Hi Sascha,
Am Montag, dem 14.12.2020 um 14:58 +0100 schrieb Sascha Hauer:
> The usb host submit_control_msg() and submit_bulk_msg() hooks pass a
> timeout value. Honor these values in the XHCI driver instead of just
> ignoring them. The USB net driver in barebox polls for receive packets
> by submitting an URB with a very low timeout, expecting it to timeout
> when no incoming packet is present. With the default timeout of 5
> seconds the XHCI driver previously used barebox became unusable.
Seems like this patch has not been applied. USB net on a XHCI host is
still unusable with current master.
Regards,
Lucas
>
> Signed-off-by: Sascha Hauer
> ---
> drivers/usb/host/xhci-ring.c | 29 +++--
> drivers/usb/host/xhci.c | 17 +
> drivers/usb/host/xhci.h | 8 +---
> 3 files changed, 25 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
> index 61b1b55a27..76c18e4615 100644
> --- a/drivers/usb/host/xhci-ring.c
> +++ b/drivers/usb/host/xhci-ring.c
> @@ -436,7 +436,8 @@ static int event_ready(struct xhci_ctrl *ctrl)
> * @param expected TRB type expected from Event TRB
> * @return pointer to event trb
> */
> -union xhci_trb *xhci_wait_for_event(struct xhci_ctrl *ctrl, trb_type
> expected)
> +union xhci_trb *xhci_wait_for_event(struct xhci_ctrl *ctrl, trb_type
> expected,
> + unsigned int timeout_ms)
> {
> trb_type type;
> uint64_t start = get_time_ns();
> @@ -460,16 +461,8 @@ union xhci_trb *xhci_wait_for_event(struct xhci_ctrl
> *ctrl, trb_type expected)
> BUG_ON(GET_COMP_CODE(
> le32_to_cpu(event->generic.field[2])) !=
> COMP_SUCCESS);
> - else
> - dev_err(ctrl->dev, "Unexpected XHCI event TRB,
> skipping... "
> - "(%08x %08x %08x %08x)\n",
> - le32_to_cpu(event->generic.field[0]),
> - le32_to_cpu(event->generic.field[1]),
> - le32_to_cpu(event->generic.field[2]),
> - le32_to_cpu(event->generic.field[3]));
> -
> xhci_acknowledge_event(ctrl);
> - } while (!is_timeout_non_interruptible(start, 5 * SECOND));
> + } while (!is_timeout_non_interruptible(start, timeout_ms * MSECOND));
>
> if (expected == TRB_TRANSFER)
> return NULL;
> @@ -495,7 +488,7 @@ static void abort_td(struct usb_device *udev, int
> ep_index)
>
> xhci_queue_command(ctrl, NULL, udev->slot_id, ep_index, TRB_STOP_RING);
>
> - event = xhci_wait_for_event(ctrl, TRB_TRANSFER);
> + event = xhci_wait_for_event(ctrl, TRB_TRANSFER, XHCI_TIMEOUT_DEFAULT);
> field = le32_to_cpu(event->trans_event.flags);
> BUG_ON(TRB_TO_SLOT_ID(field) != udev->slot_id);
> BUG_ON(TRB_TO_EP_INDEX(field) != ep_index);
> @@ -503,7 +496,7 @@ static void abort_td(struct usb_device *udev, int
> ep_index)
> != COMP_STOP)));
> xhci_acknowledge_event(ctrl);
>
> - event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
> + event = xhci_wait_for_event(ctrl, TRB_COMPLETION, XHCI_TIMEOUT_DEFAULT);
> BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags))
> != udev->slot_id || GET_COMP_CODE(le32_to_cpu(
> event->event_cmd.status)) != COMP_SUCCESS);
> @@ -511,7 +504,7 @@ static void abort_td(struct usb_device *udev, int
> ep_index)
>
> xhci_queue_command(ctrl, (void *)((uintptr_t)ring->enqueue |
> ring->cycle_state), udev->slot_id, ep_index, TRB_SET_DEQ);
> - event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
> + event = xhci_wait_for_event(ctrl, TRB_COMPLETION, XHCI_TIMEOUT_DEFAULT);
> BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags))
> != udev->slot_id || GET_COMP_CODE(le32_to_cpu(
> event->event_cmd.status)) != COMP_SUCCESS);
> @@ -557,7 +550,7 @@ static void record_transfer_result(struct usb_device
> *udev,
> * @return returns 0 if successful else -1 on failure
> */
> int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe,
> - int length, void *buffer)
> + int length, void *buffer, unsigned int timeout_ms)
> {
> int num_trbs = 0;
> struct xhci_generic_trb *start_trb;
> @@ -726,7 +719,7 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned long
> pipe,
>
> giveback_first_trb(udev, ep_index, start_cycle, start_trb);
>
> - event = xhci_wait_for_event(ctrl, TRB_TRANSFER);
> + event = xhci_wait_for_event(ctrl, TRB_TRANSFER, timeout_ms);
> if (!event) {
> dev_dbg(&udev->dev, "XHCI bulk transfer timed out,
> aborting...\n");
> abort_td(udev, ep_index);
> @@ -767,7 +760,7 @@ int xhci_bulk_tx(struct usb_device *ude
[PATCH 2/2] usb: dwc3: of-simple: add i.MX8MP compatible
The DWC3 DT node in the i.MX8MP is contained in a wrapper node for
the glue logic. Linux uses this wrapper for wakeup handling, but we
don't need this functionality in Barebox, so we can just handle it
with the of-simple DWC3 driver.
Signed-off-by: Lucas Stach
---
drivers/usb/dwc3/dwc3-of-simple.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/usb/dwc3/dwc3-of-simple.c
b/drivers/usb/dwc3/dwc3-of-simple.c
index 1f42cde37f22..6261122a127f 100644
--- a/drivers/usb/dwc3/dwc3-of-simple.c
+++ b/drivers/usb/dwc3/dwc3-of-simple.c
@@ -68,6 +68,7 @@ static const struct of_device_id of_dwc3_simple_match[] = {
{.compatible = "rockchip,rk3399-dwc3"},
{.compatible = "xlnx,zynqmp-dwc3"},
{.compatible = "fsl,ls1046a-dwc3"},
+ {.compatible = "fsl,imx8mp-dwc3"},
{.compatible = "cavium,octeon-7130-usb-uctl"},
{.compatible = "sprd,sc9860-dwc3"},
{.compatible = "amlogic,meson-axg-dwc3"},
--
2.34.1
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[PATCH 1/2] phy: freescale: imx8mq-usb: add support for i.MX8MP PHY
This is a port of the Linux kernel commit 4708ee37826e
by Li Jun . The USB3 PHY in the i.MX8MP is very
close to the one in the i.MX8MQ and just needs a different setup
routine.
Signed-off-by: Lucas Stach
---
drivers/phy/freescale/phy-fsl-imx8mq-usb.c | 87 ++
1 file changed, 74 insertions(+), 13 deletions(-)
diff --git a/drivers/phy/freescale/phy-fsl-imx8mq-usb.c
b/drivers/phy/freescale/phy-fsl-imx8mq-usb.c
index d3f9c1ba6ecf..fc5fb006b56c 100644
--- a/drivers/phy/freescale/phy-fsl-imx8mq-usb.c
+++ b/drivers/phy/freescale/phy-fsl-imx8mq-usb.c
@@ -2,20 +2,24 @@
/* Copyright (c) 2017 NXP. */
#include
+#include
+#include
#include
#include
-#include
-#include
-#include
-#include
-#include
-#include
+#include
#include
#include
+#include
+#include
+#include
+#include
+#include
#define PHY_CTRL0 0x0
#define PHY_CTRL0_REF_SSP_EN BIT(2)
+#define PHY_CTRL0_FSEL_MASKGENMASK(10, 5)
+#define PHY_CTRL0_FSEL_24M 0x2a
#define PHY_CTRL1 0x4
#define PHY_CTRL1_RESETBIT(0)
@@ -26,6 +30,11 @@
#define PHY_CTRL2 0x8
#define PHY_CTRL2_TXENABLEN0 BIT(8)
+#define PHY_CTRL2_OTG_DISABLE BIT(9)
+
+#define PHY_CTRL6 0x18
+#define PHY_CTRL6_ALT_CLK_EN BIT(1)
+#define PHY_CTRL6_ALT_CLK_SEL BIT(0)
struct imx8mq_usb_phy {
struct phy *phy;
@@ -59,6 +68,44 @@ static int imx8mq_usb_phy_init(struct phy *phy)
return 0;
}
+static int imx8mp_usb_phy_init(struct phy *phy)
+{
+ struct imx8mq_usb_phy *imx_phy = phy_get_drvdata(phy);
+ u32 value;
+
+ /* USB3.0 PHY signal fsel for 24M ref */
+ value = readl(imx_phy->base + PHY_CTRL0);
+ value &= ~PHY_CTRL0_FSEL_MASK;
+ value |= FIELD_PREP(PHY_CTRL0_FSEL_MASK, PHY_CTRL0_FSEL_24M);
+ writel(value, imx_phy->base + PHY_CTRL0);
+
+ /* Disable alt_clk_en and use internal MPLL clocks */
+ value = readl(imx_phy->base + PHY_CTRL6);
+ value &= ~(PHY_CTRL6_ALT_CLK_SEL | PHY_CTRL6_ALT_CLK_EN);
+ writel(value, imx_phy->base + PHY_CTRL6);
+
+ value = readl(imx_phy->base + PHY_CTRL1);
+ value &= ~(PHY_CTRL1_VDATSRCENB0 | PHY_CTRL1_VDATDETENB0);
+ value |= PHY_CTRL1_RESET | PHY_CTRL1_ATERESET;
+ writel(value, imx_phy->base + PHY_CTRL1);
+
+ value = readl(imx_phy->base + PHY_CTRL0);
+ value |= PHY_CTRL0_REF_SSP_EN;
+ writel(value, imx_phy->base + PHY_CTRL0);
+
+ value = readl(imx_phy->base + PHY_CTRL2);
+ value |= PHY_CTRL2_TXENABLEN0 | PHY_CTRL2_OTG_DISABLE;
+ writel(value, imx_phy->base + PHY_CTRL2);
+
+ udelay(10);
+
+ value = readl(imx_phy->base + PHY_CTRL1);
+ value &= ~(PHY_CTRL1_RESET | PHY_CTRL1_ATERESET);
+ writel(value, imx_phy->base + PHY_CTRL1);
+
+ return 0;
+}
+
static int imx8mq_phy_power_on(struct phy *phy)
{
struct imx8mq_usb_phy *imx_phy = phy_get_drvdata(phy);
@@ -75,12 +122,26 @@ static int imx8mq_phy_power_off(struct phy *phy)
return 0;
}
-static struct phy_ops imx8mq_usb_phy_ops = {
+static const struct phy_ops imx8mq_usb_phy_ops = {
.init = imx8mq_usb_phy_init,
.power_on = imx8mq_phy_power_on,
.power_off = imx8mq_phy_power_off,
};
+static const struct phy_ops imx8mp_usb_phy_ops = {
+ .init = imx8mp_usb_phy_init,
+ .power_on = imx8mq_phy_power_on,
+ .power_off = imx8mq_phy_power_off,
+};
+
+static const struct of_device_id imx8mq_usb_phy_of_match[] = {
+ {.compatible = "fsl,imx8mq-usb-phy",
+.data = &imx8mq_usb_phy_ops,},
+ {.compatible = "fsl,imx8mp-usb-phy",
+.data = &imx8mp_usb_phy_ops,},
+ { }
+};
+
static struct phy *imx8mq_usb_phy_xlate(struct device_d *dev,
struct of_phandle_args *args)
{
@@ -93,6 +154,7 @@ static int imx8mq_usb_phy_probe(struct device_d *dev)
{
struct phy_provider *phy_provider;
struct imx8mq_usb_phy *imx_phy;
+ const struct phy_ops *phy_ops;
imx_phy = xzalloc(sizeof(*imx_phy));
@@ -106,7 +168,11 @@ static int imx8mq_usb_phy_probe(struct device_d *dev)
if (IS_ERR(imx_phy->base))
return PTR_ERR(imx_phy->base);
- imx_phy->phy = phy_create(dev, NULL, &imx8mq_usb_phy_ops);
+ phy_ops = of_device_get_match_data(dev);
+ if (!phy_ops)
+ return -EINVAL;
+
+ imx_phy->phy = phy_create(dev, NULL, phy_ops);
if (IS_ERR(imx_phy->phy))
return PTR_ERR(imx_phy->phy);
@@ -117,11 +183,6 @@ static int imx8mq_usb_phy_probe(struct device_d *dev)
return PTR_ERR_OR_ZERO(phy_provider);
}
-static const struct of_device_id imx8mq_usb_phy_of_match[] = {
- {
Re: [PATCH 1/3] clk: ignore of_device_ensure_probed error in clock lookup
Hi Ahmad,
Am Montag, dem 17.01.2022 um 06:12 +0100 schrieb Ahmad Fatoum:
> Hello Lucas,
>
> On 16.01.22 22:32, Lucas Stach wrote:
> > For CLK_OF_DECLARE clocks there is no driver that is bound to the device,
> > so the lookup fails before even trying to find the provider, breaking
> > the parent_ready() logic used when initializing the declared providers.
> >
> > Ignore the return code from of_device_ensure_probed to allow the lookup
> > to proceed as usual. If of_device_ensure_probed the lookup will also fail,
> > as no provider will be found.
>
> This seems to be an alternate fix for the issue addressed by:
> bd516e38dd14 ("clk: handle CLK_OF_DECLARE in deep probe")
>
> What do you think?
Yes, it seems to be aimed at the same issue. However, your fix in
bd516e38dd14 doesn't fix my specific issue, as we still don't get the
correct -EPROBE_DEFER error code for the logic in parent_ready() in
drivers/clk/clk.c to work.
I guess we could even revert your fix if we agree that ignoring the
return code here is the right thing to do? Attaching a dummy driver
doesn't seem to be totally correct, as I think it isn't prohibited to
have both a CLK_OF_DECLARE clock controller and a real platform driver
for other uses attached to the same OF node. While I'm not aware of any
clock controllers where this would be the case, I have seen such
constructs with IRQ controllers.
Regards,
Lucas
>
> >
> > Signed-off-by: Lucas Stach
> > ---
> > drivers/clk/clk.c | 6 ++
> > 1 file changed, 2 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> > index 189c9c62df5c..a1d1d7f1a467 100644
> > --- a/drivers/clk/clk.c
> > +++ b/drivers/clk/clk.c
> > @@ -643,11 +643,9 @@ struct clk *of_clk_get_from_provider(struct
> > of_phandle_args *clkspec)
> > {
> > struct of_clk_provider *provider;
> > struct clk *clk = ERR_PTR(-EPROBE_DEFER);
> > - int ret;
> >
> > - ret = of_device_ensure_probed(clkspec->np);
> > - if (ret)
> > - return ERR_PTR(ret);
> > + /* Ignore error, as CLK_OF_DECLARE clocks have no proper driver. */
> > + of_device_ensure_probed(clkspec->np);
> >
> > /* Check if we have such a provider in our array */
> > list_for_each_entry(provider, &of_clk_providers, link) {
> >
>
>
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[PATCH 3/3] ARM: mnt-reform: switch to deep-probe
Now that all drivers used on this platform properly handle deep-probe,
we can switch it on.
Signed-off-by: Lucas Stach
---
arch/arm/boards/mnt-reform/board.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boards/mnt-reform/board.c
b/arch/arm/boards/mnt-reform/board.c
index feb874c0a0ef..010690ecbd6c 100644
--- a/arch/arm/boards/mnt-reform/board.c
+++ b/arch/arm/boards/mnt-reform/board.c
@@ -5,6 +5,7 @@
#include
#include
+#include
#include
#include
@@ -31,6 +32,7 @@ static const struct of_device_id mnt_reform_of_match[] = {
{ .compatible = "mntre,reform2"},
{ /* sentinel */ },
};
+BAREBOX_DEEP_PROBE_ENABLE(mnt_reform_of_match);
static struct driver_d mnt_reform_board_driver = {
.name = "board-mnt-reform",
--
2.31.1
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[PATCH 1/3] clk: ignore of_device_ensure_probed error in clock lookup
For CLK_OF_DECLARE clocks there is no driver that is bound to the device,
so the lookup fails before even trying to find the provider, breaking
the parent_ready() logic used when initializing the declared providers.
Ignore the return code from of_device_ensure_probed to allow the lookup
to proceed as usual. If of_device_ensure_probed the lookup will also fail,
as no provider will be found.
Signed-off-by: Lucas Stach
---
drivers/clk/clk.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 189c9c62df5c..a1d1d7f1a467 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -643,11 +643,9 @@ struct clk *of_clk_get_from_provider(struct
of_phandle_args *clkspec)
{
struct of_clk_provider *provider;
struct clk *clk = ERR_PTR(-EPROBE_DEFER);
- int ret;
- ret = of_device_ensure_probed(clkspec->np);
- if (ret)
- return ERR_PTR(ret);
+ /* Ignore error, as CLK_OF_DECLARE clocks have no proper driver. */
+ of_device_ensure_probed(clkspec->np);
/* Check if we have such a provider in our array */
list_for_each_entry(provider, &of_clk_providers, link) {
--
2.31.1
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[PATCH 2/3] soc: imx: gpcv2: split PGC domain probe in two passes
Currently it is possible that the platform device for a nested PGC
domain is added before the parent PGC device is there, which leads to
-EPROBE_DEFER when probing the driver. With normal probe this isn't
an issue, as the probe will be retried. With deep-probe this is fatal,
as the PGC domain devices aren't probed from DT, but via registration
of platform devices from the GPC driver, so the usual deep-probe
approach to ensure the devices are probed before the lookup isn't
working in this case.
Make sure to register the PGC domain platform devices in the correct
order to avoid the EPROBE_DEFER altogether.
Signed-off-by: Lucas Stach
---
drivers/soc/imx/gpcv2.c | 22 --
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index bc373ecf40cc..8abeb15d0378 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -429,7 +429,7 @@ static int imx_gpcv2_probe(struct device_d *dev)
struct device_node *pgc_np, *np;
struct resource *res;
void __iomem *base;
- int ret;
+ int ret, pass = 0;
pgc_np = of_get_child_by_name(dev->device_node, "pgc");
if (!pgc_np) {
@@ -445,10 +445,23 @@ static int imx_gpcv2_probe(struct device_d *dev)
domain_data = of_device_get_match_data(dev);
+ /*
+* Run two passes for the registration of the PGC domain platform
+* devices: first all devices that are not part of a power-domain
+* themselves, then all the others. This avoids -EPROBE_DEFER being
+* returned for nested domains, that need their parent PGC domains
+* to be present on probe.
+*/
+again:
for_each_child_of_node(pgc_np, np) {
- struct device_d *pd_dev;
+ bool child_domain = of_property_read_bool(np, "power-domains");
struct imx_pgc_domain *domain;
+ struct device_d *pd_dev;
u32 domain_index;
+
+ if ((pass == 0 && child_domain) || (pass == 1 && !child_domain))
+ continue;
+
ret = of_property_read_u32(np, "reg", &domain_index);
if (ret) {
dev_err(dev, "Failed to read 'reg' property\n");
@@ -481,6 +494,11 @@ static int imx_gpcv2_probe(struct device_d *dev)
return ret;
}
+ if (pass == 0) {
+ pass++;
+ goto again;
+ }
+
return 0;
}
--
2.31.1
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Re: [PATCH v1 8/8] ifup: optimize net boot time for USB ethernet adapters
Am Donnerstag, dem 09.09.2021 um 12:24 +0200 schrieb Oleksij Rempel:
> Am 09.09.21 um 11:28 schrieb Lucas Stach:
> > Am Donnerstag, dem 09.09.2021 um 11:13 +0200 schrieb Oleksij Rempel:
> > > On some boards, forcing detection of all device will take noticeable more
> > > time. To reduce this time, we need to scan only for USB devices.
> > >
> > > So, provide option do ifup by forcing only USB scan.
> >
> > Why is this force detection even necessary? Is there a reason you can't
> > just put a eth-discover script in /env/network/ in the defaultenv of
> > this board to do the right thing when Barebox tries to bring up the
> > network interfaces?
>
> This is board specific decision. The flag which indicate if board should
> do this is provided by the board code. So, if board code should set some
> flags anyway, why not to interpret this flags by some common code aswell?
>
A force detect should never be necessary for any board to bring up the
interfaces needed for a standard boot target. The force detection is
something you would do manually when hacking on a board.
You can still make the USB scan conditional on some board specifics,
like the status of the eth0 interface, in the discover script.
Regards,
Lucas
> > Regards,
> > Lucas
> >
> > >
> > > Signed-off-by: Oleksij Rempel
> > > ---
> > > Documentation/user/networking.rst | 3 +++
> > > arch/arm/boards/skov-imx6/board.c | 2 +-
> > > include/net.h | 1 +
> > > net/ifup.c| 16 ++--
> > > 4 files changed, 19 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/Documentation/user/networking.rst
> > > b/Documentation/user/networking.rst
> > > index 9231ebde56..18936ff169 100644
> > > --- a/Documentation/user/networking.rst
> > > +++ b/Documentation/user/networking.rst
> > > @@ -55,6 +55,9 @@ device:
> > > | | | detected automatically
> > > during start (i.e. for |
> > > | | | USB network adapters)
> > > |
> > >
> > > +--+--++
> > > +| global.net.ifup_detect_usb | boolean | Set to true if you use
> > > USB network adapter |
> > > +| | | and
> > > global.net.ifup_force_detect is too slow. |
> > > ++--+--++
> > >
> > > The first step for networking is configuring the network device. The
> > > network
> > > device is usually ``eth0``. The current configuration can be viewed with
> > > the
> > > diff --git a/arch/arm/boards/skov-imx6/board.c
> > > b/arch/arm/boards/skov-imx6/board.c
> > > index 9a32e68f21..bd00c16157 100644
> > > --- a/arch/arm/boards/skov-imx6/board.c
> > > +++ b/arch/arm/boards/skov-imx6/board.c
> > > @@ -626,7 +626,7 @@ no_switch:
> > > pr_warn("Can't disable eth0\n");
> > > }
> > >
> > > - globalvar_set("net.ifup_force_detect", "true");
> > > + globalvar_set("net.ifup_detect_usb", "true");
> > >
> > > return 0;
> > > }
> > > diff --git a/include/net.h b/include/net.h
> > > index aad28e4f4c..15cd921f56 100644
> > > --- a/include/net.h
> > > +++ b/include/net.h
> > > @@ -488,6 +488,7 @@ int net_icmp_send(struct net_connection *con, int
> > > len);
> > > void led_trigger_network(enum led_trigger trigger);
> > >
> > > #define IFUP_FLAG_FORCE (1 << 0)
> > > +#define IFUP_FLAG_USB(1 << 1)
> > >
> > > int ifup_edev(struct eth_device *edev, unsigned flags);
> > > int ifup(const char *name, unsigned flags);
> > > diff --git a/net/ifup.c b/net/ifup.c
> > > index 1870f74017..5cb2b52716 100644
> > > --- a/net/ifup.c
> > > +++ b/net/ifup.c
> > > @@ -20,6 +20,7 @@
> > > #include
> > > #include
> > > #include
> > > +#include
> > >
> > > static int eth_discover(char *file)
> > > {
> > > @@ -260,6 +261,7 @@ int ifdown(const char *ethname)
> > > }
> > >
> > > static int net_ifup_force_detect;
> > > +static int net_ifup_detect_usb;
> > &g
Re: [PATCH v1 8/8] ifup: optimize net boot time for USB ethernet adapters
Am Donnerstag, dem 09.09.2021 um 11:13 +0200 schrieb Oleksij Rempel:
> On some boards, forcing detection of all device will take noticeable more
> time. To reduce this time, we need to scan only for USB devices.
>
> So, provide option do ifup by forcing only USB scan.
Why is this force detection even necessary? Is there a reason you can't
just put a eth-discover script in /env/network/ in the defaultenv of
this board to do the right thing when Barebox tries to bring up the
network interfaces?
Regards,
Lucas
>
> Signed-off-by: Oleksij Rempel
> ---
> Documentation/user/networking.rst | 3 +++
> arch/arm/boards/skov-imx6/board.c | 2 +-
> include/net.h | 1 +
> net/ifup.c| 16 ++--
> 4 files changed, 19 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/user/networking.rst
> b/Documentation/user/networking.rst
> index 9231ebde56..18936ff169 100644
> --- a/Documentation/user/networking.rst
> +++ b/Documentation/user/networking.rst
> @@ -55,6 +55,9 @@ device:
> | | | detected automatically
> during start (i.e. for |
> | | | USB network adapters)
> |
>
> +--+--++
> +| global.net.ifup_detect_usb | boolean | Set to true if you use USB
> network adapter |
> +| | | and
> global.net.ifup_force_detect is too slow. |
> ++--+--++
>
> The first step for networking is configuring the network device. The network
> device is usually ``eth0``. The current configuration can be viewed with the
> diff --git a/arch/arm/boards/skov-imx6/board.c
> b/arch/arm/boards/skov-imx6/board.c
> index 9a32e68f21..bd00c16157 100644
> --- a/arch/arm/boards/skov-imx6/board.c
> +++ b/arch/arm/boards/skov-imx6/board.c
> @@ -626,7 +626,7 @@ no_switch:
> pr_warn("Can't disable eth0\n");
> }
>
> - globalvar_set("net.ifup_force_detect", "true");
> + globalvar_set("net.ifup_detect_usb", "true");
>
> return 0;
> }
> diff --git a/include/net.h b/include/net.h
> index aad28e4f4c..15cd921f56 100644
> --- a/include/net.h
> +++ b/include/net.h
> @@ -488,6 +488,7 @@ int net_icmp_send(struct net_connection *con, int len);
> void led_trigger_network(enum led_trigger trigger);
>
> #define IFUP_FLAG_FORCE (1 << 0)
> +#define IFUP_FLAG_USB(1 << 1)
>
> int ifup_edev(struct eth_device *edev, unsigned flags);
> int ifup(const char *name, unsigned flags);
> diff --git a/net/ifup.c b/net/ifup.c
> index 1870f74017..5cb2b52716 100644
> --- a/net/ifup.c
> +++ b/net/ifup.c
> @@ -20,6 +20,7 @@
> #include
> #include
> #include
> +#include
>
> static int eth_discover(char *file)
> {
> @@ -260,6 +261,7 @@ int ifdown(const char *ethname)
> }
>
> static int net_ifup_force_detect;
> +static int net_ifup_detect_usb;
>
> int ifup_all(unsigned flags)
> {
> @@ -282,6 +284,9 @@ int ifup_all(unsigned flags)
>
> closedir(dir);
>
> + if ((flags & IFUP_FLAG_USB) || net_ifup_detect_usb)
> + usb_rescan();
> +
> if ((flags & IFUP_FLAG_FORCE) || net_ifup_force_detect ||
> list_empty(&netdev_list))
> device_detect_all();
> @@ -303,6 +308,7 @@ void ifdown_all(void)
> static int ifup_all_init(void)
> {
> globalvar_add_simple_bool("net.ifup_force_detect",
> &net_ifup_force_detect);
> + globalvar_add_simple_bool("net.ifup_detect_usb", &net_ifup_detect_usb);
>
> return 0;
> }
> @@ -310,6 +316,8 @@ late_initcall(ifup_all_init);
>
> BAREBOX_MAGICVAR(global.net.ifup_force_detect,
> "net: force detection of devices on ifup -a");
> +BAREBOX_MAGICVAR(global.net.ifup_detect_usb,
> + "net: scan usb without forcing detection of all devices on
> ifup -a");
>
> #if IS_ENABLED(CONFIG_NET_CMD_IFUP)
>
> @@ -319,11 +327,14 @@ static int do_ifup(int argc, char *argv[])
> unsigned flags = 0;
> int all = 0;
>
> - while ((opt = getopt(argc, argv, "af")) > 0) {
> + while ((opt = getopt(argc, argv, "afu")) > 0) {
> switch (opt) {
> case 'f':
> flags |= IFUP_FLAG_FORCE;
> break;
> + case 'u':
> + flags |= IFUP_FLAG_USB;
> + break;
> case 'a':
> all = 1;
> break;
> @@ -348,12 +359,13 @@ BAREBOX_CMD_HELP_TEXT("")
> BAREBOX_CMD_HELP_TEXT("Options:")
> BAREBOX_CMD_HELP_OPT ("-a", "bring up all interfaces")
> BAREBOX_CMD_HELP_OPT ("-f", "Force. Configure even if ip already set")
> +BAREBOX_CMD_HELP_OPT ("-u", "Probe USB ")
> BAREBOX_CMD_HELP_END
>
> BAREBOX_CMD_START(ifup)
>
Re: [PATCH 3/3] firmware: zynqmp-fpga: do not use DMA coherent memory for bitstream
Am Mittwoch, dem 18.08.2021 um 15:35 +0200 schrieb Michael Tretter:
> Trying to do unaligned access of coherent memory on AArch64 will lead to
> an abort. This can happen when the FPGA loader copies the bitstream to
> the temporary buffer for the transfer to the FPGA.
>
> Convert the driver to use regular memory for the temporary buffer to
> prevent the issue.
>
> Signed-off-by: Michael Tretter
> ---
> drivers/firmware/zynqmp-fpga.c | 20 +---
> 1 file changed, 13 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/firmware/zynqmp-fpga.c b/drivers/firmware/zynqmp-fpga.c
> index 667910479aa7..0a0e7e880849 100644
> --- a/drivers/firmware/zynqmp-fpga.c
> +++ b/drivers/firmware/zynqmp-fpga.c
> @@ -203,7 +203,7 @@ static int fpgamgr_program_finish(struct firmware_handler
> *fh)
> size_t body_length;
> int header_length = 0;
> enum xilinx_byte_order byte_order;
> - u64 addr;
> + dma_addr_t addr;
> int status = 0;
> u8 flags = ZYNQMP_FPGA_BIT_ONLY_BIN;
>
> @@ -240,13 +240,19 @@ static int fpgamgr_program_finish(struct
> firmware_handler *fh)
>* memory. Allocate some extra space at the end of the buffer for the
>* bitstream size.
>*/
> - buf_aligned = dma_alloc_coherent(body_length + sizeof(buf_size),
> - DMA_ADDRESS_BROKEN);
> + buf_aligned = dma_alloc(body_length + sizeof(u32));
> if (!buf_aligned) {
> status = -ENOBUFS;
> goto err_free;
> }
>
> + addr = dma_map_single(&mgr->dev, buf_aligned,
> + body_length + sizeof(u32), DMA_TO_DEVICE);
> + if (dma_mapping_error(&mgr->dev, addr)) {
> + status = -EFAULT;
> + goto err_free;
> + }
> +
Usage of both dma_map_single and explicit dma_sync_single_for_* for a
single transfer looks odd. dma_map_single already does the cache sync,
which you then do a second time in the sync calls.
Instead you should move this dma_map_single call to the place where you
added the dma_sync_single_for_device and replace the
dma_sync_single_for_cpu with a dma_unmap_single.
Regards,
Lucas
> if (!(mgr->features & ZYNQMP_PM_FEATURE_BYTE_ORDER_IRREL) &&
> byte_order == XILINX_BYTE_ORDER_BIN)
> copy_words_swapped((u32 *)buf_aligned, body,
> @@ -254,8 +260,6 @@ static int fpgamgr_program_finish(struct firmware_handler
> *fh)
> else
> memcpy((u32 *)buf_aligned, body, body_length);
>
> - addr = (u64)buf_aligned;
> -
> if (mgr->features & ZYNQMP_PM_FEATURE_SIZE_NOT_NEEDED) {
> buf_size = body_length;
> } else {
> @@ -263,11 +267,13 @@ static int fpgamgr_program_finish(struct
> firmware_handler *fh)
> buf_size = addr + body_length;
> }
>
> - status = mgr->eemi_ops->fpga_load(addr, buf_size, flags);
> + dma_sync_single_for_device(addr, body_length + sizeof(u32),
> DMA_TO_DEVICE);
> + status = mgr->eemi_ops->fpga_load((u64)addr, buf_size, flags);
> + dma_sync_single_for_cpu(addr, body_length + sizeof(u32), DMA_TO_DEVICE);
> if (status < 0)
> dev_err(&mgr->dev, "unable to load fpga\n");
>
> - dma_free_coherent(buf_aligned, 0, body_length + sizeof(buf_size));
> + dma_free(buf_aligned);
>
> err_free:
> free(mgr->buf);
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Re: [PATCH v2 0/3] Support usb booting on i.MX8MP
Hi Uwe, Am Freitag, dem 13.08.2021 um 17:22 +0200 schrieb Uwe Kleine-König: > Hello, > > compared to (implicit) v1, the following changed here: > > - be a bit more conservative in "imx-usb-loader: Add support for >i.MX8MP" regarding last_transfer; feedback by Sascha Hauer > > - Add support in PBL to be actually booted using imx-usb-loader (only >tested the vendor U-Boot for v1), also skip the barebox header (i.e. >the first (usually) 0x8000 bytes) before the IVT header on uploadeing > > There are two things that resulted in discussions between Lucas, Ahmad > and me during development of this series: > > - On i.MX8MM and i.MX8MQ after the PBL is uploaded it's followed up by >the complete image. So the PBL is uploaded twice. The motivation for >this behaviour was that when booting from MMC loading from offset 0 >is easier because depending on the mode the hardware is in the offset >has to be specified in different ways. So to make the two modes more >similar the PBL is loaded twice for both modes. > >Here however after the PBL only the piggy data is sent because it >feels wrong for me to spend some extra effort in imx-usb-loader to do >a kludge for USB just because there are some difficulties with MMC. > >Arguments for this choice (apart from that already being completed >and tested :-) are: > >- No duplication of data that is overwritten anyhow >- Better interoperability with U-Boot/mfg-tools > While this is usually not our focus I consider it quite annoying > that there are at least three implementations of imx-usb-loader and > depending on which machine and bootloader you use you have to pick > the right implementation. With the longterm goal to have > imx-usb-loader and barebox available in Debian some > interoperability would be nice. > >I quickly tried using the boot rom load image support when booting >from SD, but it didn't work out of the box and I didn't debug that. >However I imagine that in this mode it would also be more natural to >not expect the PBL twice. > >Switching to the duplicated operation mode would make imx-usb-loader >a bit more complicated (because in the MXS code path the duplication >isn't available yet), in return we'd save an offset calculation in >the PBL. I can follow those arguments, but for the sake of the sanity of everyone involved I would vote for changing the i.MX8MM USB loading to work in the same way, maybe even using the ROM API if it works there too. i.MX8MM isn't too widely used yet, so I guess we can still change it without inflicting too much incompatibility pain. The i.MX8M* Barebox lowlevel flow is already quite delicate, so I would rather avoid having to deal with subtle differences between the various family members. > >I should be possible to look at the first post-PBL data chunk coming >in via USB and judge which mode of operation is used and behave >accordingly. If this is considered a good idea I can create a patch >for that. > > - When booting via USB the boot source is identified as "serial". I >would expect that the semantic of that is rs232 and not USB. The >source of this confusion is probably that the Reference Manual calls >the USB boot mode "USB Serial Download boot". I stuck to >BOOTSOURCE_SERIAL here for consistency. If it's not only me who would >consider using BOOTSOURCE_USB instead a fix this should be changed >consistently for all i.MX platforms. >Ahmad pointed out that this might break barebox shell scripts. This however sounds like breaking backwards compat for no real gain. As even the reference manual calls this boot mode "serial" I always found this quite clear. My vote is on keeping things as they are. Regards, Lucas > > Uwe Kleine-König (3): > imx8mp-evk: Add support for booting via USB > imx-usb-loader: Drop nearly unused struct usb_id > imx-usb-loader: Add support for i.MX8MP > > arch/arm/boards/nxp-imx8mp-evk/lowlevel.c | 27 + > arch/arm/mach-imx/boot.c | 4 +- > include/asm-generic/sections.h| 1 + > scripts/imx/imx-usb-loader.c | 131 -- > 4 files changed, 103 insertions(+), 60 deletions(-) > > > base-commit: 72424fd057d135ec0e41139fe4cb5740471d33a5 ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH v2 1/3] imx8mp-evk: Add support for booting via USB
Am Freitag, dem 13.08.2021 um 21:26 +0200 schrieb Ahmad Fatoum:
> On 13.08.21 17:22, Uwe Kleine-König wrote:
>
> S-o-b missing.
>
> > ---
> > arch/arm/boards/nxp-imx8mp-evk/lowlevel.c | 27 +++
> > arch/arm/mach-imx/boot.c | 4 +++-
> > include/asm-generic/sections.h| 1 +
> > 3 files changed, 31 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm/boards/nxp-imx8mp-evk/lowlevel.c
> > b/arch/arm/boards/nxp-imx8mp-evk/lowlevel.c
> > index 3298ded5866d..1fb7899198d6 100644
> > --- a/arch/arm/boards/nxp-imx8mp-evk/lowlevel.c
> > +++ b/arch/arm/boards/nxp-imx8mp-evk/lowlevel.c
> > @@ -99,6 +99,30 @@ static int power_init_board(void)
> > return 0;
> > }
> >
> > +/* read piggydata via a bootrom callback and place it behind our copy in
> > SDRAM */
> > +static int imx8m_bootrom_load_image(void)
> > +{
> > + int (*download_image)(u8 *dest, u32 offset, u32 size, u32 xor) = *(void
> > **)0x988;
>
> Would be nice to have this in a header, e.g.
>
> extern struct imx8mp_bootrom_ops {
> /* ... */
> int (*download_image)(u8 *dest, u32 offset, u32 size, u32 xor);
> } *imx8mp_bootrom_ops = (void *)0x988;
>
> > + size_t count = __piggydata_end - __piggydata_start;
> > + char *p = (char *)MX8M_ATF_BL33_BASE_ADDR + (__piggydata_start -
> > __image_start);
> > +
> > + while (count) {
> > + size_t chunksize = min(count, (size_t)1024);
> > + int ret;
> > +
> > + ret = download_image(p, 0, chunksize, (uintptr_t)p ^ chunksize);
> > + if (ret != 0xf0) {
> > + pr_err("Failed to load piggy data (ret = %x)\n", ret);
> > + return -EIO;
> > + }
> > +
> > + p += chunksize;
> > + count -= chunksize;
> > + }
> > +
> > + return 0;
> > +}
> > +
This shouldn't be in board code, but in some location where it is
reusable by other i.MX8MP boards.
> > extern struct dram_timing_info imx8mp_evk_dram_timing;
> >
> > static void start_atf(void)
> > @@ -125,6 +149,9 @@ static void start_atf(void)
> > case BOOTSOURCE_MMC:
> > imx8mp_esdhc_load_image(instance, false);
> > break;
> > + case BOOTSOURCE_SERIAL:
> > + imx8m_bootrom_load_image();
> > + break;
> > default:
> > printf("Unhandled bootsource BOOTSOURCE_%d\n", src);
> > hang();
> > diff --git a/arch/arm/mach-imx/boot.c b/arch/arm/mach-imx/boot.c
> > index 2b66bbf71eb1..7c1d49291045 100644
> > --- a/arch/arm/mach-imx/boot.c
> > +++ b/arch/arm/mach-imx/boot.c
> > @@ -495,10 +495,12 @@ static void __imx7_get_boot_source(enum bootsource
> > *src, int *instance,
> > case 5:
> > *src = BOOTSOURCE_NOR;
> > break;
> > - case 15:
> > + case 14: /* observed on i.MX8MP for USB "serial" booting */
> > + case 15: /* observed on i.MX8MM for USB "serial" booting */
> > *src = BOOTSOURCE_SERIAL;
> > break;
> > default:
> > + *src = BOOTSOURCE_UNKNOWN;
> > break;
> > }
> > }
> > diff --git a/include/asm-generic/sections.h b/include/asm-generic/sections.h
> > index 870bff21f668..597c4951ea5e 100644
> > --- a/include/asm-generic/sections.h
> > +++ b/include/asm-generic/sections.h
> > @@ -9,6 +9,7 @@ extern char _end[];
> > extern char __image_start[];
> > extern char __image_end[];
> > extern char __piggydata_start[];
> > +extern char __piggydata_end[];
>
> Other code normally uses __image_end, but it seems __piggydata_end should be
> equal to it. I'd prefer __image_end, because conceptually, you want to copy
> off the rest of the image (which happens to be just the piggy data)
>
> @Rouven, The sha sum is at the end of the image, right?
> Would this be included this way?
The checksum is built into the PBL, as it is used to authenticate the
piggydata, as the BootROM will only authenticate the initial loaded
part of the image, i.e. the PBL.
Regards,
Lucas
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[PATCH v2 2/4] ARM: protonic: add initial support for the Protonic PRT8MM family of boards
From: David Jander
This board is a low-cost 7" touchscreen virtual terminal for
agricultural applications.
There is no upstream Linux DT yet, so we add a minimal DT for use with the
bootloader in this patch.
Signed-off-by: David Jander
[lst: fixed and cleaned up for upstream]
Signed-off-by: Lucas Stach
---
Documentation/boards/imx/protonic-prt8mm.rst | 10 +
arch/arm/boards/Makefile |1 +
arch/arm/boards/protonic-imx8m/Makefile |3 +
arch/arm/boards/protonic-imx8m/board.c| 84 +
.../defaultenv-prt8m/boot/prt8mm-default |7 +
.../defaultenv-prt8m/network/eth0-discover|4 +
.../defaultenv-prt8m/nv/boot.default |1 +
.../protonic-imx8m/flash-header-prt8mm.imxcfg |5 +
.../boards/protonic-imx8m/lowlevel-prt8mm.c | 122 +
.../protonic-imx8m/lpddr4-timing-prt8mm.c | 1994 +
arch/arm/dts/Makefile |1 +
arch/arm/dts/imx8mm-prt8mm.dts| 251 +++
arch/arm/mach-imx/Kconfig | 10 +
images/Makefile.imx |5 +
14 files changed, 2498 insertions(+)
create mode 100644 Documentation/boards/imx/protonic-prt8mm.rst
create mode 100644 arch/arm/boards/protonic-imx8m/Makefile
create mode 100644 arch/arm/boards/protonic-imx8m/board.c
create mode 100644
arch/arm/boards/protonic-imx8m/defaultenv-prt8m/boot/prt8mm-default
create mode 100644
arch/arm/boards/protonic-imx8m/defaultenv-prt8m/network/eth0-discover
create mode 100644
arch/arm/boards/protonic-imx8m/defaultenv-prt8m/nv/boot.default
create mode 100644 arch/arm/boards/protonic-imx8m/flash-header-prt8mm.imxcfg
create mode 100644 arch/arm/boards/protonic-imx8m/lowlevel-prt8mm.c
create mode 100644 arch/arm/boards/protonic-imx8m/lpddr4-timing-prt8mm.c
create mode 100644 arch/arm/dts/imx8mm-prt8mm.dts
diff --git a/Documentation/boards/imx/protonic-prt8mm.rst
b/Documentation/boards/imx/protonic-prt8mm.rst
new file mode 100644
index ..f8c8b2c88da0
--- /dev/null
+++ b/Documentation/boards/imx/protonic-prt8mm.rst
@@ -0,0 +1,10 @@
+Protonic Holland PRT8MM board
+=
+
+This board is a low-cost 7inch touchscreen virtual terminal for agricultural
applications.
+HW specs:
+
+* SoC: i.MX8M mini
+* RAM: 1GiB LPDDR4
+* eMMC: 16GiB
+* Display: 7inch 800x480 with capacitive touchscreen.
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index 40b0af8d30b6..51f5f60857c2 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -105,6 +105,7 @@ obj-$(CONFIG_MACH_PM9261) += pm9261/
obj-$(CONFIG_MACH_PM9263) += pm9263/
obj-$(CONFIG_MACH_PM9G45) += pm9g45/
obj-$(CONFIG_MACH_PROTONIC_IMX6) += protonic-imx6/
+obj-$(CONFIG_MACH_PROTONIC_IMX8M) += protonic-imx8m/
obj-$(CONFIG_MACH_QIL_A9260) += qil-a926x/
obj-$(CONFIG_MACH_QIL_A9G20) += qil-a926x/
obj-$(CONFIG_MACH_RADXA_ROCK) += radxa-rock/
diff --git a/arch/arm/boards/protonic-imx8m/Makefile
b/arch/arm/boards/protonic-imx8m/Makefile
new file mode 100644
index ..51a27f0c2dfd
--- /dev/null
+++ b/arch/arm/boards/protonic-imx8m/Makefile
@@ -0,0 +1,3 @@
+obj-y += board.o
+lwl-y += lowlevel-prt8mm.o lpddr4-timing-prt8mm.o
+bbenv-y += defaultenv-prt8m
diff --git a/arch/arm/boards/protonic-imx8m/board.c
b/arch/arm/boards/protonic-imx8m/board.c
new file mode 100644
index ..87264f0c9785
--- /dev/null
+++ b/arch/arm/boards/protonic-imx8m/board.c
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: 2020 David Jander, Protonic Holland
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+static int prt_prt8mm_init_power(void)
+{
+ struct i2c_adapter *adapter = NULL;
+ struct i2c_client client;
+ int ret;
+ char buf[2];
+
+ client.addr = 0x60;
+ adapter = i2c_get_adapter(1);
+ if (!adapter) {
+ printf("i2c bus not found\n");
+ return -ENODEV;
+ }
+ client.adapter = adapter;
+
+ buf[0] = 0xe3;
+ ret = i2c_write_reg(&client, 0x00, buf, 1); // VSEL0 = 0.95V, force PWM
+ if (ret < 0) {
+ printf("i2c write error\n");
+ return -ENODEV;
+ }
+ buf[0] = 0xe0;
+ ret = i2c_write_reg(&client, 0x01, buf, 1); // VSEL1 = 0.92V, force PWM
+ if (ret < 0) {
+ printf("i2c write error\n");
+ return -ENODEV;
+ }
+ return 0;
+}
+
+static int prt_prt8mm_probe(struct device_d *dev)
+{
+ int emmc_bbu_flag = 0;
+ int sd_bbu_flag = 0;
+
+ prt_prt8mm_init_power();
+
+ barebox_set_hostname("prt8mm");
+
+ if (bootsource_get() == BOOTSOURCE_MMC) {
+ if (bootsource_get_instance() ==
[PATCH v2 1/4] drivers: mci: imx-esdhc-common.c: Add missing dev_dbg define for pbl case
From: David Jander Signed-off-by: David Jander Signed-off-by: Lucas Stach --- drivers/mci/imx-esdhc-common.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mci/imx-esdhc-common.c b/drivers/mci/imx-esdhc-common.c index c9d589468f6c..7ee0674b997f 100644 --- a/drivers/mci/imx-esdhc-common.c +++ b/drivers/mci/imx-esdhc-common.c @@ -156,7 +156,9 @@ static void __udelay(int us) #define udelay(n) __udelay(n) #undef dev_err +#undef dev_dbg #define dev_err(d, ...)pr_err(__VA_ARGS__) +#define dev_dbg(d, ...)pr_debug(__VA_ARGS__) #endif -- 2.29.2 ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH v2 3/4] ARM: imx_v8_defconfig: enable PRT8MM board
Signed-off-by: Lucas Stach --- arch/arm/configs/imx_v8_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/imx_v8_defconfig b/arch/arm/configs/imx_v8_defconfig index 06d79f594d5b..db097d1675b8 100644 --- a/arch/arm/configs/imx_v8_defconfig +++ b/arch/arm/configs/imx_v8_defconfig @@ -1,5 +1,6 @@ CONFIG_ARCH_IMX=y CONFIG_IMX_MULTI_BOARDS=y +CONFIG_MACH_PROTONIC_IMX8M=y CONFIG_MACH_ZII_IMX8MQ_DEV=y CONFIG_MACH_NXP_IMX8MM_EVK=y CONFIG_MACH_NXP_IMX8MP_EVK=y -- 2.29.2 ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH v2 4/4] ARM: imx_v8_defconfig: enable EHCI
The i.MX8MM USB host controller uses the standard EHCI interface. Enable support in the defconfig to make this work out of the box. Signed-off-by: Lucas Stach --- arch/arm/configs/imx_v8_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/imx_v8_defconfig b/arch/arm/configs/imx_v8_defconfig index db097d1675b8..e1e7b0f91e67 100644 --- a/arch/arm/configs/imx_v8_defconfig +++ b/arch/arm/configs/imx_v8_defconfig @@ -105,6 +105,7 @@ CONFIG_MTD_DATAFLASH=y CONFIG_MTD_M25P80=y CONFIG_USB_HOST=y CONFIG_USB_IMX_CHIPIDEA=y +CONFIG_USB_EHCI=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_SERIAL=y -- 2.29.2 ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH 2/2] bootm: add support for booting compressed images
Am Mittwoch, dem 26.05.2021 um 11:41 +0200 schrieb Ahmad Fatoum:
> On 26.05.21 11:39, Lucas Stach wrote:
> > Hi Ahmad,
> >
> > Am Mittwoch, dem 26.05.2021 um 11:17 +0200 schrieb Ahmad Fatoum:
> > > Hello Lucas,
> > >
> > > On 25.05.21 20:37, Lucas Stach wrote:
> > > > ARM64 does not have a self extracting image format, but relies on the
> > > > image
> > > > being externally compressed with one of the standard compression
> > > > algorithms.
> > > >
> > > > Add support for decompressing the bootm OS image. It is added in common
> > > > code as it may also be useful for other images/architectures.
> > > >
> > > > Signed-off-by: Lucas Stach
> > > > ---
> > > > common/bootm.c | 92 ++
> > > > 1 file changed, 92 insertions(+)
> > > >
> > > > diff --git a/common/bootm.c b/common/bootm.c
> > > > index 092116beb94a..2bfb5cb01593 100644
> > > > --- a/common/bootm.c
> > > > +++ b/common/bootm.c
> > > > @@ -12,6 +12,7 @@
> > > > #include
> > > > #include
> > > > #include
> > > > +#include
> > > >
> > > > static LIST_HEAD(handler_list);
> > > >
> > > > @@ -808,6 +809,85 @@ err_out:
> > > > return ret;
> > > > }
> > > >
> > > > +static int do_bootm_compressed(struct image_data *img_data)
> > > > +{
> > > > + struct bootm_data bootm_data = {
> > > > + .oftree_file = img_data->oftree_file,
> > > > + .initrd_file = img_data->initrd_file,
> > > > + .tee_file = img_data->tee_file,
> > > > + .verbose = img_data->verbose,
> > > > + .verify = img_data->verify,
> > > > + .force = img_data->force,
> > > > + .dryrun = img_data->dryrun,
> > > > + .initrd_address = img_data->initrd_address,
> > > > + .os_address = img_data->os_address,
> > >
> > > I am wondering whether it makes sense to directly extract
> > > to os_address to avoid the extra copy. Depending on the subsequent
> > > bootm handler, the image may still need to be relocated, but if
> > > we choose a generous alignment here, the copy later on could
> > > be avoided.
> >
> > For the common case where we let Barebox/the bootm image handler decide
> > where to put the OS image, we don't know this address yet when
> > decompressing the image here. I don't think it makes sense to optimize
> > the special case where the OS address is already known.
>
> I see. A debug print for higher verbosity levels, just before invoking
> bootm_boot would be nice, so it's easy to find out how long the
> extraction took.
Actually due to the way this is implemented as nested bootm you kind of
get this naturally. The output when booting a compressed image looks
like this:
blspec: booting someboard from somewhere
Loading LZO compressed 'somewhere/Image.lzo'
Loading ARM aarch64 Linux image '/tmp/bootm-compressed-6504dc00'
Loading devicetree from 'somewhere/someboard.dtb'
Regards,
Lucas
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Re: [PATCH 2/2] bootm: add support for booting compressed images
Hi Ahmad,
Am Mittwoch, dem 26.05.2021 um 11:17 +0200 schrieb Ahmad Fatoum:
> Hello Lucas,
>
> On 25.05.21 20:37, Lucas Stach wrote:
> > ARM64 does not have a self extracting image format, but relies on the image
> > being externally compressed with one of the standard compression algorithms.
> >
> > Add support for decompressing the bootm OS image. It is added in common
> > code as it may also be useful for other images/architectures.
> >
> > Signed-off-by: Lucas Stach
> > ---
> > common/bootm.c | 92 ++
> > 1 file changed, 92 insertions(+)
> >
> > diff --git a/common/bootm.c b/common/bootm.c
> > index 092116beb94a..2bfb5cb01593 100644
> > --- a/common/bootm.c
> > +++ b/common/bootm.c
> > @@ -12,6 +12,7 @@
> > #include
> > #include
> > #include
> > +#include
> >
> > static LIST_HEAD(handler_list);
> >
> > @@ -808,6 +809,85 @@ err_out:
> > return ret;
> > }
> >
> > +static int do_bootm_compressed(struct image_data *img_data)
> > +{
> > + struct bootm_data bootm_data = {
> > + .oftree_file = img_data->oftree_file,
> > + .initrd_file = img_data->initrd_file,
> > + .tee_file = img_data->tee_file,
> > + .verbose = img_data->verbose,
> > + .verify = img_data->verify,
> > + .force = img_data->force,
> > + .dryrun = img_data->dryrun,
> > + .initrd_address = img_data->initrd_address,
> > + .os_address = img_data->os_address,
>
> I am wondering whether it makes sense to directly extract
> to os_address to avoid the extra copy. Depending on the subsequent
> bootm handler, the image may still need to be relocated, but if
> we choose a generous alignment here, the copy later on could
> be avoided.
For the common case where we let Barebox/the bootm image handler decide
where to put the OS image, we don't know this address yet when
decompressing the image here. I don't think it makes sense to optimize
the special case where the OS address is already known.
Regards,
Lucas
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[PATCH v2 2/2] bootm: add support for booting compressed images
ARM64 does not have a self extracting image format, but relies on the image
being externally compressed with one of the standard compression algorithms.
Add support for decompressing the bootm OS image. It is added in common
code as it may also be useful for other images/architectures.
Signed-off-by: Lucas Stach
---
v2: Add proper error handling if nested bootm fails.
---
common/bootm.c | 93 ++
1 file changed, 93 insertions(+)
diff --git a/common/bootm.c b/common/bootm.c
index 092116beb94a..f5c0e5184b0a 100644
--- a/common/bootm.c
+++ b/common/bootm.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
static LIST_HEAD(handler_list);
@@ -808,6 +809,86 @@ err_out:
return ret;
}
+static int do_bootm_compressed(struct image_data *img_data)
+{
+ struct bootm_data bootm_data = {
+ .oftree_file = img_data->oftree_file,
+ .initrd_file = img_data->initrd_file,
+ .tee_file = img_data->tee_file,
+ .verbose = img_data->verbose,
+ .verify = img_data->verify,
+ .force = img_data->force,
+ .dryrun = img_data->dryrun,
+ .initrd_address = img_data->initrd_address,
+ .os_address = img_data->os_address,
+ .os_entry = img_data->os_entry,
+ };
+ int from, to, ret;
+ char *dstpath;
+
+ from = open(img_data->os_file, O_RDONLY);
+ if (from < 0)
+ return -ENODEV;
+
+ dstpath = make_temp("bootm-compressed");
+ if (!dstpath) {
+ ret = -ENOMEM;
+ goto fail_from;
+ }
+
+ to = open(dstpath, O_CREAT | O_WRONLY);
+ if (to < 0) {
+ ret = -ENODEV;
+ goto fail_make_temp;
+ }
+
+ ret = uncompress_fd_to_fd(from, to, uncompress_err_stdout);
+ if (ret)
+ goto fail_to;
+
+ bootm_data.os_file = dstpath;
+ ret = bootm_boot(&bootm_data);
+
+fail_to:
+ close(to);
+ unlink(dstpath);
+fail_make_temp:
+ free(dstpath);
+fail_from:
+ close(from);
+ return ret;
+}
+
+static struct image_handler bzip2_bootm_handler = {
+ .name = "BZIP2 compressed file",
+ .bootm = do_bootm_compressed,
+ .filetype = filetype_bzip2,
+};
+
+static struct image_handler gzip_bootm_handler = {
+ .name = "GZIP compressed file",
+ .bootm = do_bootm_compressed,
+ .filetype = filetype_gzip,
+};
+
+static struct image_handler lzo_bootm_handler = {
+ .name = "LZO compressed file",
+ .bootm = do_bootm_compressed,
+ .filetype = filetype_lzo_compressed,
+};
+
+static struct image_handler lz4_bootm_handler = {
+ .name = "LZ4 compressed file",
+ .bootm = do_bootm_compressed,
+ .filetype = filetype_lz4_compressed,
+};
+
+static struct image_handler xz_bootm_handler = {
+ .name = "XZ compressed file",
+ .bootm = do_bootm_compressed,
+ .filetype = filetype_xz_compressed,
+};
+
static int bootm_init(void)
{
globalvar_add_simple("bootm.image", NULL);
@@ -830,6 +911,18 @@ static int bootm_init(void)
globalvar_add_simple_enum("bootm.verify", (unsigned int
*)&bootm_verify_mode,
bootm_verify_names,
ARRAY_SIZE(bootm_verify_names));
+
+ if (IS_ENABLED(CONFIG_BZLIB))
+ register_image_handler(&bzip2_bootm_handler);
+ if (IS_ENABLED(CONFIG_ZLIB))
+ register_image_handler(&gzip_bootm_handler);
+ if (IS_ENABLED(CONFIG_LZO_DECOMPRESS))
+ register_image_handler(&lzo_bootm_handler);
+ if (IS_ENABLED(CONFIG_LZ4_DECOMPRESS))
+ register_image_handler(&lz4_bootm_handler);
+ if (IS_ENABLED(CONFIG_XZ_DECOMPRESS))
+ register_image_handler(&xz_bootm_handler);
+
return 0;
}
late_initcall(bootm_init);
--
2.29.2
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[PATCH v2 1/2] uncompress: use read_full to fill decompression buffer
The decompression algorithms want all of the requested buffer size
to be filled and don't cope with less bytes being returned.
Use read_full to satisfy this requirement.
Signed-off-by: Lucas Stach
---
lib/uncompress.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/lib/uncompress.c b/lib/uncompress.c
index c47d319dbb5f..5c0d1e9f4d66 100644
--- a/lib/uncompress.c
+++ b/lib/uncompress.c
@@ -24,6 +24,7 @@
#include
#include
#include
+#include
static void *uncompress_buf;
static unsigned int uncompress_size;
@@ -142,7 +143,7 @@ static int uncompress_infd, uncompress_outfd;
static int fill_fd(void *buf, unsigned int len)
{
- return read(uncompress_infd, buf, len);
+ return read_full(uncompress_infd, buf, len);
}
static int flush_fd(void *buf, unsigned int len)
--
2.29.2
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[PATCH 1/3] ARM: protonic: add initial support for the Protonic PRT8MM family of boards
From: David Jander
This board is a low-cost 7" touchscreen virtual terminal for
agricultural applications.
There is no upstream Linux DT yet, so we add a minimal DT for use with the
bootloader in this patch.
Signed-off-by: David Jander
[lst: fixed and cleaned up for upstream]
Signed-off-by: Lucas Stach
---
Documentation/boards/imx/protonic-prt8mm.rst | 10 +
arch/arm/boards/Makefile |1 +
arch/arm/boards/protonic-imx8m/Makefile |3 +
arch/arm/boards/protonic-imx8m/board.c| 92 +
.../defaultenv-prt8m/network/eth0-discover|4 +
.../protonic-imx8m/flash-header-prt8mm.imxcfg |5 +
.../boards/protonic-imx8m/lowlevel-prt8mm.c | 131 ++
.../protonic-imx8m/lpddr4-timing-prt8mm.c | 1994 +
arch/arm/dts/Makefile |1 +
arch/arm/dts/imx8mm-prt8mm.dts| 251 +++
arch/arm/mach-imx/Kconfig | 10 +
images/Makefile.imx |5 +
12 files changed, 2507 insertions(+)
create mode 100644 Documentation/boards/imx/protonic-prt8mm.rst
create mode 100644 arch/arm/boards/protonic-imx8m/Makefile
create mode 100644 arch/arm/boards/protonic-imx8m/board.c
create mode 100644
arch/arm/boards/protonic-imx8m/defaultenv-prt8m/network/eth0-discover
create mode 100644 arch/arm/boards/protonic-imx8m/flash-header-prt8mm.imxcfg
create mode 100644 arch/arm/boards/protonic-imx8m/lowlevel-prt8mm.c
create mode 100644 arch/arm/boards/protonic-imx8m/lpddr4-timing-prt8mm.c
create mode 100644 arch/arm/dts/imx8mm-prt8mm.dts
diff --git a/Documentation/boards/imx/protonic-prt8mm.rst
b/Documentation/boards/imx/protonic-prt8mm.rst
new file mode 100644
index ..f8c8b2c88da0
--- /dev/null
+++ b/Documentation/boards/imx/protonic-prt8mm.rst
@@ -0,0 +1,10 @@
+Protonic Holland PRT8MM board
+=
+
+This board is a low-cost 7inch touchscreen virtual terminal for agricultural
applications.
+HW specs:
+
+* SoC: i.MX8M mini
+* RAM: 1GiB LPDDR4
+* eMMC: 16GiB
+* Display: 7inch 800x480 with capacitive touchscreen.
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index 40b0af8d30b6..51f5f60857c2 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -105,6 +105,7 @@ obj-$(CONFIG_MACH_PM9261) += pm9261/
obj-$(CONFIG_MACH_PM9263) += pm9263/
obj-$(CONFIG_MACH_PM9G45) += pm9g45/
obj-$(CONFIG_MACH_PROTONIC_IMX6) += protonic-imx6/
+obj-$(CONFIG_MACH_PROTONIC_IMX8M) += protonic-imx8m/
obj-$(CONFIG_MACH_QIL_A9260) += qil-a926x/
obj-$(CONFIG_MACH_QIL_A9G20) += qil-a926x/
obj-$(CONFIG_MACH_RADXA_ROCK) += radxa-rock/
diff --git a/arch/arm/boards/protonic-imx8m/Makefile
b/arch/arm/boards/protonic-imx8m/Makefile
new file mode 100644
index ..51a27f0c2dfd
--- /dev/null
+++ b/arch/arm/boards/protonic-imx8m/Makefile
@@ -0,0 +1,3 @@
+obj-y += board.o
+lwl-y += lowlevel-prt8mm.o lpddr4-timing-prt8mm.o
+bbenv-y += defaultenv-prt8m
diff --git a/arch/arm/boards/protonic-imx8m/board.c
b/arch/arm/boards/protonic-imx8m/board.c
new file mode 100644
index ..08694068507c
--- /dev/null
+++ b/arch/arm/boards/protonic-imx8m/board.c
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: 2020 David Jander, Protonic Holland
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+static int prt_prt8mm_init_power(void)
+{
+ struct i2c_adapter *adapter = NULL;
+ struct i2c_client client;
+ int ret;
+ char buf[2];
+
+ client.addr = 0x60;
+ adapter = i2c_get_adapter(1);
+ if (!adapter) {
+ printf("i2c bus not found\n");
+ return -ENODEV;
+ }
+ client.adapter = adapter;
+
+ buf[0] = 0xe3;
+ ret = i2c_write_reg(&client, 0x00, buf, 1); // VSEL0 = 0.95V, force PWM
+ if (ret < 0) {
+ printf("i2c write error\n");
+ return -ENODEV;
+ }
+ buf[0] = 0xe0;
+ ret = i2c_write_reg(&client, 0x01, buf, 1); // VSEL1 = 0.92V, force PWM
+ if (ret < 0) {
+ printf("i2c write error\n");
+ return -ENODEV;
+ }
+ return 0;
+}
+
+static int prt_prt8mm_probe(struct device_d *dev)
+{
+ int emmc_bbu_flag = 0;
+ int sd_bbu_flag = 0;
+
+ prt_prt8mm_init_power();
+
+ barebox_set_hostname("prt8mm");
+
+ if (bootsource_get() == BOOTSOURCE_MMC) {
+ if (bootsource_get_instance() == 2) {
+ of_device_enable_path("/chosen/environment-emmc");
+ emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT;
+ } else {
+ of_device_enable_path("/chosen/environment-sd");
+
[PATCH 2/3] ARM: imx_v8_defconfig: enable PRT8MM board
Signed-off-by: Lucas Stach --- arch/arm/configs/imx_v8_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/imx_v8_defconfig b/arch/arm/configs/imx_v8_defconfig index 06d79f594d5b..db097d1675b8 100644 --- a/arch/arm/configs/imx_v8_defconfig +++ b/arch/arm/configs/imx_v8_defconfig @@ -1,5 +1,6 @@ CONFIG_ARCH_IMX=y CONFIG_IMX_MULTI_BOARDS=y +CONFIG_MACH_PROTONIC_IMX8M=y CONFIG_MACH_ZII_IMX8MQ_DEV=y CONFIG_MACH_NXP_IMX8MM_EVK=y CONFIG_MACH_NXP_IMX8MP_EVK=y -- 2.29.2 ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH 3/3] ARM: imx_v8_defconfig: enable EHCI
The i.MX8MM USB host controller uses the standard EHCI interface. Enable support in the defconfig to make this work out of the box. Signed-off-by: Lucas Stach --- arch/arm/configs/imx_v8_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/imx_v8_defconfig b/arch/arm/configs/imx_v8_defconfig index db097d1675b8..e1e7b0f91e67 100644 --- a/arch/arm/configs/imx_v8_defconfig +++ b/arch/arm/configs/imx_v8_defconfig @@ -105,6 +105,7 @@ CONFIG_MTD_DATAFLASH=y CONFIG_MTD_M25P80=y CONFIG_USB_HOST=y CONFIG_USB_IMX_CHIPIDEA=y +CONFIG_USB_EHCI=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_SERIAL=y -- 2.29.2 ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH 2/2] bootm: add support for booting compressed images
ARM64 does not have a self extracting image format, but relies on the image
being externally compressed with one of the standard compression algorithms.
Add support for decompressing the bootm OS image. It is added in common
code as it may also be useful for other images/architectures.
Signed-off-by: Lucas Stach
---
common/bootm.c | 92 ++
1 file changed, 92 insertions(+)
diff --git a/common/bootm.c b/common/bootm.c
index 092116beb94a..2bfb5cb01593 100644
--- a/common/bootm.c
+++ b/common/bootm.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
static LIST_HEAD(handler_list);
@@ -808,6 +809,85 @@ err_out:
return ret;
}
+static int do_bootm_compressed(struct image_data *img_data)
+{
+ struct bootm_data bootm_data = {
+ .oftree_file = img_data->oftree_file,
+ .initrd_file = img_data->initrd_file,
+ .tee_file = img_data->tee_file,
+ .verbose = img_data->verbose,
+ .verify = img_data->verify,
+ .force = img_data->force,
+ .dryrun = img_data->dryrun,
+ .initrd_address = img_data->initrd_address,
+ .os_address = img_data->os_address,
+ .os_entry = img_data->os_entry,
+ };
+ int from, to, ret;
+ char *dstpath;
+
+ from = open(img_data->os_file, O_RDONLY);
+ if (from < 0)
+ return -ENODEV;
+
+ dstpath = make_temp("bootm-compressed");
+ if (!dstpath) {
+ ret = -ENOMEM;
+ goto fail_from;
+ }
+
+ to = open(dstpath, O_CREAT | O_WRONLY);
+ if (to < 0) {
+ ret = -ENODEV;
+ goto fail_make_temp;
+ }
+
+ ret = uncompress_fd_to_fd(from, to, uncompress_err_stdout);
+ if (ret)
+ goto fail_to;
+
+ bootm_data.os_file = dstpath;
+ return bootm_boot(&bootm_data);
+
+fail_to:
+ close(to);
+fail_make_temp:
+ free(dstpath);
+fail_from:
+ close(from);
+ return ret;
+}
+
+static struct image_handler bzip2_bootm_handler = {
+ .name = "BZIP2 compressed file",
+ .bootm = do_bootm_compressed,
+ .filetype = filetype_bzip2,
+};
+
+static struct image_handler gzip_bootm_handler = {
+ .name = "GZIP compressed file",
+ .bootm = do_bootm_compressed,
+ .filetype = filetype_gzip,
+};
+
+static struct image_handler lzo_bootm_handler = {
+ .name = "LZO compressed file",
+ .bootm = do_bootm_compressed,
+ .filetype = filetype_lzo_compressed,
+};
+
+static struct image_handler lz4_bootm_handler = {
+ .name = "LZ4 compressed file",
+ .bootm = do_bootm_compressed,
+ .filetype = filetype_lz4_compressed,
+};
+
+static struct image_handler xz_bootm_handler = {
+ .name = "XZ compressed file",
+ .bootm = do_bootm_compressed,
+ .filetype = filetype_xz_compressed,
+};
+
static int bootm_init(void)
{
globalvar_add_simple("bootm.image", NULL);
@@ -830,6 +910,18 @@ static int bootm_init(void)
globalvar_add_simple_enum("bootm.verify", (unsigned int
*)&bootm_verify_mode,
bootm_verify_names,
ARRAY_SIZE(bootm_verify_names));
+
+ if (IS_ENABLED(CONFIG_BZLIB))
+ register_image_handler(&bzip2_bootm_handler);
+ if (IS_ENABLED(CONFIG_ZLIB))
+ register_image_handler(&gzip_bootm_handler);
+ if (IS_ENABLED(CONFIG_LZO_DECOMPRESS))
+ register_image_handler(&lzo_bootm_handler);
+ if (IS_ENABLED(CONFIG_LZ4_DECOMPRESS))
+ register_image_handler(&lz4_bootm_handler);
+ if (IS_ENABLED(CONFIG_XZ_DECOMPRESS))
+ register_image_handler(&xz_bootm_handler);
+
return 0;
}
late_initcall(bootm_init);
--
2.29.2
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[PATCH 1/2] uncompress: use read_full to fill decompression buffer
The decompression algorithms want all of the requested buffer size
to be filled and don't cope with less bytes being returned.
Use read_full to satisfy this requirement.
Signed-off-by: Lucas Stach
---
lib/uncompress.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/lib/uncompress.c b/lib/uncompress.c
index c47d319dbb5f..5c0d1e9f4d66 100644
--- a/lib/uncompress.c
+++ b/lib/uncompress.c
@@ -24,6 +24,7 @@
#include
#include
#include
+#include
static void *uncompress_buf;
static unsigned int uncompress_size;
@@ -142,7 +143,7 @@ static int uncompress_infd, uncompress_outfd;
static int fill_fd(void *buf, unsigned int len)
{
- return read(uncompress_infd, buf, len);
+ return read_full(uncompress_infd, buf, len);
}
static int flush_fd(void *buf, unsigned int len)
--
2.29.2
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[PATCH] ARM: use new vendor prefix for MNT Reform2
From: Lucas Stach
The vendor prefix for MNT Research GmbH in the upstream kernel will be
mntre (not yet landed, but acked by the maintainer). Switch to this
prefix in Barebox now to keep bootspec booting working.
Signed-off-by: Lucas Stach
---
arch/arm/boards/mnt-reform/board.c | 2 +-
arch/arm/dts/imx8mq-mnt-reform2.dts | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boards/mnt-reform/board.c
b/arch/arm/boards/mnt-reform/board.c
index e2d628586a50..feb874c0a0ef 100644
--- a/arch/arm/boards/mnt-reform/board.c
+++ b/arch/arm/boards/mnt-reform/board.c
@@ -28,7 +28,7 @@ static int mnt_reform_probe(struct device_d *dev)
}
static const struct of_device_id mnt_reform_of_match[] = {
- { .compatible = "mnt,reform2"},
+ { .compatible = "mntre,reform2"},
{ /* sentinel */ },
};
diff --git a/arch/arm/dts/imx8mq-mnt-reform2.dts
b/arch/arm/dts/imx8mq-mnt-reform2.dts
index 4e80e00dd143..5a65324b3c75 100644
--- a/arch/arm/dts/imx8mq-mnt-reform2.dts
+++ b/arch/arm/dts/imx8mq-mnt-reform2.dts
@@ -12,7 +12,7 @@
/ {
model = "MNT Reform2";
- compatible = "mnt,reform2", "fsl,imx8mq";
+ compatible = "mntre,reform2", "fsl,imx8mq";
chosen {
stdout-path = &uart1;
--
2.31.1
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Re: [PATCH 1/1] zedboard: add support for usb
Hi Michael,
Am Montag, dem 03.05.2021 um 14:08 + schrieb Michael Graichen:
> This adds minimalistic support for USB on the Zedboard/Zynq-7000
This change does 3 distinct things and should be split in 3 patches to
do one thing at a time:
- add Zynq EHCI support
- add ULPI PHY ID
- add Zedboard USB pinmux
> From e1e1cdc8e2f82a5c9ecb4acc8eb67181687791d0 Mon Sep 17 00:00:00 2001
> From: Michael Graichen
> Date: Mon, 3 May 2021 16:08:23 +0200
> Subject: [PATCH] zedboard: add support for usb
>
> Signed-off-by: Michael Graichen
> ---
> arch/arm/boards/avnet-zedboard/lowlevel.c | 13 +++
> drivers/usb/host/Kconfig | 6 +++
> drivers/usb/host/Makefile | 1 +
> drivers/usb/host/ehci-zynq.c | 47 +++
> drivers/usb/otg/ulpi.c| 1 +
> 5 files changed, 68 insertions(+)
> create mode 100644 drivers/usb/host/ehci-zynq.c
>
> diff --git a/arch/arm/boards/avnet-zedboard/lowlevel.c
> b/arch/arm/boards/avnet-zedboard/lowlevel.c
> index f7bdceb42..e43832218 100644
> --- a/arch/arm/boards/avnet-zedboard/lowlevel.c
> +++ b/arch/arm/boards/avnet-zedboard/lowlevel.c
> @@ -236,6 +236,19 @@ static void avnet_zedboard_ps7_init(void)
> writel(0x0702, ZYNQ_MIO_BASE + 0x14);
> writel(0x0702, ZYNQ_MIO_BASE + 0x18);
> writel(0x0602, ZYNQ_MIO_BASE + 0x20);
> + /* USB0 */
> + writel(0x0304, ZYNQ_MIO_BASE + 0x70); // MIO_PIN_28 =>
> OTG_DATA_4
> + writel(0x0305, ZYNQ_MIO_BASE + 0x74); // MIO_PIN_29 => OTG_DIR
> + writel(0x0304, ZYNQ_MIO_BASE + 0x78); // MIO_PIN_30 => OTG_STP
> + writel(0x0305, ZYNQ_MIO_BASE + 0x7c); // MIO_PIN_31 => OTG_NXT
> + writel(0x0304, ZYNQ_MIO_BASE + 0x80); // MIO_PIN_32 =>
> OTG_DATA_0
> + writel(0x0304, ZYNQ_MIO_BASE + 0x84); // MIO_PIN_33 =>
> OTG_DATA_1
> + writel(0x0304, ZYNQ_MIO_BASE + 0x88); // MIO_PIN_34 =>
> OTG_DATA_2
> + writel(0x0304, ZYNQ_MIO_BASE + 0x8c); // MIO_PIN_35 =>
> OTG_DATA_3
> + writel(0x0305, ZYNQ_MIO_BASE + 0x90); // MIO_PIN_36 => OTG-CLK
> + writel(0x0304, ZYNQ_MIO_BASE + 0x94); // MIO_PIN_37 =>
> OTG_DATA_5
> + writel(0x0304, ZYNQ_MIO_BASE + 0x98); // MIO_PIN_38 =>
> OTG_DATA_6
> + writel(0x0304, ZYNQ_MIO_BASE + 0x9c); // MIO_PIN_39 =>
> OTG_DATA_7
>
>
> /* poor mans clkctrl */
> writel(0x1403, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_UART_CLK_CTRL);
> diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
> index 891523c4d..fcd90824c 100644
> --- a/drivers/usb/host/Kconfig
> +++ b/drivers/usb/host/Kconfig
> @@ -13,6 +13,12 @@ config USB_EHCI_ATMEL
> select USB_OHCI_AT91
> bool "Atmel EHCI driver"
>
>
> +config USB_EHCI_ZYNQ
> + bool "Support for Xilinx Zynq on-chip EHCI USB controller"
> + depends on ARCH_ZYNQ
> + help
> + Enable support for Zynq on-chip EHCI USB controller
> +
Maybe update the defconfig too, if it doesn't blow up the image size
too much?
> config USB_OHCI
> bool "OHCI driver"
> depends on !MMU && HAS_DMA
> diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
> index e7a6cf213..eef038128 100644
> --- a/drivers/usb/host/Makefile
> +++ b/drivers/usb/host/Makefile
> @@ -1,6 +1,7 @@
> obj-$(CONFIG_USB_EHCI) += ehci-hcd.o
> obj-$(CONFIG_USB_EHCI_OMAP) += ehci-omap.o
> obj-$(CONFIG_USB_EHCI_ATMEL) += ehci-atmel.o
> +obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
> obj-$(CONFIG_USB_OHCI) += ohci-hcd.o
> obj-$(CONFIG_USB_OHCI_AT91) += ohci-at91.o
> obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o
> diff --git a/drivers/usb/host/ehci-zynq.c b/drivers/usb/host/ehci-zynq.c
> new file mode 100644
> index 0..4246960e1
> --- /dev/null
> +++ b/drivers/usb/host/ehci-zynq.c
> @@ -0,0 +1,47 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * USB Low level initialization(Specific to Zynq 7000)
> + */
> +
> +#include
> +#include
> +
> +struct zynq_ehci_priv {
> + struct device_d *dev;
> + void __iomem *base;
> +};
> +
> +static int zynq_ehci_probe(struct device_d *dev)
> +{
> + struct zynq_ehci_priv *pdata;
pdata isn't used anywhere AFAICS, maybe drop it and simplify the code?
Regards,
Lucas
> + struct resource *res;
> + void __iomem *base;
> +
> + pdata = xzalloc(sizeof(*pdata));
> + pdata->dev = dev;
> + dev->priv = pdata;
> +
> + res = dev_get_resource(dev, IORESOURCE_MEM, 0);
> + if (!res)
> + return -EINVAL;
> +
> + base = IOMEM(res->start);
> + pdata->base = base;
> +
> + ulpi_setup(base + 0x170, 1);
> + add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, (unsigned int)base,
> NULL);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id zynq_ehci_dt_ids[] = {
> + { .compatible = "xlnx,zynq-usb-2.20a" },
> + { /* sentinel */ }
> +};
> +
> +static st
Re: [PATCH 1/1] Zynq: add support to chainload another barebox
Hi Michael, Am Montag, dem 03.05.2021 um 10:07 + schrieb Michael Graichen: > Since OCRAM is only 192K this introduces CONFIG_ZYNQ_BUILD_FSBL so we can can > chainload a more feature rich barebox via bootm. > > From 1f1a95eca42198d73c38cc12b9b44f061980cef8 Mon Sep 17 00:00:00 2001 > From: Michael Graichen > Date: Mon, 3 May 2021 12:03:05 +0200 > Subject: [PATCH] zynq: add support to chainload another barebox Seems you imported this patch from somewhere and it left some traces in the commit message? Also I don't understand what this change is supposed to be doing. You are building just another Barebox binary, with no real differences in the configuration. I would much prefer a proper 2-stage loading in the PBL, but that requires FAT support for the SDcard boot, which I didn't get around to take a look at yet. Regards, Lucas > Signed-off-by: Michael Graichen > --- > arch/arm/mach-zynq/Kconfig | 6 +- > images/Makefile.zynq | 21 +++-- > 2 files changed, 20 insertions(+), 7 deletions(-) > > diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig > index 3e07633e5..0800b55e6 100644 > --- a/arch/arm/mach-zynq/Kconfig > +++ b/arch/arm/mach-zynq/Kconfig > @@ -21,7 +21,11 @@ config ARCH_ZYNQ7000 > select OFDEVICE > select RELOCATABLE > > - > +config ZYNQ_BUILD_FSBL > + prompt "build FSBL binary (BOOT.BIN)" > + bool > + help > + Say Y here if you want to build an FSBL binary for the Zynq. > > menu "select Zynq boards to be built" > > diff --git a/images/Makefile.zynq b/images/Makefile.zynq > index b00e74869..39c72bd88 100644 > --- a/images/Makefile.zynq > +++ b/images/Makefile.zynq > @@ -7,17 +7,26 @@ zynqcfg_cpp_flags = -Wp,-MD,$(depfile) -nostdinc -x > assembler-with-cpp \ > > zynqcfg-tmp = $(subst $(comma),_,$(dot-target).zynqcfg.tmp) > > -quiet_cmd_zynq_image = ZYNQIMG $@ > +quiet_cmd_zynq_image = ZYNQIMG $@ > cmd_zynq_image = \ > $(CPP) $(zynqcfg_cpp_flags) -o $(zynqcfg-tmp) $(CFG_$(@F)) ; \ > $(objtree)/scripts/zynq_mkimage -c $(zynqcfg-tmp) \ > - -f $(subst .zynqimg,,$@) -o $@ > + -f $(subst .zynqimg_fsbl,,$@) -o $@ > > -$(obj)/%.zynqimg: $(obj)/% FORCE > +$(obj)/%.zynqimg_fsbl: $(obj)/% FORCE > $(call if_changed,zynq_image) > > > #-- > > -CFG_start_avnet_zedboard.pblb.zynqimg = > $(board)/avnet-zedboard/zedboard.zynqcfg > -FILE_barebox-avnet-zedboard.img = start_avnet_zedboard.pblb.zynqimg > -image-$(CONFIG_MACH_ZEDBOARD) += barebox-avnet-zedboard.img > +FILE_barebox-avnet-zedboard.img = start_avnet_zedboard.pblb > +zynq-barebox-$(CONFIG_MACH_ZEDBOARD) += barebox-avnet-zedboard.img > + > +CFG_start_avnet_zedboard.pblb.zynqimg_fsbl = > $(board)/avnet-zedboard/zedboard.zynqcfg > +FILE_barebox-avnet-zedboard-fsbl.img = start_avnet_zedboard.pblb.zynqimg_fsbl > +zynq-fsbl-$(CONFIG_MACH_ZEDBOARD) += barebox-avnet-zedboard-fsbl.img > + > +ifdef CONFIG_ZYNQ_BUILD_FSBL > +image-y += $(zynq-fsbl-y) > +else > +image-y += $(zynq-barebox-y) > +endif > -- > 2.25.1 > > ___ > barebox mailing list > barebox@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/barebox ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH] scripts/spdxcheck.py: Use Python 3
Hi Antony,
Am Mittwoch, dem 28.04.2021 um 07:39 +0300 schrieb Antony Pavlov:
> On Fri, 16 Apr 2021 12:14:04 +0300
> Antony Pavlov wrote:
>
> ping
Please be patient. Sascha is out sick, but should be back next week.
Regards,
Lucas
> > Based on this linux kernel commit:
> >
> > > commit d0259c42abff51b586496a0594933e394efefbc5
> > > Author: Bert Vermeulen
> > > Date: Thu Jan 21 09:54:12 2021 +0100
> > >
> > > spdxcheck.py: Use Python 3
> > >
> > > Python 2.x has been officially EOL'ed for some time, and in any case
> > > the git module for it is hard to come by.
> >
> > Signed-off-by: Antony Pavlov
> > ---
> > scripts/checkpatch.pl | 4 ++--
> > scripts/spdxcheck.py | 2 +-
> > 2 files changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
> > index b8bd4e1a59..36e3d768f3 100755
> > --- a/scripts/checkpatch.pl
> > +++ b/scripts/checkpatch.pl
> > @@ -885,10 +885,10 @@ sub is_maintained_obsolete {
> > sub is_SPDX_License_valid {
> > my ($license) = @_;
> >
> >
> >
> >
> > - return 1 if (!$tree || which("python") eq "" || !(-e
> > "$root/scripts/spdxcheck.py") || !(-e "$root/.git"));
> > + return 1 if (!$tree || which("python3") eq "" || !(-e
> > "$root/scripts/spdxcheck.py") || !(-e "$root/.git"));
> >
> >
> >
> >
> > my $root_path = abs_path($root);
> > - my $status = `cd "$root_path"; echo "$license" | python
> > scripts/spdxcheck.py -`;
> > + my $status = `cd "$root_path"; echo "$license" | python3
> > scripts/spdxcheck.py -`;
> > return 0 if ($status ne "");
> > return 1;
> > }
> > diff --git a/scripts/spdxcheck.py b/scripts/spdxcheck.py
> > index 6374e078a5..0f81337394 100755
> > --- a/scripts/spdxcheck.py
> > +++ b/scripts/spdxcheck.py
> > @@ -1,4 +1,4 @@
> > -#!/usr/bin/env python
> > +#!/usr/bin/env python3
> > # SPDX-License-Identifier: GPL-2.0
> > # Copyright Thomas Gleixner
> >
> >
> >
> >
> > --
> > 2.31.0
> >
>
>
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[PATCH] ARM: i.MX: demote reset reason print to debug level
The i.MX reset reason is not really helpful on its own, as it needs
to be augmented with other information like the watchdog state to get
the real system reset reason. As it stands this log is more confusing
than answering any questions a user might have.
Demote the log to debug level to stop this confusion.
Signed-off-by: Lucas Stach
---
arch/arm/mach-imx/imx.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-imx/imx.c b/arch/arm/mach-imx/imx.c
index 3d8c55c54ecd..bd7e9ac42320 100644
--- a/arch/arm/mach-imx/imx.c
+++ b/arch/arm/mach-imx/imx.c
@@ -209,6 +209,6 @@ void imx_set_reset_reason(void __iomem *srsr,
reset_source_set_prinst(type, RESET_SOURCE_DEFAULT_PRIORITY, instance);
- pr_info("i.MX reset reason %s (SRSR: 0x%08x)\n",
- reset_source_to_string(type), reg);
+ pr_debug("i.MX reset reason %s (SRSR: 0x%08x)\n",
+reset_source_to_string(type), reg);
}
--
2.29.2
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Re: [PATCH 7/8] ARM: mmu-early: map no-map entries XN & uncached
Am Dienstag, dem 20.04.2021 um 09:57 +0200 schrieb Rouven Czerwinski:
> Ensure that reserved map entries with the no-map flag are marked as
> uncached and non-execute during the early MMU initialization.
>
> Signed-off-by: Rouven Czerwinski
> ---
> arch/arm/cpu/mmu-early.c | 12
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm/cpu/mmu-early.c b/arch/arm/cpu/mmu-early.c
> index b985aa455f..63cf61b2aa 100644
> --- a/arch/arm/cpu/mmu-early.c
> +++ b/arch/arm/cpu/mmu-early.c
> @@ -3,9 +3,11 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> +#include
>
>
>
>
> #include "mmu.h"
>
>
>
>
> @@ -24,6 +26,8 @@ static inline void map_region(unsigned long start, unsigned
> long size,
> void mmu_early_enable(unsigned long membase, unsigned long memsize,
> unsigned long _ttb)
> {
> + struct pbl_reserved_memory* res_mem = get_pbl_reserved_memory();
> + int i;
> ttb = (uint32_t *)_ttb;
>
>
>
>
> arm_set_cache_functions();
> @@ -58,6 +62,14 @@ void mmu_early_enable(unsigned long membase, unsigned long
> memsize,
> /* maps main memory as cachable */
> map_region(membase, memsize, PMD_SECT_DEF_CACHED);
>
>
>
>
> + for(i=0; i < get_pbl_reserved_memory_num(); i++) {
> + if(res_mem->flag & FDT_RES_MEM_FLAG_NOMAP)
Quite a bit of missing whitespace in the two lines above.
Also the variables at the top of the function don't form a reverse
christmas tree, but that isn't part of the coding style, so I don't
complain about that. ;)
Regards,
Lucas
> + map_region(res_mem->base, res_mem->size,
> +PMD_SECT_DEF_UNCACHED | PMD_SECT_XN);
> + res_mem++;
> + }
> +
> +
> /*
> * With HAB enabled we call into the ROM code later in
> imx6_hab_get_status().
> * Map the ROM cached which has the effect that the XN bit is not set.
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Re: [PATCH v2] ARM: i.MX: sabresd: Add support for i.MX6QP board variant
Am Donnerstag, dem 15.04.2021 um 17:12 +0200 schrieb Sascha Hauer:
> On Thu, Apr 15, 2021 at 04:59:30PM +0200, Lucas Stach wrote:
> > Am Donnerstag, dem 15.04.2021 um 16:03 +0200 schrieb Sascha Hauer:
> > > The SabreSD comes with different SoC variants. This patch adds support
> > > for the i.MX6QP based board. the DCD data has been taken from U-Boot
> > > 2021.04
> > >
> > > Signed-off-by: Sascha Hauer
> > > ---
> > >
> > [...]
> > > new file mode 100644
> > > index 00..52cc8aa73b
> > > --- /dev/null
> > > +++ b/arch/arm/dts/imx6qp-sabresd.dts
> > > @@ -0,0 +1,42 @@
> > > +/*
> > > + * Copyright 2012 Freescale Semiconductor, Inc.
> > > + * Copyright 2011 Linaro Ltd.
> > > + *
> > > + * The code contained herein is licensed under the GNU General Public
> > > + * License. You may obtain a copy of the GNU General Public License
> > > + * Version 2 or later at the following locations:
> > > + *
> > > + * http://www.opensource.org/licenses/gpl-license.html
> > > + * http://www.gnu.org/copyleft/gpl.html
> > > + */
> > > +
> > > +#include
> > > +
> > > +/ {
> > > + model = "Freescale i.MX6 Quad SABRE Smart Device Board";
> > > + compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
> >
> > I'm not sure I like this overwriting of the compatible string. AFAICS
> > we don't have any instances for "fsl,imx6qp" compatible checks in
> > either Barebox or Linux kernel, so it shouldn't cause any immediate
> > damage, but this still feels wrong.
>
> It's overwritten with the same strings as the included upstream dts has.
> Anyway, as you say overwriting them here seems wrong. I removed it.
You had me confused for bit here, so I just checked and the compatible
in the included upstream dts is different, as expected:
compatible = "fsl,imx6qp-sabresd", "fsl,imx6qp";
So now that you removed those lines, does you board file need fixing
for the different compatibles?
Regards,
Lucas
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Re: [PATCH v2] ARM: i.MX: sabresd: Add support for i.MX6QP board variant
Am Donnerstag, dem 15.04.2021 um 16:03 +0200 schrieb Sascha Hauer:
> The SabreSD comes with different SoC variants. This patch adds support
> for the i.MX6QP based board. the DCD data has been taken from U-Boot
> 2021.04
>
> Signed-off-by: Sascha Hauer
> ---
>
[...]
> new file mode 100644
> index 00..52cc8aa73b
> --- /dev/null
> +++ b/arch/arm/dts/imx6qp-sabresd.dts
> @@ -0,0 +1,42 @@
> +/*
> + * Copyright 2012 Freescale Semiconductor, Inc.
> + * Copyright 2011 Linaro Ltd.
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +#include
> +
> +/ {
> + model = "Freescale i.MX6 Quad SABRE Smart Device Board";
> + compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
I'm not sure I like this overwriting of the compatible string. AFAICS
we don't have any instances for "fsl,imx6qp" compatible checks in
either Barebox or Linux kernel, so it shouldn't cause any immediate
damage, but this still feels wrong.
Regards,
Lucas
> +
> + chosen {
> + stdout-path = &uart1;
> +
> + environment {
> + compatible = "barebox,environment";
> + device-path = &environment_usdhc3;
> + };
> + };
> +};
> +
> +&usdhc3 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + partition@0 {
> + label = "barebox";
> + reg = <0x0 0xe>;
> + };
> +
> + environment_usdhc3: partition@e {
> + label = "barebox-environment";
> + reg = <0xe 0x2>;
> + };
> +};
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Re: [PATCH 3/5] kvx: Implement dma handling primitives
Hi Jules,
Am Dienstag, dem 02.03.2021 um 11:58 +0100 schrieb Jules Maselbas:
> Hi Lucas and Ahmad,
>
> On Tue, Mar 02, 2021 at 11:14:09AM +0100, Lucas Stach wrote:
> > Am Dienstag, dem 02.03.2021 um 09:37 +0100 schrieb Ahmad Fatoum:
> > > Hello Jules, Yann,
> > >
> > > On 01.03.21 16:58, Jules Maselbas wrote:
> > > > From: Yann Sionneau
> > > Some comments inline. I am not a cache cohereny expert, so take
> > > it with a grain of salt.
> > >
> > > > +static inline void *dma_alloc_coherent(size_t size, dma_addr_t
> > > > *dma_handle)
> > > > +{
> > > > + void *ret = xmemalign(PAGE_SIZE, size);
> > > > +
> > > > + if (dma_handle)
> > > > + *dma_handle = (dma_addr_t)(uintptr_t)ret;
> > > > +
> > > > + return ret;
> > > > +}
> > >
> > > This would imply that the CPU barebox is booting is coherent with all
> > >
> > > devices that barebox needs to access. Is that the case?
> > >
> > > (See below)
> > >
> This is bogus, memory is not coherent with all devices, this should be
> handled by the mmu, which is currently not supported in our barebox port.
> Using this can lead to coherency issues. We can either drop this
> function, so that is leads to an error at link time, or add a call to
> BUG for a runtime error.
>
> Right now we aren't using any driver that require dma_alloc_coherent,
> but we use drivers that requires dma_alloc and dma_map_single instead.
I would vote for a BUILD_BUG_ON_MSG in this function, so you get a
compile time error and you can state what needs to be done in order to
get rid of the failure.
> > > > +/*
> > > > + * The implementation of arch should follow the following rules:
> > > > + * map for_cpu for_device unmap
> > > > + * TO_DEV writeback nonewriteback none
> > > > + * FROM_DEVinvalidate invalidate(*) invalidate
> > > > invalidate(*)
> > > > + * BIDIR writeback invalidate writeback
> > > > invalidate
> > > > + *
> > > > + * (*) - only necessary if the CPU speculatively prefetches.
> > > > + *
> > > > + * (see https://lkml.org/lkml/2018/5/18/979)
> > > > + */
> > > > +
> > > > +void dma_sync_single_for_device(dma_addr_t addr, size_t size,
> > > > + enum dma_data_direction dir)
> > > > +{
> > > > + switch (dir) {
> > > > + case DMA_FROM_DEVICE:
> > > > + kvx_dcache_invalidate_mem_area(addr, size);
> >
> > Why do you need to explicitly invalidate, but not flush? Even if the
> > CPU speculatively prefetches, the coherency protocol should make sure
> > to invalidate the speculatively loaded lines, right?
> Since we don't have a coherent memory, here we need to invalidate L1
> dcache to let the CPU see deivce's writes in memory.
> Also every write goes through the cache, flush is not required.
Ah, if all your caches are write-through that makes sense. Can you add
a comment somewhere stating that this implementation assumes WT caches
on KVX? This way we can avoid the confusion Ahamd and myself fell into
when glancing over the code.
Regards,
Lucas
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Re: [PATCH 3/5] kvx: Implement dma handling primitives
Am Dienstag, dem 02.03.2021 um 09:37 +0100 schrieb Ahmad Fatoum:
> Hello Jules, Yann,
>
> On 01.03.21 16:58, Jules Maselbas wrote:
> > From: Yann Sionneau
>
> Some comments inline. I am not a cache cohereny expert, so take
> it with a grain of salt.
>
> >
> > Signed-off-by: Yann Sionneau
> > Signed-off-by: Jules Maselbas
> > ---
>
> > --- /dev/null
> > +++ b/arch/kvx/include/asm/dma.h
> > @@ -0,0 +1,35 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/* SPDX-FileCopyrightText: 2021 Yann Sionneau ,
> > Kalray Inc. */
> > +
> > +#ifndef __ASM_DMA_H
> > +#define __ASM_DMA_H
> > +
> > +#include
> > +
> > +#define KVX_DDR_32BIT_RAM_WINDOW_BA(0x8000ULL)
> > +#define KVX_DDR_64BIT_RAM_WINDOW_BA(0x1ULL)
> > +#define MAX_32BIT_ADDR (0xULL)
> > +
> > +#define dma_alloc dma_alloc
> > +static inline void *dma_alloc(size_t size)
> > +{
> > + return xmemalign(64, ALIGN(size, 64));
> > +}
> > +
> > +static inline void *dma_alloc_coherent(size_t size, dma_addr_t *dma_handle)
> > +{
> > + void *ret = xmemalign(PAGE_SIZE, size);
> > +
> > + if (dma_handle)
> > + *dma_handle = (dma_addr_t)(uintptr_t)ret;
> > +
> > + return ret;
> > +}
>
> This would imply that the CPU barebox is booting is coherent with all
>
> devices that barebox needs to access. Is that the case?
>
> (See below)
>
> > +
> > +static inline void dma_free_coherent(void *mem, dma_addr_t dma_handle,
> > +size_t size)
> > +{
> > + free(mem);
> > +}
> > +
> > +#endif /* __ASM_DMA_H */
> > diff --git a/arch/kvx/include/asm/sys_arch.h
> > b/arch/kvx/include/asm/sys_arch.h
> > index 9df32c4e7..ce07a5598 100644
> > --- a/arch/kvx/include/asm/sys_arch.h
> > +++ b/arch/kvx/include/asm/sys_arch.h
> > @@ -11,6 +11,9 @@
> > #define EXCEPTION_STRIDE 0x40
> > #define EXCEPTION_ALIGNMENT0x100
> >
> >
> >
> >
> >
> >
> >
> >
> > +#define kvx_cluster_id() ((int) \
> > + ((kvx_sfr_get(PCR) & KVX_SFR_PCR_CID_MASK) \
> > + >> KVX_SFR_PCR_CID_SHIFT))
> > #define KVX_SFR_START(__sfr_reg) \
> > (KVX_SFR_## __sfr_reg ## _SHIFT)
> >
> >
> >
> >
> >
> >
> >
> >
> > diff --git a/arch/kvx/lib/Makefile b/arch/kvx/lib/Makefile
> > index d271ebccf..c730e1c23 100644
> > --- a/arch/kvx/lib/Makefile
> > +++ b/arch/kvx/lib/Makefile
> > @@ -3,4 +3,4 @@
> > # Copyright (C) 2019 Kalray Inc.
> > #
> >
> >
> >
> >
> >
> >
> >
> >
> > -obj-y += cpuinfo.o board.o dtb.o poweroff.o bootm.o setjmp.o cache.o
> > +obj-y += cpuinfo.o board.o dtb.o poweroff.o bootm.o setjmp.o cache.o
> > dma-default.o
> > diff --git a/arch/kvx/lib/dma-default.c b/arch/kvx/lib/dma-default.c
> > new file mode 100644
> > index 0..755a8c66f
> > --- /dev/null
> > +++ b/arch/kvx/lib/dma-default.c
> > @@ -0,0 +1,91 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +// SPDX-FileCopyrightText: 2021 Yann Sionneau ,
> > Kalray Inc.
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +/*
> > + * The implementation of arch should follow the following rules:
> > + * map for_cpu for_device unmap
> > + * TO_DEV writeback nonewriteback none
> > + * FROM_DEVinvalidate invalidate(*) invalidate
> > invalidate(*)
> > + * BIDIR writeback invalidate writeback invalidate
> > + *
> > + * (*) - only necessary if the CPU speculatively prefetches.
> > + *
> > + * (see https://lkml.org/lkml/2018/5/18/979)
> > + */
> > +
> > +void dma_sync_single_for_device(dma_addr_t addr, size_t size,
> > + enum dma_data_direction dir)
> > +{
> > + switch (dir) {
> > + case DMA_FROM_DEVICE:
> > + kvx_dcache_invalidate_mem_area(addr, size);
Why do you need to explicitly invalidate, but not flush? Even if the
CPU speculatively prefetches, the coherency protocol should make sure
to invalidate the speculatively loaded lines, right?
> > + break;
> > + case DMA_TO_DEVICE:
> > + case DMA_BIDIRECTIONAL:
> > + /* allow device to read buffer written by CPU */
> > + wmb();
>
> If the interconnect was indeed coherent, like dma_alloc_coherent
> above hints, you wouldn't need any barriers here..?
Coherency does not imply strict ordering, so the barriers are in fact
correct, as the CPU write buffers and/or the interconnect can still
change the ordering of the writes as seen by a remote observer.
> > + break;
> > + default:
> > + BUG();
> > + }
> > +}
> > +
> > +void dma_sync_single_for_cpu(dma_addr_t addr, size_t size,
> > + enum dma_data_direction dir)
> > +{
> > + switch (dir) {
> > + case DMA_FROM_DEVICE:
> > + case DMA_TO_DEVICE:
> > + break;
> > + case DMA_BIDIRECTIONAL:
> > + kvx_dcache_invalidate_mem_area(addr, size);
> > + break;
[PATCH] ARM: imx8mq: reclock ARM PLL to 800MHz
The BootROM sets up the ARM PLL to run at 1.6GHz and then uses the divider after the PLL the achieve a CPU clock rate of 800MHz. New Linux kernels (>= 5.8) switch to a clock path that bypasses the divider, as the divider should not be used for CPU clock frequencies >1GHz. If the BootROM setup is left unchanged this causes the CPU clock to jump to the full 1.6GHz until CPUfreq takes over and reprograms the PLL. This rate is outside of the chip specification and leads to crashes. Fix this by reclocking the ARM PLL to 800MHz. Signed-off-by: Lucas Stach --- arch/arm/dts/imx8mq.dtsi | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi index ec8347f38fa8..e56cdfe1308e 100644 --- a/arch/arm/dts/imx8mq.dtsi +++ b/arch/arm/dts/imx8mq.dtsi @@ -17,7 +17,9 @@ <&clk IMX8MQ_CLK_USDHC2>, <&clk IMX8MQ_CLK_ENET_AXI>, <&clk IMX8MQ_CLK_ENET_TIMER>, - <&clk IMX8MQ_CLK_ENET_REF>; + <&clk IMX8MQ_CLK_ENET_REF>, + <&clk IMX8MQ_ARM_PLL>, + <&clk IMX8MQ_CLK_A53_DIV>; assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_400M>, <&clk IMX8MQ_SYS1_PLL_400M>, @@ -29,5 +31,7 @@ <2>, <26600>, <2500>, - <12500>; + <12500>, + <8>, + <8>; }; -- 2.29.2 ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH 5/5] ARM: i.MX: add MNT Reform board support
Hi Antony, Am Montag, dem 28.12.2020 um 09:48 +0300 schrieb Antony Pavlov: > On Sun, 27 Dec 2020 22:50:42 +0100 > Lucas Stach wrote: > > Hi! > > I'm very glad to see that barebox runs on MNT Reform! > > Are you planning to add MIPI DSI display output? Yes, I think I will eventually get around to it. For now the focus is on getting the Linux kernel support into shape for upstream, however. As I needed a convenient way to boot Linux on the device for this task a Barebox port was the logical first step. ;) It may take a while until I circle back to improve the Barebox support. > > The MNT Reform is a DIY Laptop, built around a Boundarydevices i.MX8MQ SoM. > > This adds a pretty minimal support, as there is no upstream DT yet. It also > > does not properly abstract the SoM (power supply init in MNT Reform lowlevel > > code and only single DRAM configuration supported), as there are a lot of > > variants of the SoM and I'm only able to test the single one that will be > > shipped with the Reform. > > > > What has been tested to work: > > - SD card > > - eMMC > > - Gigabit network > > - NVMe storage Forgot to mention: USB is also supported. Regards, Lucas > > > > There is a quirk in the board support: the Nitrogen SoM only allows to > > configure one of the BOOT_MODE straps, which means the choices for the boot > > selection are only "boot from fuses", which means eMMC boot and > > "serial boot". As serial boot isn't really useful on the device (requires > > USB A<->A cable with VBUS protection), we rely on the BootROM fallback to > > boot from SD card in this mode. The board support code thus treats the > > bootsource "serial" as SD card boot. > > > > Signed-off-by: Lucas Stach > > --- > > arch/arm/boards/Makefile |1 + > > arch/arm/boards/mnt-reform/Makefile |2 + > > arch/arm/boards/mnt-reform/board.c| 40 + > > .../mnt-reform/flash-header-mnt-reform.imxcfg |6 + > > arch/arm/boards/mnt-reform/lowlevel.c | 187 +++ > > arch/arm/boards/mnt-reform/lpddr4-timing.c| 1012 + > > arch/arm/dts/Makefile |1 + > > arch/arm/dts/imx8mq-mnt-reform2.dts | 223 > > arch/arm/mach-imx/Kconfig |9 + > > images/Makefile.imx |6 + > > 10 files changed, 1487 insertions(+) > > create mode 100644 arch/arm/boards/mnt-reform/Makefile > > create mode 100644 arch/arm/boards/mnt-reform/board.c > > create mode 100644 > > arch/arm/boards/mnt-reform/flash-header-mnt-reform.imxcfg > > create mode 100644 arch/arm/boards/mnt-reform/lowlevel.c > > create mode 100644 arch/arm/boards/mnt-reform/lpddr4-timing.c > > create mode 100644 arch/arm/dts/imx8mq-mnt-reform2.dts > > > ... > > > > > > ___ > > barebox mailing list > > barebox@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/barebox > ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH 1/5] ddr: imx8m: implement i.MX8MQ support
The i.MX8MQ uses a different PLL type than the later i.MX8M family
members, so the PLL setup did not actually work on this SoC. In U-Boot
the used PLL setup routine is a compile time decision. As we want
our DRAM init code to work for multi-image builds, this passes the
SoC type through to the PLL init, so we can use the correct setup
routine depending on the SoC we are running on.
Signed-off-by: Lucas Stach
---
drivers/ddr/imx8m/ddr_init.c | 4 +-
drivers/ddr/imx8m/ddrphy_train.c | 4 +-
drivers/ddr/imx8m/ddrphy_utils.c | 107 ---
include/soc/imx8m/ddr.h | 4 +-
4 files changed, 104 insertions(+), 15 deletions(-)
diff --git a/drivers/ddr/imx8m/ddr_init.c b/drivers/ddr/imx8m/ddr_init.c
index 1cd7b7406dc7..34da44af6446 100644
--- a/drivers/ddr/imx8m/ddr_init.c
+++ b/drivers/ddr/imx8m/ddr_init.c
@@ -62,7 +62,7 @@ static int imx8m_ddr_init(struct dram_timing_info
*dram_timing,
initial_drate = dram_timing->fsp_msg[0].drate;
/* default to the frequency point 0 clock */
- ddrphy_init_set_dfi_clk(initial_drate);
+ ddrphy_init_set_dfi_clk(initial_drate, type);
/* D-aasert the presetn */
reg32_write(src_ddrc_rcr, 0x8F06);
@@ -115,7 +115,7 @@ static int imx8m_ddr_init(struct dram_timing_info
*dram_timing,
*/
pr_debug("ddrphy config start\n");
- ret = ddr_cfg_phy(dram_timing);
+ ret = ddr_cfg_phy(dram_timing, type);
if (ret)
return ret;
diff --git a/drivers/ddr/imx8m/ddrphy_train.c b/drivers/ddr/imx8m/ddrphy_train.c
index 9280c853aa1c..a4677f903c6b 100644
--- a/drivers/ddr/imx8m/ddrphy_train.c
+++ b/drivers/ddr/imx8m/ddrphy_train.c
@@ -31,7 +31,7 @@ void ddr_load_train_code(enum fw_type type)
DDRC_PHY_DMEM, dmem, dsize);
}
-int ddr_cfg_phy(struct dram_timing_info *dram_timing)
+int ddr_cfg_phy(struct dram_timing_info *dram_timing, enum ddrc_type type)
{
struct dram_cfg_param *dram_cfg;
struct dram_fsp_msg *fsp_msg;
@@ -54,7 +54,7 @@ int ddr_cfg_phy(struct dram_timing_info *dram_timing)
for (i = 0; i < dram_timing->fsp_msg_num; i++) {
pr_debug("DRAM PHY training for %dMTS\n", fsp_msg->drate);
/* set dram PHY input clocks to desired frequency */
- ddrphy_init_set_dfi_clk(fsp_msg->drate);
+ ddrphy_init_set_dfi_clk(fsp_msg->drate, type);
/* load the dram training firmware image */
dwc_ddrphy_apb_wr(0xd, 0x0);
diff --git a/drivers/ddr/imx8m/ddrphy_utils.c b/drivers/ddr/imx8m/ddrphy_utils.c
index c48372491015..9a4e1a22ee5e 100644
--- a/drivers/ddr/imx8m/ddrphy_utils.c
+++ b/drivers/ddr/imx8m/ddrphy_utils.c
@@ -214,7 +214,7 @@ static struct imx_int_pll_rate_table *fracpll(u32 freq)
return NULL;
}
-static int dram_pll_init(u32 freq)
+static int dram_frac_pll_init(u32 freq)
{
volatile int i;
u32 tmp;
@@ -261,35 +261,124 @@ static int dram_pll_init(u32 freq)
return 0;
}
-void ddrphy_init_set_dfi_clk(unsigned int drate)
+#define SSCG_PLL_LOCK BIT(31)
+#define SSCG_PLL_DRAM_PLL_CLKE BIT(9)
+#define SSCG_PLL_PDBIT(7)
+#define SSCG_PLL_BYPASS1 BIT(5)
+#define SSCG_PLL_BYPASS2 BIT(4)
+
+#define SSCG_PLL_REF_DIVR2_MASK(0x3f << 19)
+#define SSCG_PLL_REF_DIVR2_VAL(n) (((n) << 19) & SSCG_PLL_REF_DIVR2_MASK)
+#define SSCG_PLL_FEEDBACK_DIV_F1_MASK (0x3f << 13)
+#define SSCG_PLL_FEEDBACK_DIV_F1_VAL(n)(((n) << 13) &
SSCG_PLL_FEEDBACK_DIV_F1_MASK)
+#define SSCG_PLL_FEEDBACK_DIV_F2_MASK (0x3f << 7)
+#define SSCG_PLL_FEEDBACK_DIV_F2_VAL(n)(((n) << 7) &
SSCG_PLL_FEEDBACK_DIV_F2_MASK)
+#define SSCG_PLL_OUTPUT_DIV_VAL_MASK (0x3f << 1)
+#define SSCG_PLL_OUTPUT_DIV_VAL(n) (((n) << 1) &
SSCG_PLL_OUTPUT_DIV_VAL_MASK)
+
+static int dram_sscg_pll_init(u32 freq)
+{
+ u32 val;
+ void __iomem *pll_base = IOMEM(MX8M_ANATOP_BASE_ADDR) + 0x60;
+
+ /* Bypass */
+ setbits_le32(pll_base, SSCG_PLL_BYPASS1 | SSCG_PLL_BYPASS2);
+
+ val = readl(pll_base + 0x8);
+ val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
+SSCG_PLL_FEEDBACK_DIV_F2_MASK |
+SSCG_PLL_FEEDBACK_DIV_F1_MASK |
+SSCG_PLL_REF_DIVR2_MASK);
+
+ switch (freq) {
+ case MHZ(800):
+ val |= SSCG_PLL_OUTPUT_DIV_VAL(0);
+ val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11);
+ val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
+ val |= SSCG_PLL_REF_DIVR2_VAL(29);
+ break;
+ case MHZ(600):
+ val |= SSCG_PLL_OUTPUT_DIV_VAL(1);
+ val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(17);
+ val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
+ val |= SSCG_PLL_REF_DIV
[PATCH 2/5] ddr: imx8m: remove bogus defines
Most of those defines aren't used. Whether DDR_ONE_RANK should be defined
is really dependent on the used DRAM on a specific board, so move this
from the common header into the board DRAM setup.
Signed-off-by: Lucas Stach
---
arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c | 2 ++
include/soc/imx8m/lpddr4_define.h | 7 ---
2 files changed, 2 insertions(+), 7 deletions(-)
diff --git a/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c
b/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c
index 8d6cc389ba9b..e7c01f9cc9a0 100644
--- a/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c
+++ b/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c
@@ -5,6 +5,8 @@
#include
#include
+
+#define DDR_ONE_RANK
#include
static struct dram_cfg_param lpddr4_ddrc_cfg[] = {
diff --git a/include/soc/imx8m/lpddr4_define.h
b/include/soc/imx8m/lpddr4_define.h
index caf5bafb6d02..805357959349 100644
--- a/include/soc/imx8m/lpddr4_define.h
+++ b/include/soc/imx8m/lpddr4_define.h
@@ -6,13 +6,6 @@
#ifndef __LPDDR4_DEFINE_H_
#define __LPDDR4_DEFINE_H_
-#define LPDDR4_DVFS_DBI
-#define DDR_ONE_RANK
-/* #define LPDDR4_DBI_ON */
-#define DFI_BUG_WR
-#define M845S_4GBx2
-#define PRETRAIN
-
/* DRAM MR setting */
#ifdef LPDDR4_DBI_ON
#define LPDDR4_MR3 0xf1
--
2.29.2
___
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[PATCH 4/5] net: phy: at803x: sync RX/TX delay setup with Linux
The RX/TX delay setup was pretty broken in that it only handled
one specific delay case. Sync the whole code with with the Linux
driver to get correct and consistent behavior.
Signed-off-by: Lucas Stach
---
drivers/net/phy/at803x.c | 88 ++--
1 file changed, 76 insertions(+), 12 deletions(-)
diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c
index 016ed97020ad..e0e147b1913e 100644
--- a/drivers/net/phy/at803x.c
+++ b/drivers/net/phy/at803x.c
@@ -27,8 +27,10 @@
#define AT803X_FUNC_DATA 0x4003
#define AT803X_DEBUG_ADDR 0x1D
#define AT803X_DEBUG_DATA 0x1E
-#define AT803X_DEBUG_SYSTEM_MODE_CTRL 0x05
-#define AT803X_DEBUG_RGMII_TX_CLK_DLY (1 << 8)
+#define AT803X_DEBUG_REG_0 0x00
+#define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15)
+#define AT803X_DEBUG_REG_5 0x05
+#define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8)
/* AT803x supports either the XTAL input pad, an internal PLL or the
* DSP as clock reference for the clock output pad. The XTAL reference
@@ -74,6 +76,58 @@ struct at803x_priv {
u16 clk_25m_mask;
};
+static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg)
+{
+ int ret;
+
+ ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
+ if (ret < 0)
+ return ret;
+
+ return phy_read(phydev, AT803X_DEBUG_DATA);
+}
+
+static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
+u16 clear, u16 set)
+{
+ u16 val;
+ int ret;
+
+ ret = at803x_debug_reg_read(phydev, reg);
+ if (ret < 0)
+ return ret;
+
+ val = ret & 0x;
+ val &= ~clear;
+ val |= set;
+
+ return phy_write(phydev, AT803X_DEBUG_DATA, val);
+}
+
+static int at803x_enable_rx_delay(struct phy_device *phydev)
+{
+ return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 0,
+AT803X_DEBUG_RX_CLK_DLY_EN);
+}
+
+static int at803x_enable_tx_delay(struct phy_device *phydev)
+{
+ return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 0,
+AT803X_DEBUG_TX_CLK_DLY_EN);
+}
+
+static int at803x_disable_rx_delay(struct phy_device *phydev)
+{
+ return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0,
+AT803X_DEBUG_RX_CLK_DLY_EN, 0);
+}
+
+static int at803x_disable_tx_delay(struct phy_device *phydev)
+{
+ return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5,
+AT803X_DEBUG_TX_CLK_DLY_EN, 0);
+}
+
static bool at803x_match_phy_id(struct phy_device *phydev, u32 phy_id)
{
struct phy_driver *drv = to_phy_driver(phydev->dev.driver);
@@ -196,16 +250,26 @@ static int at803x_config_init(struct phy_device *phydev)
if (ret < 0)
return ret;
- if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
- ret = phy_write(phydev, AT803X_DEBUG_ADDR,
- AT803X_DEBUG_SYSTEM_MODE_CTRL);
- if (ret)
- return ret;
- ret = phy_write(phydev, AT803X_DEBUG_DATA,
- AT803X_DEBUG_RGMII_TX_CLK_DLY);
- if (ret)
- return ret;
- }
+ /* The RX and TX delay default is:
+* after HW reset: RX delay enabled and TX delay disabled
+* after SW reset: RX delay enabled, while TX delay retains the
+* value before reset.
+*/
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
+ ret = at803x_enable_rx_delay(phydev);
+ else
+ ret = at803x_disable_rx_delay(phydev);
+ if (ret < 0)
+ return ret;
+
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
+ ret = at803x_enable_tx_delay(phydev);
+ else
+ ret = at803x_disable_tx_delay(phydev);
+ if (ret < 0)
+ return ret;
return at803x_clk_out_config(phydev);
}
--
2.29.2
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[PATCH 5/5] ARM: i.MX: add MNT Reform board support
The MNT Reform is a DIY Laptop, built around a Boundarydevices i.MX8MQ SoM.
This adds a pretty minimal support, as there is no upstream DT yet. It also
does not properly abstract the SoM (power supply init in MNT Reform lowlevel
code and only single DRAM configuration supported), as there are a lot of
variants of the SoM and I'm only able to test the single one that will be
shipped with the Reform.
What has been tested to work:
- SD card
- eMMC
- Gigabit network
- NVMe storage
There is a quirk in the board support: the Nitrogen SoM only allows to
configure one of the BOOT_MODE straps, which means the choices for the boot
selection are only "boot from fuses", which means eMMC boot and
"serial boot". As serial boot isn't really useful on the device (requires
USB A<->A cable with VBUS protection), we rely on the BootROM fallback to
boot from SD card in this mode. The board support code thus treats the
bootsource "serial" as SD card boot.
Signed-off-by: Lucas Stach
---
arch/arm/boards/Makefile |1 +
arch/arm/boards/mnt-reform/Makefile |2 +
arch/arm/boards/mnt-reform/board.c| 40 +
.../mnt-reform/flash-header-mnt-reform.imxcfg |6 +
arch/arm/boards/mnt-reform/lowlevel.c | 187 +++
arch/arm/boards/mnt-reform/lpddr4-timing.c| 1012 +
arch/arm/dts/Makefile |1 +
arch/arm/dts/imx8mq-mnt-reform2.dts | 223
arch/arm/mach-imx/Kconfig |9 +
images/Makefile.imx |6 +
10 files changed, 1487 insertions(+)
create mode 100644 arch/arm/boards/mnt-reform/Makefile
create mode 100644 arch/arm/boards/mnt-reform/board.c
create mode 100644 arch/arm/boards/mnt-reform/flash-header-mnt-reform.imxcfg
create mode 100644 arch/arm/boards/mnt-reform/lowlevel.c
create mode 100644 arch/arm/boards/mnt-reform/lpddr4-timing.c
create mode 100644 arch/arm/dts/imx8mq-mnt-reform2.dts
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index 81c228efd614..f8cdd90ed6e6 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -178,3 +178,4 @@ obj-$(CONFIG_MACH_ZII_IMX7D_DEV)+=
zii-imx7d-dev/
obj-$(CONFIG_MACH_WAGO_PFC_AM35XX) += wago-pfc-am35xx/
obj-$(CONFIG_MACH_LS1046ARDB) += ls1046ardb/
obj-$(CONFIG_MACH_TQMLS1046A) += tqmls1046a/
+obj-$(CONFIG_MACH_MNT_REFORM) += mnt-reform/
diff --git a/arch/arm/boards/mnt-reform/Makefile
b/arch/arm/boards/mnt-reform/Makefile
new file mode 100644
index ..a3da88fbe68f
--- /dev/null
+++ b/arch/arm/boards/mnt-reform/Makefile
@@ -0,0 +1,2 @@
+obj-y += board.o
+lwl-y += lowlevel.o lpddr4-timing.o
\ No newline at end of file
diff --git a/arch/arm/boards/mnt-reform/board.c
b/arch/arm/boards/mnt-reform/board.c
new file mode 100644
index ..e2d628586a50
--- /dev/null
+++ b/arch/arm/boards/mnt-reform/board.c
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Lucas Stach
+ */
+
+#include
+#include
+#include
+#include
+
+static int mnt_reform_probe(struct device_d *dev)
+{
+ int emmc_bbu_flag = 0;
+ int sd_bbu_flag = 0;
+
+ if (bootsource_get() == BOOTSOURCE_MMC) {
+ of_device_enable_path("/chosen/environment-emmc");
+ emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT;
+ } else {
+ of_device_enable_path("/chosen/environment-sd");
+ sd_bbu_flag = BBU_HANDLER_FLAG_DEFAULT;
+ }
+
+ imx8m_bbu_internal_mmc_register_handler("SD", "/dev/mmc1.barebox",
sd_bbu_flag);
+ imx8m_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc0",
emmc_bbu_flag);
+
+ return 0;
+}
+
+static const struct of_device_id mnt_reform_of_match[] = {
+ { .compatible = "mnt,reform2"},
+ { /* sentinel */ },
+};
+
+static struct driver_d mnt_reform_board_driver = {
+ .name = "board-mnt-reform",
+ .probe = mnt_reform_probe,
+ .of_compatible = DRV_OF_COMPAT(mnt_reform_of_match),
+};
+device_platform_driver(mnt_reform_board_driver);
diff --git a/arch/arm/boards/mnt-reform/flash-header-mnt-reform.imxcfg
b/arch/arm/boards/mnt-reform/flash-header-mnt-reform.imxcfg
new file mode 100644
index ..80ce03e22c3a
--- /dev/null
+++ b/arch/arm/boards/mnt-reform/flash-header-mnt-reform.imxcfg
@@ -0,0 +1,6 @@
+soc imx8mq
+
+loadaddr 0x007E1000
+max_load_size 0x3F000
+ivtofs 0x400
+#include
diff --git a/arch/arm/boards/mnt-reform/lowlevel.c
b/arch/arm/boards/mnt-reform/lowlevel.c
new file mode 100644
index ..268dfb611aa8
--- /dev/null
+++ b/arch/arm/boards/mnt-reform/lowlevel.c
@@ -0,0 +1,187 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Lucas Stach
+ */
+
+#include
+#include
+#include
+#include
