[PATCH 1/4] commands: Kconfig: Remove HW ECC dependency from nandtest
NAND_ECC_HW is no longer optional so remove the dependency from nandtest. Otherwise nandtest won't be build for HW ECC boards. Signed-off-by: Stefan Riedmueller --- commands/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/commands/Kconfig b/commands/Kconfig index 6d84c956e576..8e8b5a926fbb 100644 --- a/commands/Kconfig +++ b/commands/Kconfig @@ -1884,7 +1884,6 @@ config CMD_NANDTEST tristate depends on NAND depends on PARTITION - depends on NAND_ECC_HW || NAND_ECC_SOFT prompt "nandtest" help NAND flash memory test -- 2.25.1 ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH 3/4] mtd: nand_msx: Implement ooblayout ops
The default ooblayout ops do not work on nand_mxs devices and can lead
to an unresponsible system when doing a 'nand -i' on that device.
Thus implement the ooblayout ops for the nand_mxs driver separately.
Since writing the oob area is not supported simply return the whole oob
area as ecc.
Signed-off-by: Stefan Riedmueller
---
drivers/mtd/nand/nand_mxs.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/drivers/mtd/nand/nand_mxs.c b/drivers/mtd/nand/nand_mxs.c
index 96ae71364efb..285ae3c121b6 100644
--- a/drivers/mtd/nand/nand_mxs.c
+++ b/drivers/mtd/nand/nand_mxs.c
@@ -269,6 +269,33 @@ static void mxs_nand_return_dma_descs(struct mxs_nand_info
*info)
info->desc_index = 0;
}
+/*
+ * We don't support writing the oob area so simply return the whole oob
+ * as ECC.
+ */
+static int mxs_nand_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobregion)
+{
+ if (section)
+ return -ERANGE;
+
+ oobregion->offset = 0;
+ oobregion->length = mtd->oobsize;
+
+ return 0;
+}
+
+static int mxs_nand_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobregion)
+{
+ return -ERANGE;
+}
+
+static const struct mtd_ooblayout_ops mxs_nand_ooblayout_ops = {
+ .ecc = mxs_nand_ooblayout_ecc,
+ .free = mxs_nand_ooblayout_free,
+};
+
static uint32_t mxs_nand_ecc_chunk_cnt(uint32_t page_data_size)
{
return page_data_size / MXS_NAND_CHUNK_DATA_CHUNK_SIZE;
@@ -2218,6 +2245,8 @@ static int mxs_nand_probe(struct device_d *dev)
if (err)
goto err2;
+ mtd_set_ooblayout(mtd, &mxs_nand_ooblayout_ops);
+
mxs_nand_scan_bbt(chip);
err = add_mtd_nand_device(mtd, "nand");
--
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[PATCH 2/4] nandtest: Fix status print for NAND which size exceeds 4 GB
Nandsize can be larger than 4 GB. So during status print the number of
blocks calculation needs to use 64 bit division.
Signed-off-by: Stefan Riedmueller
---
commands/nandtest.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/commands/nandtest.c b/commands/nandtest.c
index bfe4c4c0ed03..1bb59c7fdba5 100644
--- a/commands/nandtest.c
+++ b/commands/nandtest.c
@@ -178,12 +178,14 @@ static int erase_and_write(loff_t ofs, unsigned char
*data,
}
/* Print stats of nandtest. */
-static void print_stats(int nr_passes, int length)
+static void print_stats(int nr_passes, loff_t length)
{
unsigned int i;
+ uint64_t blocks = (uint64_t)length;
+
+ do_div(blocks, meminfo.erasesize);
printf(" Summary \n");
- printf("Tested blocks : %d\n", (length/meminfo.erasesize)
- * nr_passes);
+ printf("Tested blocks : %lld\n", blocks * nr_passes);
for (i = 0; i < MAX_ECC_BITS; i++)
printf("ECC %d bit error(s) : %u\n", i + 1, ecc_stats[i]);
--
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[PATCH 4/4] imx-bbu-nand-fcb: Inform user if the barebox partition is too small
Show an error message and return an error code if the barebox partition
is too small. This can easily happen when having large erasoblocks since
all four FCB copies need a separate eraseblock.
Signed-off-by: Stefan Riedmueller
---
common/imx-bbu-nand-fcb.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/common/imx-bbu-nand-fcb.c b/common/imx-bbu-nand-fcb.c
index 0e008c6bc2c0..4e680a0a51e7 100644
--- a/common/imx-bbu-nand-fcb.c
+++ b/common/imx-bbu-nand-fcb.c
@@ -501,7 +501,8 @@ static int imx_bbu_firmware_start_block(struct mtd_info
*mtd, int num)
* @num: The slot number (0 or 1)
*
* This returns the start page for a firmware slot, to be written into the
- * Firmwaren_startingPage field in the FCB.
+ * Firmwaren_startingPage field in the FCB or a negative error code in case
+ * of a failure.
*/
static int imx_bbu_firmware_fcb_start_page(struct mtd_info *mtd, int num)
{
@@ -512,6 +513,11 @@ static int imx_bbu_firmware_fcb_start_page(struct mtd_info
*mtd, int num)
blocksleft = imx_bbu_firmware_max_blocks(mtd);
+ if (blocksleft <= 0) {
+ pr_err("partition size too small for both firmwares\n");
+ return -ENOMEM;
+ }
+
/*
* The ROM only checks for a bad block when advancing the read position,
* but not if the initial block is good, hence we cannot directly point
@@ -1258,7 +1264,15 @@ static int imx_bbu_nand_update(struct bbu_handler
*handler, struct bbu_data *dat
free(fcb);
fcb = xzalloc(sizeof(*fcb));
fcb->Firmware1_startingPage =
imx_bbu_firmware_fcb_start_page(mtd, !used);
+ if (fcb->Firmware1_startingPage < 0) {
+ ret = fcb->Firmware1_startingPage;
+ goto out;
+ }
fcb->Firmware2_startingPage =
imx_bbu_firmware_fcb_start_page(mtd, used);
+ if (fcb->Firmware2_startingPage < 0) {
+ ret = fcb->Firmware2_startingPage;
+ goto out;
+ }
fcb->PagesInFirmware1 = fw_size / mtd->writesize;
fcb->PagesInFirmware2 = fcb->PagesInFirmware1;
--
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[PATCH] net: eth: of_fixup_node: Use reproducible node name for fixup
To be able to fixup older devicetrees, prior to v4.15 where leading
zeros of the unit addresses were removed, use the reproducible name to
find the corresponding nodes.
Signed-off-by: Stefan Riedmueller
---
net/eth.c | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/net/eth.c b/net/eth.c
index 626b35d5cc65..84f99d3aa822 100644
--- a/net/eth.c
+++ b/net/eth.c
@@ -304,7 +304,8 @@ static void eth_of_fixup_node(struct device_node *root,
const char *node_path, int ethid,
const u8 ethaddr[ETH_ALEN])
{
- struct device_node *node;
+ struct device_node *bb_node, *fixup_node;
+ char *name;
int ret;
if (!is_valid_ether_addr(ethaddr)) {
@@ -314,22 +315,25 @@ static void eth_of_fixup_node(struct device_node *root,
}
if (node_path) {
- node = of_find_node_by_path_from(root, node_path);
+ bb_node = of_find_node_by_path_from(0, node_path);
+ name = of_get_reproducible_name(bb_node);
+ fixup_node = of_find_node_by_reproducible_name(root, name);
+ free(name);
} else {
char eth[12];
sprintf(eth, "ethernet%d", ethid);
- node = of_find_node_by_alias(root, eth);
+ fixup_node = of_find_node_by_alias(root, eth);
}
- if (!node) {
+ if (!fixup_node) {
pr_debug("%s: no node to fixup\n", __func__);
return;
}
- ret = of_set_property(node, "mac-address", ethaddr, ETH_ALEN, 1);
+ ret = of_set_property(fixup_node, "mac-address", ethaddr, ETH_ALEN, 1);
if (ret)
pr_err("Setting mac-address property of %s failed with: %s\n",
- node->full_name, strerror(-ret));
+ fixup_node->full_name, strerror(-ret));
}
static int eth_of_fixup(struct device_node *root, void *unused)
--
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[PATCH] mtd: Notify user when erasure of a block failed during erase op
Give the user information about the faulty block when an erase
operation fails with error.
Signed-off-by: Stefan Riedmueller
---
drivers/mtd/core.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/core.c b/drivers/mtd/core.c
index af33ad665c5a..22eb2a056c4e 100644
--- a/drivers/mtd/core.c
+++ b/drivers/mtd/core.c
@@ -222,8 +222,11 @@ static int mtd_op_erase(struct cdev *cdev, loff_t count,
loff_t offset)
printf("Skipping bad block at 0x%08llx\n", addr);
} else {
ret = mtd_erase(mtd, &erase);
- if (ret)
+ if (ret) {
+ printf("%s: failed to erase block at
0x%08llx\n",
+ __func__, addr);
return ret;
+ }
}
addr += mtd->erasesize;
--
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[PATCH 1/2] nand: nand-mxs: Fix marking BBT blocks as bad
Currently the nand-mxs driver uses a hook function to the
mtd->_block_markbad function to allow write access to the OOB bytes only
if it is to mark a block as bad.
This hook is not called when a Bad Block Table block is marked bad since
this routine directly calls nand_markbad_bbm.
The chip->legacy.block_markbad hook gives a driver the ability to
implement a custom block_markbad function. Since this is used by
nand_markbad_bbm, if it exists, replace the mtd->_block_markbad hook by
a chip->legacy.block_markbad function. The gpmi-nand Linux implementation
of this driver uses the same mechanism.
This fixes an issue where marking Bad Block Table blocks as bad fails
with:
NXS NAND: Writing OOB isn't supported
Tested on PHYTEC phyCORE-i.MX 6Q.
Signed-off-by: Stefan Riedmueller
---
drivers/mtd/nand/nand_mxs.c | 87 +++--
1 file changed, 34 insertions(+), 53 deletions(-)
diff --git a/drivers/mtd/nand/nand_mxs.c b/drivers/mtd/nand/nand_mxs.c
index 434da49d3ea9..96ae71364efb 100644
--- a/drivers/mtd/nand/nand_mxs.c
+++ b/drivers/mtd/nand/nand_mxs.c
@@ -215,7 +215,6 @@ struct mxs_nand_info {
uint8_t *data_buf;
uint8_t *oob_buf;
- uint8_t marking_block_bad;
uint8_t raw_oob_mode;
/* Functions with altered behaviour */
@@ -223,8 +222,6 @@ struct mxs_nand_info {
loff_t from, struct mtd_oob_ops *ops);
int (*hooked_write_oob)(struct mtd_info *mtd,
loff_t to, struct mtd_oob_ops *ops);
- int (*hooked_block_markbad)(struct mtd_info *mtd,
- loff_t ofs);
/* DMA descriptors */
struct mxs_dma_desc **desc;
@@ -1073,27 +1070,6 @@ static int mxs_nand_hook_write_oob(struct mtd_info *mtd,
loff_t to,
return ret;
}
-/*
- * Mark a block bad in NAND.
- *
- * This function is a veneer that replaces the function originally installed by
- * the NAND Flash MTD code.
- */
-static int mxs_nand_hook_block_markbad(struct mtd_info *mtd, loff_t ofs)
-{
- struct nand_chip *chip = mtd_to_nand(mtd);
- struct mxs_nand_info *nand_info = chip->priv;
- int ret;
-
- nand_info->marking_block_bad = 1;
-
- ret = nand_info->hooked_block_markbad(mtd, ofs);
-
- nand_info->marking_block_bad = 0;
-
- return ret;
-}
-
/*
* There are several places in this driver where we have to handle the OOB and
* block marks. This is the function where things are the most complicated, so
@@ -1177,36 +1153,14 @@ static int mxs_nand_ecc_read_oob(struct nand_chip
*chip, int page)
*/
static int mxs_nand_ecc_write_oob(struct nand_chip *chip, int page)
{
- struct mtd_info *mtd = nand_to_mtd(chip);
- struct mxs_nand_info *nand_info = chip->priv;
- int column;
- uint8_t block_mark = 0;
-
/*
* There are fundamental incompatibilities between the i.MX GPMI NFC and
* the NAND Flash MTD model that make it essentially impossible to write
* the out-of-band bytes.
-*
-* We permit *ONE* exception. If the *intent* of writing the OOB is to
-* mark a block bad, we can do that.
*/
- if (!nand_info->marking_block_bad) {
- printf("NXS NAND: Writing OOB isn't supported\n");
- return -EIO;
- }
-
- column = nand_info->version == GPMI_VERSION_TYPE_MX23 ? 0 :
mtd->writesize;
- /* Write the block mark. */
- chip->legacy.cmdfunc(chip, NAND_CMD_SEQIN, column, page);
- chip->legacy.write_buf(chip, &block_mark, 1);
- chip->legacy.cmdfunc(chip, NAND_CMD_PAGEPROG, -1, -1);
-
- /* Check if it worked. */
- if (chip->legacy.waitfunc(chip) & NAND_STATUS_FAIL)
- return -EIO;
-
- return 0;
+ printf("MXS NAND: Writing OOB isn't supported\n");
+ return -EIO;
}
/*
@@ -1227,6 +1181,37 @@ static int mxs_nand_block_bad(struct nand_chip *chip ,
loff_t ofs)
return 0;
}
+/*
+ * Mark a block as bad in NAND.
+ */
+static int mxs_nand_block_markbad(struct nand_chip *chip , loff_t ofs)
+{
+ struct mtd_info *mtd = nand_to_mtd(chip);
+ struct mxs_nand_info *nand_info = chip->priv;
+ int column, page, chipnr, status;
+ uint8_t block_mark = 0;
+
+ chipnr = (int)(ofs >> chip->chip_shift);
+ nand_select_target(chip, chipnr);
+
+ column = nand_info->version == GPMI_VERSION_TYPE_MX23 ? 0 :
mtd->writesize;
+ page = (int)(ofs >> chip->page_shift);
+ /* Write the block mark. */
+ chip->legacy.cmdfunc(chip, NAND_CMD_SEQIN, column, page);
+ chip->legacy.write_buf(chip, &block_mark, 1);
+ chip->legacy.cmdfunc(chip, NAND_CMD_PAGEPROG, -1, -1);
+
+ /* Check if it wor
[PATCH] fs: Fix default mount when device already mounted
Let cdev_mount_default return an error in case the device is already
mounted to a different location than the default mount point.
Otherwise the automount routine can get stuck in an infinite loop
spamming:
mounted /dev/mmc0.0 on /mnt/mmc
mounted /dev/mmc0.0 on /mnt/mmc
mounted /dev/mmc0.0 on /mnt/mmc
Signed-off-by: Stefan Riedmueller
---
fs/fs.c | 28 +++-
1 file changed, 19 insertions(+), 9 deletions(-)
diff --git a/fs/fs.c b/fs/fs.c
index 3db24b7b6822..4f2345d22544 100644
--- a/fs/fs.c
+++ b/fs/fs.c
@@ -951,9 +951,10 @@ const char *cdev_get_mount_path(struct cdev *cdev)
/*
* cdev_mount_default - mount a cdev to the default path
*
- * If a cdev is already mounted return the path it's mounted on, otherwise
- * mount it to /mnt/ and return the path. Returns an error pointer
- * on failure.
+ * If a cdev is already mounted to the default mount path return the path
+ * it's mounted on. If it is mounted to any other path return EBUSY.
+ * Otherwise mount it to /mnt/ and return the path. Returns an
+ * error pointer on failure.
*/
const char *cdev_mount_default(struct cdev *cdev, const char *fsoptions)
{
@@ -962,15 +963,24 @@ const char *cdev_mount_default(struct cdev *cdev, const
char *fsoptions)
int ret;
/*
-* If this cdev is already mounted somewhere use this path
-* instead of mounting it again to avoid corruption on the
-* filesystem. Note this ignores eventual fsoptions though.
+* If this cdev is already mounted somewhere other than the
+* default mount path return -EBUSY instead of mounting it
+* again to avoid corruption on the filesystem. Note this
+* ignores eventual fsoptions though. If the cdev is already
+* mounted on the default path just return that path.
*/
path = cdev_get_mount_path(cdev);
- if (path)
- return path;
-
newpath = basprintf("/mnt/%s", cdev->name);
+
+ if (path) {
+ if (strcmp(newpath, path)) {
+ free(newpath);
+ return ERR_PTR(-EBUSY);
+ } else {
+ return path;
+ }
+ }
+
make_directory(newpath);
devpath = basprintf("/dev/%s", cdev->name);
--
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[PATCH 2/2] mtd: nand_bbt: Skip bad blocks when searching for the BBT in NAND
The blocks containing the bad block table can become bad as well. So
make sure to skip any blocks that are marked bad when searching for the
bad block table.
Signed-off-by: Stefan Riedmueller
---
drivers/mtd/nand/nand_bbt.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c
index a86b5b2da38e..0b48373e6a0b 100644
--- a/drivers/mtd/nand/nand_bbt.c
+++ b/drivers/mtd/nand/nand_bbt.c
@@ -528,6 +528,7 @@ static int search_bbt(struct nand_chip *this, uint8_t *buf,
{
u64 targetsize = nanddev_target_size(&this->base);
struct mtd_info *mtd = nand_to_mtd(this);
+ struct nand_bbt_descr *bd = this->badblock_pattern;
int i, chips;
int startblock, block, dir;
int scanlen = mtd->writesize + mtd->oobsize;
@@ -563,6 +564,9 @@ static int search_bbt(struct nand_chip *this, uint8_t *buf,
int actblock = startblock + dir * block;
loff_t offs = (loff_t)actblock << this->bbt_erase_shift;
+ /* Check if block is marked bad */
+ if (scan_block_fast(this, bd, offs, buf))
+ continue;
/* Read first page */
scan_read(this, buf, offs, mtd->writesize, td);
if (!check_pattern(buf, scanlen, mtd->writesize, td)) {
--
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[PATCH v3 7/7] ARM: dts: imx6: phytec: Increase NAND barebox partition size
For NAND flash with eraseblock size 1 MB and more the current
barebox partition size is not sufficient. The 4 FCB copies alone occupy
the 4 MB partition size. Increase the partition size to 16 MB to be fit
for the future and leaving some blocks for bad block handling as well.
Signed-off-by: Stefan Riedmueller
---
Changes in v3:
- Rebased on latest master
---
arch/arm/dts/imx6qdl-phytec-pfla02.dtsi | 6 +++---
arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi | 6 +++---
arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi | 6 +++---
3 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
index 846ebbe6b18b..841ad653b26d 100644
--- a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
@@ -98,17 +98,17 @@
partition@0 {
label = "barebox";
- reg = <0x0 0x40>;
+ reg = <0x0 0x100>;
};
partition@40 {
label = "barebox-environment";
- reg = <0x40 0x10>;
+ reg = <0x100 0x10>;
};
partition@50 {
label = "root";
- reg = <0x50 0x0>;
+ reg = <0x110 0x0>;
};
};
};
diff --git a/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
b/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
index 892bce1fc0ab..5d287258bb6c 100644
--- a/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
+++ b/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
@@ -42,17 +42,17 @@
partition@0 {
label = "barebox";
- reg = <0x0 0x40>;
+ reg = <0x0 0x100>;
};
environment_nand: partition@40 {
label = "barebox-environment";
- reg = <0x40 0x2>;
+ reg = <0x100 0x10>;
};
partition@42 {
label = "root";
- reg = <0x42 0x0>;
+ reg = <0x110 0x0>;
};
};
};
diff --git a/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
b/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
index 69f252b42382..918b62f794b3 100644
--- a/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
+++ b/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
@@ -50,17 +50,17 @@
partition@0 {
label = "barebox";
- reg = <0x0 0x40>;
+ reg = <0x0 0x100>;
};
partition@40 {
label = "barebox-environment";
- reg = <0x40 0x10>;
+ reg = <0x100 0x10>;
};
partition@50 {
label = "root";
- reg = <0x50 0x0>;
+ reg = <0x110 0x0>;
};
};
};
--
2.7.4
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[PATCH v3 5/7] ARM: dts: imx6: phycard: Switch to new partitions binding
The SD card interface is still using the legacy partition binding.
Change this by switching to the new bindings.
Signed-off-by: Stefan Riedmueller
---
Changes in v3:
- Rebased on latest master
---
arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi | 22 +-
1 file changed, 13 insertions(+), 9 deletions(-)
diff --git a/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
b/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
index f1a5e5962362..f17ba7bf808d 100644
--- a/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
+++ b/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
@@ -158,15 +158,19 @@
cd-gpios = <&gpio5 22 0>;
status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
- partition@0 {
- label = "barebox";
- reg = <0x0 0xe>;
- };
- environment_usdhc3: partition@e {
- label = "barebox-environment";
- reg = <0xe 0x2>;
+ partition@0 {
+ label = "barebox";
+ reg = <0x0 0xe>;
+ };
+
+ environment_usdhc3: partition@e {
+ label = "barebox-environment";
+ reg = <0xe 0x2>;
+ };
};
};
--
2.7.4
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[PATCH v3 6/7] ARM: dts: imx6: phycard: Use gpio binding constants
Signed-off-by: Stefan Riedmueller
---
Changes in v3:
- Rebased on latest master
---
arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
b/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
index f17ba7bf808d..892bce1fc0ab 100644
--- a/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
+++ b/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
@@ -4,6 +4,8 @@
* Author: Christian Hemp
*/
+#include
+
/ {
chosen {
environment-nand {
@@ -155,7 +157,7 @@
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
-cd-gpios = <&gpio5 22 0>;
+cd-gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>;
status = "disabled";
partitions {
--
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[PATCH v3 1/7] ARM: dts: imx6: pcaaxl3: Order nodes alphabetically
Bring the device tree nodes in alphabetical order and in this context
also remove the deprecated iomux group.
Signed-off-by: Stefan Riedmueller
---
Changes in v3:
- Rebased on latest master
---
arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi | 182 -
1 file changed, 90 insertions(+), 92 deletions(-)
diff --git a/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi
b/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi
index 66b547ad8eef..db986f87ef26 100644
--- a/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi
+++ b/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi
@@ -17,104 +17,16 @@
compatible = "phytec,imx6q-pcaaxl3", "fsl,imx6q";
chosen {
- environment-sd3 {
- compatible = "barebox,environment";
- device-path = &environment_usdhc3;
- status = "disabled";
- };
-
environment-nand {
compatible = "barebox,environment";
device-path = &environment_nand;
status = "disabled";
};
- };
-};
-
-&i2c1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
-
- eeprom: m24c32@50 {
- compatible = "st,24c32", "at24";
- reg = <0x50>;
- };
-};
-
-&iomuxc {
- pinctrl-names = "default";
-
- imx6q-phytec-pcaaxl3 {
- pinctrl_enet: enetgrp {
- fsl,pins = <
- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
- MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
- MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
- MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
- MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
- MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
- MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
- MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK0x1b0b0
- MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3 0x1b0b0
- MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3 0x1b0b0
- MX6QDL_PAD_KEY_ROW1__ENET_COL 0x1b0b0
- MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2 0x1b0b0
- MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2 0x1b0b0
- MX6QDL_PAD_KEY_COL3__ENET_CRS 0x1b0b0
- MX6QDL_PAD_GPIO_18__ENET_RX_CLK 0x1b0b0
- MX6QDL_PAD_GPIO_19__ENET_TX_ER 0x1b0b0
- >;
- };
-
- pinctrl_gpmi_nand: gpmigrp {
- fsl,pins = <
- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B0xb0b1
- MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B0xb0b1
- MX6QDL_PAD_NANDF_CS1__NAND_CE1_B0xb0b1
- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
- MX6QDL_PAD_NANDF_D0__NAND_DATA000xb0b1
- MX6QDL_PAD_NANDF_D1__NAND_DATA010xb0b1
- MX6QDL_PAD_NANDF_D2__NAND_DATA020xb0b1
- MX6QDL_PAD_NANDF_D3__NAND_DATA030xb0b1
- MX6QDL_PAD_NANDF_D4__NAND_DATA040xb0b1
- MX6QDL_PAD_NANDF_D5__NAND_DATA050xb0b1
- MX6QDL_PAD_NANDF_D6__NAND_DATA060xb0b1
- MX6QDL_PAD_NANDF_D7__NAND_DATA070xb0b1
- MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
- >;
- };
-
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX6QDL_PAD_EIM_D21__I2C1_SCL
0x4001b8b1
- MX6QDL_PAD_EIM_D28__I2C1_SDA
0x4001b8b1
- >;
- };
-
- pinctrl_uart3: uart3grp {
- fsl,pins = &
[PATCH v3 2/7] ARM: dts: imx6: pcaaxl3: Update license and model description
Make use of SPDX license identifiers and update copyright notices and
model descriptions of the phyCARD-i.MX 6 SOM.
Signed-off-by: Stefan Riedmueller
---
Changes in v3:
- Rebased on latest master
---
arch/arm/dts/imx6q-phytec-pbaa03.dts | 13 -
arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi | 13 -
2 files changed, 8 insertions(+), 18 deletions(-)
diff --git a/arch/arm/dts/imx6q-phytec-pbaa03.dts
b/arch/arm/dts/imx6q-phytec-pbaa03.dts
index 5216a2dfe316..8034f90804ec 100644
--- a/arch/arm/dts/imx6q-phytec-pbaa03.dts
+++ b/arch/arm/dts/imx6q-phytec-pbaa03.dts
@@ -1,12 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later)
/*
- * Copyright 2014 Christian Hemp, Phytec Messtechnik GmbH
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ * Copyright (C) 2014 PHYTEC Messtechnik GmbH
+ * Author: Christian Hemp
*/
/dts-v1/;
@@ -16,7 +11,7 @@
#include "imx6q-phytec-pcaaxl3.dtsi"
/ {
- model = "Phytec phyCARD-i.MX6 Quad Carrier-Board";
+ model = "PHYTEC phyCARD-i.MX6 Quad";
compatible = "phytec,imx6q-pbaa03", "phytec,imx6q-pcaaxl3", "fsl,imx6q";
chosen {
diff --git a/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi
b/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi
index db986f87ef26..0dbd5419ba10 100644
--- a/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi
+++ b/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi
@@ -1,19 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later)
/*
- * Copyright 201 Christian Hemp, Phytec Messtechnik GmbH
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ * Copyright (C) 2014 PHYTEC Messtechnik GmbH
+ * Author: Christian Hemp
*/
#include
#include "imx6q.dtsi"
/ {
- model = "Phytec phyCARD-i.MX6 Quad";
+ model = "PHYTEC phyCARD-i.MX6 Quad";
compatible = "phytec,imx6q-pcaaxl3", "fsl,imx6q";
chosen {
--
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[PATCH v3 4/7] ARM: dts: imx6: phycard: Make eeprom configurable
The EEPROM is a configurable option. So make it configurable from the
dts file.
Signed-off-by: Stefan Riedmueller
---
Changes in v3:
- Rebased on latest master
---
arch/arm/dts/imx6q-phytec-phycard.dts| 4
arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi | 1 +
2 files changed, 5 insertions(+)
diff --git a/arch/arm/dts/imx6q-phytec-phycard.dts
b/arch/arm/dts/imx6q-phytec-phycard.dts
index 09106f7d4dda..c06461c2c73d 100644
--- a/arch/arm/dts/imx6q-phytec-phycard.dts
+++ b/arch/arm/dts/imx6q-phytec-phycard.dts
@@ -23,6 +23,10 @@
};
};
+&eeprom {
+ status = "okay";
+};
+
&fec {
status = "okay";
};
diff --git a/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
b/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
index 6d963f191024..f1a5e5962362 100644
--- a/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
+++ b/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
@@ -63,6 +63,7 @@
eeprom: m24c32@50 {
compatible = "st,24c32", "at24";
reg = <0x50>;
+ status = "disabled";
};
};
--
2.7.4
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[PATCH v3 3/7] ARM: dts: imx6: pcaaxl3: Make use of the simpler name phycard
Use the simpler name phycard instead of the article number pcaaxl3
for device tree file names and image names of the phyCARD-i.MX 6.
Signed-off-by: Stefan Riedmueller
---
Changes in v3:
- Rebased on latest master
---
arch/arm/boards/phytec-som-imx6/lowlevel.c | 6 +++---
arch/arm/dts/Makefile | 2 +-
arch/arm/dts/{imx6q-phytec-pbaa03.dts => imx6q-phytec-phycard.dts} | 6 +-
.../{imx6q-phytec-pcaaxl3.dtsi => imx6qdl-phytec-phycard-som.dtsi} | 6 --
images/Makefile.imx | 6 +++---
5 files changed, 12 insertions(+), 14 deletions(-)
rename arch/arm/dts/{imx6q-phytec-pbaa03.dts => imx6q-phytec-phycard.dts} (83%)
rename arch/arm/dts/{imx6q-phytec-pcaaxl3.dtsi =>
imx6qdl-phytec-phycard-som.dtsi} (96%)
diff --git a/arch/arm/boards/phytec-som-imx6/lowlevel.c
b/arch/arm/boards/phytec-som-imx6/lowlevel.c
index 2de84169c692..900aa19c19ea 100644
--- a/arch/arm/boards/phytec-som-imx6/lowlevel.c
+++ b/arch/arm/boards/phytec-som-imx6/lowlevel.c
@@ -90,9 +90,9 @@ static void __noreturn start_imx6_phytec_common(uint32_t size,
__dtb_##fdt_name##_start); \
}
-PHYTEC_ENTRY(start_phytec_pbaa03_1gib, imx6q_phytec_pbaa03, SZ_1G, true);
-PHYTEC_ENTRY(start_phytec_pbaa03_1gib_1bank, imx6q_phytec_pbaa03, SZ_1G, true);
-PHYTEC_ENTRY(start_phytec_pbaa03_2gib, imx6q_phytec_pbaa03, SZ_2G, true);
+PHYTEC_ENTRY(start_phytec_phycard_imx6q_1gib, imx6q_phytec_phycard, SZ_1G,
true);
+PHYTEC_ENTRY(start_phytec_phycard_imx6q_1gib_1bank, imx6q_phytec_phycard,
SZ_1G, true);
+PHYTEC_ENTRY(start_phytec_phycard_imx6q_2gib, imx6q_phytec_phycard, SZ_2G,
true);
PHYTEC_ENTRY(start_phytec_pbab01_512mb_1bank, imx6q_phytec_pbab01, SZ_512M,
true);
PHYTEC_ENTRY(start_phytec_pbab01_1gib, imx6q_phytec_pbab01, SZ_1G, true);
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 5c9a311c5f8a..e8dca0b8513c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -52,7 +52,7 @@ lwl-dtb-$(CONFIG_MACH_PHYTEC_SOM_AM335X) +=
am335x-phytec-phyflex-som.dtb.o am33
am335x-phytec-phycore-som-nand-no-eeprom.dtb.o
am335x-phytec-phycore-som-nand-no-spi-no-eeprom.dtb.o \
am335x-phytec-phycore-som-emmc.dtb.o \
am335x-phytec-phycard-som.dtb.o am335x-phytec-phycard-som-mlo.dtb.o
-lwl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += imx6q-phytec-pbaa03.dtb.o \
+lwl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += imx6q-phytec-phycard.dtb.o \
imx6s-phytec-pbab01.dtb.o \
imx6dl-phytec-pbab01.dtb.o \
imx6q-phytec-pbab01.dtb.o \
diff --git a/arch/arm/dts/imx6q-phytec-pbaa03.dts
b/arch/arm/dts/imx6q-phytec-phycard.dts
similarity index 83%
rename from arch/arm/dts/imx6q-phytec-pbaa03.dts
rename to arch/arm/dts/imx6q-phytec-phycard.dts
index 8034f90804ec..09106f7d4dda 100644
--- a/arch/arm/dts/imx6q-phytec-pbaa03.dts
+++ b/arch/arm/dts/imx6q-phytec-phycard.dts
@@ -5,10 +5,14 @@
*/
/dts-v1/;
+
#ifdef CONFIG_BOOTM_FITIMAGE_PUBKEY
#include CONFIG_BOOTM_FITIMAGE_PUBKEY
#endif
-#include "imx6q-phytec-pcaaxl3.dtsi"
+
+#include
+#include "imx6q.dtsi"
+#include "imx6qdl-phytec-phycard-som.dtsi"
/ {
model = "PHYTEC phyCARD-i.MX6 Quad";
diff --git a/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi
b/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
similarity index 96%
rename from arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi
rename to arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
index 0dbd5419ba10..6d963f191024 100644
--- a/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi
+++ b/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
@@ -4,13 +4,7 @@
* Author: Christian Hemp
*/
-#include
-#include "imx6q.dtsi"
-
/ {
- model = "PHYTEC phyCARD-i.MX6 Quad";
- compatible = "phytec,imx6q-pcaaxl3", "fsl,imx6q";
-
chosen {
environment-nand {
compatible = "barebox,environment";
diff --git a/images/Makefile.imx b/images/Makefile.imx
index 53d4ac8202c5..5b60037c0787 100644
--- a/images/Makefile.imx
+++ b/images/Makefile.imx
@@ -281,11 +281,11 @@ $(call build_imx_habv4img, CONFIG_MACH_EMBEST_MARSBOARD,
start_imx6q_marsboard,
$(call build_imx_habv4img, CONFIG_MACH_EMBEST_RIOTBOARD,
start_imx6s_riotboard, embest-riotboard/flash-header-embest-riotboard,
embest-imx6s-riotboard)
-$(call build_imx_habv4img, CONFIG_MACH_PHYTEC_SOM_IMX6,
start_phytec_pbaa03_1gib, phytec-som-imx6/flash-header-phytec-pcaaxl3-1gib,
phytec-pbaa03-1gib)
+$(call build_imx_habv4img, CONFIG_MACH_PHYTEC_SOM_IMX6,
start_phytec_phycard_imx6q_1gib,
phytec-som-imx6/flash-header-phytec-pcaaxl3-1gib, phytec-phycard-imx6q-1gib)
-$(call build_imx_habv4img, CONFIG_MACH_PHYTEC_SOM_IMX6,
start_phytec_pbaa03_1gib_1bank,
phytec-som-imx6/flash-header-phytec-
[PATCH v2 8/8] ARM: dts: imx6: phytec: Increase NAND barebox partition size
For NAND flash with eraseblock size 1 MB and more the current
barebox partition size is not sufficient. The 4 FCB copies alone occupy
the 4 MB partition size. Increase the partition size to 16 MB to be fit
for the future and leaving some blocks for bad block handling as well.
Signed-off-by: Stefan Riedmueller
---
No changes in v2
---
arch/arm/dts/imx6qdl-phytec-pfla02.dtsi | 6 +++---
arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi | 6 +++---
arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi | 6 +++---
3 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
index 846ebbe6b18b..841ad653b26d 100644
--- a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
@@ -98,17 +98,17 @@
partition@0 {
label = "barebox";
- reg = <0x0 0x40>;
+ reg = <0x0 0x100>;
};
partition@40 {
label = "barebox-environment";
- reg = <0x40 0x10>;
+ reg = <0x100 0x10>;
};
partition@50 {
label = "root";
- reg = <0x50 0x0>;
+ reg = <0x110 0x0>;
};
};
};
diff --git a/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
b/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
index 13ffc8ee02ef..ff6c50128d68 100644
--- a/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
+++ b/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
@@ -42,17 +42,17 @@
partition@0 {
label = "barebox";
- reg = <0x0 0x40>;
+ reg = <0x0 0x100>;
};
partition@40 {
label = "barebox-environment";
- reg = <0x40 0x2>;
+ reg = <0x100 0x10>;
};
partition@42 {
label = "root";
- reg = <0x42 0x0>;
+ reg = <0x110 0x0>;
};
};
};
diff --git a/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
b/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
index 1d39368165db..2e03c08aa8e5 100644
--- a/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
+++ b/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
@@ -138,17 +138,17 @@
partition@0 {
label = "barebox";
- reg = <0x0 0x40>;
+ reg = <0x0 0x100>;
};
partition@40 {
label = "barebox-environment";
- reg = <0x40 0x10>;
+ reg = <0x100 0x10>;
};
partition@50 {
label = "root";
- reg = <0x50 0x0>;
+ reg = <0x110 0x0>;
};
};
};
--
2.7.4
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[PATCH v2 6/8] ARM: dts: imx6: phycard: Switch to new partitions binding
The SD card interface is still using the legacy partition binding.
Change this by switching to the new bindings.
Signed-off-by: Stefan Riedmueller
---
No changes in v2
---
arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi | 21 -
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
b/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
index 51cece26837a..de07562c6884 100644
--- a/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
+++ b/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
@@ -158,16 +158,19 @@
cd-gpios = <&gpio5 22 0>;
status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
- partition@0 {
- label = "barebox";
- reg = <0x0 0xe>;
- };
+ partition@0 {
+ label = "barebox";
+ reg = <0x0 0xe>;
+ };
- partition@e {
- label = "barebox-environment";
- reg = <0xe 0x2>;
+ partition@e {
+ label = "barebox-environment";
+ reg = <0xe 0x2>;
+ };
};
};
--
2.7.4
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[PATCH v2 3/8] ARM: dts: imx6: pcaaxl3: Make use of the simpler name phycard
Use the simpler name phycard instead of the article number pcaaxl3
for device tree file names and image names of the phyCARD-i.MX 6.
Also make the dtsi file includeable for i.MX 6Solo/DualLight as well.
Signed-off-by: Stefan Riedmueller
---
Changes in v2:
- Remove the model and compatible from dtsi file and move i.MX 6 specific
includes to the dts file.
- Extend commit message.
---
arch/arm/boards/phytec-som-imx6/lowlevel.c | 6 ++---
arch/arm/dts/Makefile | 2 +-
...-phytec-pbaa03.dts => imx6q-phytec-phycard.dts} | 4 +++-
...caaxl3.dtsi => imx6qdl-phytec-phycard-som.dtsi} | 6 -
images/Makefile.imx| 28 +++---
5 files changed, 21 insertions(+), 25 deletions(-)
rename arch/arm/dts/{imx6q-phytec-pbaa03.dts => imx6q-phytec-phycard.dts} (81%)
rename arch/arm/dts/{imx6q-phytec-pcaaxl3.dtsi =>
imx6qdl-phytec-phycard-som.dtsi} (96%)
diff --git a/arch/arm/boards/phytec-som-imx6/lowlevel.c
b/arch/arm/boards/phytec-som-imx6/lowlevel.c
index 2de84169c692..900aa19c19ea 100644
--- a/arch/arm/boards/phytec-som-imx6/lowlevel.c
+++ b/arch/arm/boards/phytec-som-imx6/lowlevel.c
@@ -90,9 +90,9 @@ static void __noreturn start_imx6_phytec_common(uint32_t size,
__dtb_##fdt_name##_start); \
}
-PHYTEC_ENTRY(start_phytec_pbaa03_1gib, imx6q_phytec_pbaa03, SZ_1G, true);
-PHYTEC_ENTRY(start_phytec_pbaa03_1gib_1bank, imx6q_phytec_pbaa03, SZ_1G, true);
-PHYTEC_ENTRY(start_phytec_pbaa03_2gib, imx6q_phytec_pbaa03, SZ_2G, true);
+PHYTEC_ENTRY(start_phytec_phycard_imx6q_1gib, imx6q_phytec_phycard, SZ_1G,
true);
+PHYTEC_ENTRY(start_phytec_phycard_imx6q_1gib_1bank, imx6q_phytec_phycard,
SZ_1G, true);
+PHYTEC_ENTRY(start_phytec_phycard_imx6q_2gib, imx6q_phytec_phycard, SZ_2G,
true);
PHYTEC_ENTRY(start_phytec_pbab01_512mb_1bank, imx6q_phytec_pbab01, SZ_512M,
true);
PHYTEC_ENTRY(start_phytec_pbab01_1gib, imx6q_phytec_pbab01, SZ_1G, true);
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 294a0bfa5525..5f854bd22f2f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -51,7 +51,7 @@ lwl-dtb-$(CONFIG_MACH_PHYTEC_SOM_AM335X) +=
am335x-phytec-phyflex-som.dtb.o am33
am335x-phytec-phycore-som-nand-no-eeprom.dtb.o
am335x-phytec-phycore-som-nand-no-spi-no-eeprom.dtb.o \
am335x-phytec-phycore-som-emmc.dtb.o \
am335x-phytec-phycard-som.dtb.o am335x-phytec-phycard-som-mlo.dtb.o
-lwl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += imx6q-phytec-pbaa03.dtb.o \
+lwl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += imx6q-phytec-phycard.dtb.o \
imx6s-phytec-pbab01.dtb.o \
imx6dl-phytec-pbab01.dtb.o \
imx6q-phytec-pbab01.dtb.o \
diff --git a/arch/arm/dts/imx6q-phytec-pbaa03.dts
b/arch/arm/dts/imx6q-phytec-phycard.dts
similarity index 81%
rename from arch/arm/dts/imx6q-phytec-pbaa03.dts
rename to arch/arm/dts/imx6q-phytec-phycard.dts
index b11b8b3f93fe..a56130a31ca6 100644
--- a/arch/arm/dts/imx6q-phytec-pbaa03.dts
+++ b/arch/arm/dts/imx6q-phytec-phycard.dts
@@ -5,7 +5,9 @@
*/
/dts-v1/;
-#include "imx6q-phytec-pcaaxl3.dtsi"
+#include
+#include "imx6q.dtsi"
+#include "imx6qdl-phytec-phycard-som.dtsi"
/ {
model = "PHYTEC phyCARD-i.MX6 Quad";
diff --git a/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi
b/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
similarity index 96%
rename from arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi
rename to arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
index 0dbd5419ba10..6d963f191024 100644
--- a/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi
+++ b/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
@@ -4,13 +4,7 @@
* Author: Christian Hemp
*/
-#include
-#include "imx6q.dtsi"
-
/ {
- model = "PHYTEC phyCARD-i.MX6 Quad";
- compatible = "phytec,imx6q-pcaaxl3", "fsl,imx6q";
-
chosen {
environment-nand {
compatible = "barebox,environment";
diff --git a/images/Makefile.imx b/images/Makefile.imx
index a8f8a9b7d622..fea43e0e5516 100644
--- a/images/Makefile.imx
+++ b/images/Makefile.imx
@@ -416,20 +416,20 @@ CFG_start_imx6s_riotboard.pblb.imximg =
$(board)/embest-riotboard/flash-header-e
FILE_barebox-embest-imx6s-riotboard.img = start_imx6s_riotboard.pblb.imximg
image-$(CONFIG_MACH_EMBEST_RIOTBOARD) += barebox-embest-imx6s-riotboard.img
-pblb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += start_phytec_pbaa03_1gib
-CFG_start_phytec_pbaa03_1gib.pblb.imximg =
$(board)/phytec-som-imx6/flash-header-phytec-pcaaxl3-1gib.imxcfg
-FILE_barebox-phytec-pbaa03-1gib.img = start_phytec_pbaa03_1gib.pblb.imximg
-image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-pbaa03-1gib.img
-
-pblb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += start_phytec_pbaa03_1gib_1bank
-CFG_start_phytec_pbaa03_1gib_1bank.pblb.imximg =
$(board)/ph
[PATCH v2 4/8] ARM: dts: imx6: phycard: Make eeprom configurable
The EEPROM is a configurable option. So make it configurable from the
dts file.
Signed-off-by: Stefan Riedmueller
---
No changes in v2
---
arch/arm/dts/imx6q-phytec-phycard.dts| 4
arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi | 1 +
2 files changed, 5 insertions(+)
diff --git a/arch/arm/dts/imx6q-phytec-phycard.dts
b/arch/arm/dts/imx6q-phytec-phycard.dts
index a56130a31ca6..7f6e0b76ec56 100644
--- a/arch/arm/dts/imx6q-phytec-phycard.dts
+++ b/arch/arm/dts/imx6q-phytec-phycard.dts
@@ -18,6 +18,10 @@
};
};
+&eeprom {
+ status = "okay";
+};
+
&fec {
status = "okay";
};
diff --git a/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
b/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
index 6d963f191024..f1a5e5962362 100644
--- a/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
+++ b/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
@@ -63,6 +63,7 @@
eeprom: m24c32@50 {
compatible = "st,24c32", "at24";
reg = <0x50>;
+ status = "disabled";
};
};
--
2.7.4
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[PATCH v2 7/8] ARM: dts: imx6: phycard: Use gpio binding constants
Signed-off-by: Stefan Riedmueller
---
Changes in v2:
- Added this patch
---
arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
b/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
index de07562c6884..13ffc8ee02ef 100644
--- a/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
+++ b/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
@@ -4,6 +4,8 @@
* Author: Christian Hemp
*/
+#include
+
/ {
chosen {
environment-nand {
@@ -155,7 +157,7 @@
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
-cd-gpios = <&gpio5 22 0>;
+cd-gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>;
status = "disabled";
partitions {
--
2.7.4
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[PATCH v2 1/8] ARM: dts: imx6: pcaaxl3: Order nodes alphabetically
Bring the device tree nodes in alphabetical order and in this context
also remove the deprecated iomux group.
Signed-off-by: Stefan Riedmueller
---
No changes in v2
---
arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi | 182 -
1 file changed, 90 insertions(+), 92 deletions(-)
diff --git a/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi
b/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi
index 66b547ad8eef..db986f87ef26 100644
--- a/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi
+++ b/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi
@@ -17,104 +17,16 @@
compatible = "phytec,imx6q-pcaaxl3", "fsl,imx6q";
chosen {
- environment-sd3 {
- compatible = "barebox,environment";
- device-path = &environment_usdhc3;
- status = "disabled";
- };
-
environment-nand {
compatible = "barebox,environment";
device-path = &environment_nand;
status = "disabled";
};
- };
-};
-
-&i2c1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
-
- eeprom: m24c32@50 {
- compatible = "st,24c32", "at24";
- reg = <0x50>;
- };
-};
-
-&iomuxc {
- pinctrl-names = "default";
-
- imx6q-phytec-pcaaxl3 {
- pinctrl_enet: enetgrp {
- fsl,pins = <
- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
- MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
- MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
- MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
- MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
- MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
- MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
- MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK0x1b0b0
- MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3 0x1b0b0
- MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3 0x1b0b0
- MX6QDL_PAD_KEY_ROW1__ENET_COL 0x1b0b0
- MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2 0x1b0b0
- MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2 0x1b0b0
- MX6QDL_PAD_KEY_COL3__ENET_CRS 0x1b0b0
- MX6QDL_PAD_GPIO_18__ENET_RX_CLK 0x1b0b0
- MX6QDL_PAD_GPIO_19__ENET_TX_ER 0x1b0b0
- >;
- };
-
- pinctrl_gpmi_nand: gpmigrp {
- fsl,pins = <
- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B0xb0b1
- MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B0xb0b1
- MX6QDL_PAD_NANDF_CS1__NAND_CE1_B0xb0b1
- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
- MX6QDL_PAD_NANDF_D0__NAND_DATA000xb0b1
- MX6QDL_PAD_NANDF_D1__NAND_DATA010xb0b1
- MX6QDL_PAD_NANDF_D2__NAND_DATA020xb0b1
- MX6QDL_PAD_NANDF_D3__NAND_DATA030xb0b1
- MX6QDL_PAD_NANDF_D4__NAND_DATA040xb0b1
- MX6QDL_PAD_NANDF_D5__NAND_DATA050xb0b1
- MX6QDL_PAD_NANDF_D6__NAND_DATA060xb0b1
- MX6QDL_PAD_NANDF_D7__NAND_DATA070xb0b1
- MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
- >;
- };
-
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX6QDL_PAD_EIM_D21__I2C1_SCL
0x4001b8b1
- MX6QDL_PAD_EIM_D28__I2C1_SDA
0x4001b8b1
- >;
- };
-
- pinctrl_uart3: uart3grp {
- fsl,pins = &
[PATCH v2 5/8] ARM: dts: imx6: phycard: Use partname for environment device-path
Change environment device-path from using a separate label to
referencing a device plus partname.
Signed-off-by: Stefan Riedmueller
---
No changes in v2
---
arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
b/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
index f1a5e5962362..51cece26837a 100644
--- a/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
+++ b/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
@@ -8,13 +8,13 @@
chosen {
environment-nand {
compatible = "barebox,environment";
- device-path = &environment_nand;
+ device-path = &gpmi, "partname:barebox-environment";
status = "disabled";
};
environment-sd3 {
compatible = "barebox,environment";
- device-path = &environment_usdhc3;
+ device-path = &usdhc3, "partname:barebox-environment";
status = "disabled";
};
};
@@ -43,7 +43,7 @@
reg = <0x0 0x40>;
};
- environment_nand: partition@40 {
+ partition@40 {
label = "barebox-environment";
reg = <0x40 0x2>;
};
@@ -165,7 +165,8 @@
label = "barebox";
reg = <0x0 0xe>;
};
- environment_usdhc3: partition@e {
+
+ partition@e {
label = "barebox-environment";
reg = <0xe 0x2>;
};
--
2.7.4
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[PATCH v2 2/8] ARM: dts: imx6: pcaaxl3: Update license and model description
Make use of SPDX license identifiers and update copyright notices and
model descriptions of the phyCARD-i.MX 6 SOM.
Signed-off-by: Stefan Riedmueller
---
Changes in v2:
- Don't remove dtsi's model and compatible yet
---
arch/arm/dts/imx6q-phytec-pbaa03.dts | 13 -
arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi | 13 -
2 files changed, 8 insertions(+), 18 deletions(-)
diff --git a/arch/arm/dts/imx6q-phytec-pbaa03.dts
b/arch/arm/dts/imx6q-phytec-pbaa03.dts
index 4724a02ad7d8..b11b8b3f93fe 100644
--- a/arch/arm/dts/imx6q-phytec-pbaa03.dts
+++ b/arch/arm/dts/imx6q-phytec-pbaa03.dts
@@ -1,19 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later)
/*
- * Copyright 2014 Christian Hemp, Phytec Messtechnik GmbH
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ * Copyright (C) 2014 PHYTEC Messtechnik GmbH
+ * Author: Christian Hemp
*/
/dts-v1/;
#include "imx6q-phytec-pcaaxl3.dtsi"
/ {
- model = "Phytec phyCARD-i.MX6 Quad Carrier-Board";
+ model = "PHYTEC phyCARD-i.MX6 Quad";
compatible = "phytec,imx6q-pbaa03", "phytec,imx6q-pcaaxl3", "fsl,imx6q";
chosen {
diff --git a/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi
b/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi
index db986f87ef26..0dbd5419ba10 100644
--- a/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi
+++ b/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi
@@ -1,19 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later)
/*
- * Copyright 201 Christian Hemp, Phytec Messtechnik GmbH
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ * Copyright (C) 2014 PHYTEC Messtechnik GmbH
+ * Author: Christian Hemp
*/
#include
#include "imx6q.dtsi"
/ {
- model = "Phytec phyCARD-i.MX6 Quad";
+ model = "PHYTEC phyCARD-i.MX6 Quad";
compatible = "phytec,imx6q-pcaaxl3", "fsl,imx6q";
chosen {
--
2.7.4
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[PATCH 7/7] ARM: dts: imx6: phytec: Increase NAND barebox partition size
For NAND flash with eraseblock size 1 MB and more the current
barebox partition size is not sufficient. The 4 FCB copies alone occupy
the 4 MB partition size. Increase the partition size to 16 MB to be fit
for the future and leaving some blocks for bad block handling as well.
Signed-off-by: Stefan Riedmueller
---
arch/arm/dts/imx6qdl-phytec-pfla02.dtsi | 6 +++---
arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi | 6 +++---
arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi | 6 +++---
3 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
index 846ebbe6b18b..841ad653b26d 100644
--- a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
@@ -98,17 +98,17 @@
partition@0 {
label = "barebox";
- reg = <0x0 0x40>;
+ reg = <0x0 0x100>;
};
partition@40 {
label = "barebox-environment";
- reg = <0x40 0x10>;
+ reg = <0x100 0x10>;
};
partition@50 {
label = "root";
- reg = <0x50 0x0>;
+ reg = <0x110 0x0>;
};
};
};
diff --git a/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
b/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
index d607bfd0d95f..251134424470 100644
--- a/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
+++ b/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
@@ -43,17 +43,17 @@
partition@0 {
label = "barebox";
- reg = <0x0 0x40>;
+ reg = <0x0 0x100>;
};
partition@40 {
label = "barebox-environment";
- reg = <0x40 0x2>;
+ reg = <0x100 0x10>;
};
partition@42 {
label = "root";
- reg = <0x42 0x0>;
+ reg = <0x110 0x0>;
};
};
};
diff --git a/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
b/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
index 1d39368165db..2e03c08aa8e5 100644
--- a/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
+++ b/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
@@ -138,17 +138,17 @@
partition@0 {
label = "barebox";
- reg = <0x0 0x40>;
+ reg = <0x0 0x100>;
};
partition@40 {
label = "barebox-environment";
- reg = <0x40 0x10>;
+ reg = <0x100 0x10>;
};
partition@50 {
label = "root";
- reg = <0x50 0x0>;
+ reg = <0x110 0x0>;
};
};
};
--
2.7.4
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[PATCH 5/7] ARM: dts: imx6: phycard: Use partname for environment device-path
Change environment device-path from using a separate label to
referencing a device plus partname.
Signed-off-by: Stefan Riedmueller
---
arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
b/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
index 78fc0c719637..c28076294092 100644
--- a/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
+++ b/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
@@ -11,13 +11,13 @@
chosen {
environment-nand {
compatible = "barebox,environment";
- device-path = &environment_nand;
+ device-path = &gpmi, "partname:barebox-environment";
status = "disabled";
};
environment-sd3 {
compatible = "barebox,environment";
- device-path = &environment_usdhc3;
+ device-path = &usdhc3, "partname:barebox-environment";
status = "disabled";
};
};
@@ -46,7 +46,7 @@
reg = <0x0 0x40>;
};
- environment_nand: partition@40 {
+ partition@40 {
label = "barebox-environment";
reg = <0x40 0x2>;
};
@@ -168,7 +168,8 @@
label = "barebox";
reg = <0x0 0xe>;
};
- environment_usdhc3: partition@e {
+
+ partition@e {
label = "barebox-environment";
reg = <0xe 0x2>;
};
--
2.7.4
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[PATCH 6/7] ARM: dts: imx6: phycard: Switch to new partitions binding
The SD card interface is still using the legacy partition binding.
Change this by switching to the new bindings.
Signed-off-by: Stefan Riedmueller
---
arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi | 21 -
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
b/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
index c28076294092..d607bfd0d95f 100644
--- a/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
+++ b/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
@@ -161,16 +161,19 @@
cd-gpios = <&gpio5 22 0>;
status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
- partition@0 {
- label = "barebox";
- reg = <0x0 0xe>;
- };
+ partition@0 {
+ label = "barebox";
+ reg = <0x0 0xe>;
+ };
- partition@e {
- label = "barebox-environment";
- reg = <0xe 0x2>;
+ partition@e {
+ label = "barebox-environment";
+ reg = <0xe 0x2>;
+ };
};
};
--
2.7.4
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[PATCH 4/7] ARM: dts: imx6: phycard: Make eeprom configurable
The EEPROM is a configurable option. So make it configurable from the
dts file.
Signed-off-by: Stefan Riedmueller
---
arch/arm/dts/imx6q-phytec-phycard.dts| 4
arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi | 1 +
2 files changed, 5 insertions(+)
diff --git a/arch/arm/dts/imx6q-phytec-phycard.dts
b/arch/arm/dts/imx6q-phytec-phycard.dts
index cfcdcd2a1343..f06acb010095 100644
--- a/arch/arm/dts/imx6q-phytec-phycard.dts
+++ b/arch/arm/dts/imx6q-phytec-phycard.dts
@@ -16,6 +16,10 @@
};
};
+&eeprom {
+ status = "okay";
+};
+
&fec {
status = "okay";
};
diff --git a/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
b/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
index 5e0495996d52..78fc0c719637 100644
--- a/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
+++ b/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
@@ -66,6 +66,7 @@
eeprom: m24c32@50 {
compatible = "st,24c32", "at24";
reg = <0x50>;
+ status = "disabled";
};
};
--
2.7.4
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[PATCH 3/7] ARM: dts: imx6: pcaaxl3: Make use of the simpler name phycard
Use the simpler name phycard instead of the article number pcaaxl3
for device tree file names and image names of the phyCARD-i.MX 6.
Signed-off-by: Stefan Riedmueller
---
arch/arm/boards/phytec-som-imx6/lowlevel.c | 6 ++---
arch/arm/dts/Makefile | 2 +-
...-phytec-pbaa03.dts => imx6q-phytec-phycard.dts} | 2 +-
...caaxl3.dtsi => imx6qdl-phytec-phycard-som.dtsi} | 0
images/Makefile.imx| 28 +++---
5 files changed, 19 insertions(+), 19 deletions(-)
rename arch/arm/dts/{imx6q-phytec-pbaa03.dts => imx6q-phytec-phycard.dts} (90%)
rename arch/arm/dts/{imx6q-phytec-pcaaxl3.dtsi =>
imx6qdl-phytec-phycard-som.dtsi} (100%)
diff --git a/arch/arm/boards/phytec-som-imx6/lowlevel.c
b/arch/arm/boards/phytec-som-imx6/lowlevel.c
index 2de84169c692..900aa19c19ea 100644
--- a/arch/arm/boards/phytec-som-imx6/lowlevel.c
+++ b/arch/arm/boards/phytec-som-imx6/lowlevel.c
@@ -90,9 +90,9 @@ static void __noreturn start_imx6_phytec_common(uint32_t size,
__dtb_##fdt_name##_start); \
}
-PHYTEC_ENTRY(start_phytec_pbaa03_1gib, imx6q_phytec_pbaa03, SZ_1G, true);
-PHYTEC_ENTRY(start_phytec_pbaa03_1gib_1bank, imx6q_phytec_pbaa03, SZ_1G, true);
-PHYTEC_ENTRY(start_phytec_pbaa03_2gib, imx6q_phytec_pbaa03, SZ_2G, true);
+PHYTEC_ENTRY(start_phytec_phycard_imx6q_1gib, imx6q_phytec_phycard, SZ_1G,
true);
+PHYTEC_ENTRY(start_phytec_phycard_imx6q_1gib_1bank, imx6q_phytec_phycard,
SZ_1G, true);
+PHYTEC_ENTRY(start_phytec_phycard_imx6q_2gib, imx6q_phytec_phycard, SZ_2G,
true);
PHYTEC_ENTRY(start_phytec_pbab01_512mb_1bank, imx6q_phytec_pbab01, SZ_512M,
true);
PHYTEC_ENTRY(start_phytec_pbab01_1gib, imx6q_phytec_pbab01, SZ_1G, true);
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 294a0bfa5525..5f854bd22f2f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -51,7 +51,7 @@ lwl-dtb-$(CONFIG_MACH_PHYTEC_SOM_AM335X) +=
am335x-phytec-phyflex-som.dtb.o am33
am335x-phytec-phycore-som-nand-no-eeprom.dtb.o
am335x-phytec-phycore-som-nand-no-spi-no-eeprom.dtb.o \
am335x-phytec-phycore-som-emmc.dtb.o \
am335x-phytec-phycard-som.dtb.o am335x-phytec-phycard-som-mlo.dtb.o
-lwl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += imx6q-phytec-pbaa03.dtb.o \
+lwl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += imx6q-phytec-phycard.dtb.o \
imx6s-phytec-pbab01.dtb.o \
imx6dl-phytec-pbab01.dtb.o \
imx6q-phytec-pbab01.dtb.o \
diff --git a/arch/arm/dts/imx6q-phytec-pbaa03.dts
b/arch/arm/dts/imx6q-phytec-phycard.dts
similarity index 90%
rename from arch/arm/dts/imx6q-phytec-pbaa03.dts
rename to arch/arm/dts/imx6q-phytec-phycard.dts
index b11b8b3f93fe..cfcdcd2a1343 100644
--- a/arch/arm/dts/imx6q-phytec-pbaa03.dts
+++ b/arch/arm/dts/imx6q-phytec-phycard.dts
@@ -5,7 +5,7 @@
*/
/dts-v1/;
-#include "imx6q-phytec-pcaaxl3.dtsi"
+#include "imx6qdl-phytec-phycard-som.dtsi"
/ {
model = "PHYTEC phyCARD-i.MX6 Quad";
diff --git a/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi
b/arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
similarity index 100%
rename from arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi
rename to arch/arm/dts/imx6qdl-phytec-phycard-som.dtsi
diff --git a/images/Makefile.imx b/images/Makefile.imx
index a8f8a9b7d622..fea43e0e5516 100644
--- a/images/Makefile.imx
+++ b/images/Makefile.imx
@@ -416,20 +416,20 @@ CFG_start_imx6s_riotboard.pblb.imximg =
$(board)/embest-riotboard/flash-header-e
FILE_barebox-embest-imx6s-riotboard.img = start_imx6s_riotboard.pblb.imximg
image-$(CONFIG_MACH_EMBEST_RIOTBOARD) += barebox-embest-imx6s-riotboard.img
-pblb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += start_phytec_pbaa03_1gib
-CFG_start_phytec_pbaa03_1gib.pblb.imximg =
$(board)/phytec-som-imx6/flash-header-phytec-pcaaxl3-1gib.imxcfg
-FILE_barebox-phytec-pbaa03-1gib.img = start_phytec_pbaa03_1gib.pblb.imximg
-image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-pbaa03-1gib.img
-
-pblb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += start_phytec_pbaa03_1gib_1bank
-CFG_start_phytec_pbaa03_1gib_1bank.pblb.imximg =
$(board)/phytec-som-imx6/flash-header-phytec-pcaaxl3-1gib-1bank.imxcfg
-FILE_barebox-phytec-pbaa03-1gib-1bank.img =
start_phytec_pbaa03_1gib_1bank.pblb.imximg
-image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-pbaa03-1gib-1bank.img
-
-pblb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += start_phytec_pbaa03_2gib
-CFG_start_phytec_pbaa03_2gib.pblb.imximg =
$(board)/phytec-som-imx6/flash-header-phytec-pcaaxl3-2gib.imxcfg
-FILE_barebox-phytec-pbaa03-2gib.img = start_phytec_pbaa03_2gib.pblb.imximg
-image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-pbaa03-2gib.img
+pblb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += start_phytec_phycard_imx6q_1gib
+CFG_start_phytec_phycard_imx6q_1gib.pblb.imximg =
$(board)/phytec-som-imx6/flash-header-phytec-pcaaxl3-1gib.imxcfg
+
[PATCH 2/7] ARM: dts: imx6: pcaaxl3: Update license and model description
Make use of SPDX license identifiers and update copyright notices and
model descriptions of the phyCARD-i.MX 6 SOM.
Signed-off-by: Stefan Riedmueller
---
arch/arm/dts/imx6q-phytec-pbaa03.dts | 13 -
arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi | 14 +++---
2 files changed, 7 insertions(+), 20 deletions(-)
diff --git a/arch/arm/dts/imx6q-phytec-pbaa03.dts
b/arch/arm/dts/imx6q-phytec-pbaa03.dts
index 4724a02ad7d8..b11b8b3f93fe 100644
--- a/arch/arm/dts/imx6q-phytec-pbaa03.dts
+++ b/arch/arm/dts/imx6q-phytec-pbaa03.dts
@@ -1,19 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later)
/*
- * Copyright 2014 Christian Hemp, Phytec Messtechnik GmbH
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ * Copyright (C) 2014 PHYTEC Messtechnik GmbH
+ * Author: Christian Hemp
*/
/dts-v1/;
#include "imx6q-phytec-pcaaxl3.dtsi"
/ {
- model = "Phytec phyCARD-i.MX6 Quad Carrier-Board";
+ model = "PHYTEC phyCARD-i.MX6 Quad";
compatible = "phytec,imx6q-pbaa03", "phytec,imx6q-pcaaxl3", "fsl,imx6q";
chosen {
diff --git a/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi
b/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi
index db986f87ef26..5e0495996d52 100644
--- a/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi
+++ b/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi
@@ -1,21 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later)
/*
- * Copyright 201 Christian Hemp, Phytec Messtechnik GmbH
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ * Copyright (C) 2014 PHYTEC Messtechnik GmbH
+ * Author: Christian Hemp
*/
#include
#include "imx6q.dtsi"
/ {
- model = "Phytec phyCARD-i.MX6 Quad";
- compatible = "phytec,imx6q-pcaaxl3", "fsl,imx6q";
-
chosen {
environment-nand {
compatible = "barebox,environment";
--
2.7.4
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[PATCH 1/7] ARM: dts: imx6: pcaaxl3: Order nodes alphabetically
Bring the device tree nodes in alphabetical order and in this context
also remove the deprecated iomux group.
Signed-off-by: Stefan Riedmueller
---
arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi | 182 -
1 file changed, 90 insertions(+), 92 deletions(-)
diff --git a/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi
b/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi
index 66b547ad8eef..db986f87ef26 100644
--- a/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi
+++ b/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi
@@ -17,104 +17,16 @@
compatible = "phytec,imx6q-pcaaxl3", "fsl,imx6q";
chosen {
- environment-sd3 {
- compatible = "barebox,environment";
- device-path = &environment_usdhc3;
- status = "disabled";
- };
-
environment-nand {
compatible = "barebox,environment";
device-path = &environment_nand;
status = "disabled";
};
- };
-};
-
-&i2c1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
-
- eeprom: m24c32@50 {
- compatible = "st,24c32", "at24";
- reg = <0x50>;
- };
-};
-
-&iomuxc {
- pinctrl-names = "default";
-
- imx6q-phytec-pcaaxl3 {
- pinctrl_enet: enetgrp {
- fsl,pins = <
- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
- MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
- MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
- MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
- MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
- MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
- MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
- MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK0x1b0b0
- MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3 0x1b0b0
- MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3 0x1b0b0
- MX6QDL_PAD_KEY_ROW1__ENET_COL 0x1b0b0
- MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2 0x1b0b0
- MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2 0x1b0b0
- MX6QDL_PAD_KEY_COL3__ENET_CRS 0x1b0b0
- MX6QDL_PAD_GPIO_18__ENET_RX_CLK 0x1b0b0
- MX6QDL_PAD_GPIO_19__ENET_TX_ER 0x1b0b0
- >;
- };
-
- pinctrl_gpmi_nand: gpmigrp {
- fsl,pins = <
- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B0xb0b1
- MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B0xb0b1
- MX6QDL_PAD_NANDF_CS1__NAND_CE1_B0xb0b1
- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
- MX6QDL_PAD_NANDF_D0__NAND_DATA000xb0b1
- MX6QDL_PAD_NANDF_D1__NAND_DATA010xb0b1
- MX6QDL_PAD_NANDF_D2__NAND_DATA020xb0b1
- MX6QDL_PAD_NANDF_D3__NAND_DATA030xb0b1
- MX6QDL_PAD_NANDF_D4__NAND_DATA040xb0b1
- MX6QDL_PAD_NANDF_D5__NAND_DATA050xb0b1
- MX6QDL_PAD_NANDF_D6__NAND_DATA060xb0b1
- MX6QDL_PAD_NANDF_D7__NAND_DATA070xb0b1
- MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
- >;
- };
-
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX6QDL_PAD_EIM_D21__I2C1_SCL
0x4001b8b1
- MX6QDL_PAD_EIM_D28__I2C1_SDA
0x4001b8b1
- >;
- };
-
- pinctrl_uart3: uart3grp {
- fsl,pins = &
[PATCH] ARM: boards: phytec-som-imx6: Replace spi by spi-nor in bootsource script
Commit 7802c6f891b7 ("ARM: i.MX6: boot: Return BOOTSOURCE_SPI_NOR, not
BOOTSOURCE_SPI") changed the returned boot source for SPI NOR on i.MX 6
from SPI to SPI_NOR. This needs to be accounted for in the bootsource
scripts.
Signed-off-by: Stefan Riedmueller
---
.../phytec-som-imx6/defaultenv-physom-imx6-phycore/init/bootsource | 2 +-
arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/init/bootsource | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git
a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6-phycore/init/bootsource
b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6-phycore/init/bootsource
index 515613b04161..fa5f7f26c5a7 100644
---
a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6-phycore/init/bootsource
+++
b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6-phycore/init/bootsource
@@ -12,7 +12,7 @@ if [ $bootsource = mmc ]; then
fi
elif [ $bootsource = nand ]; then
global.boot.default="nand spi emmc mmc net"
-elif [ $bootsource = spi ]; then
+elif [ $bootsource = spi-nor ]; then
global.boot.default="spi nand emmc mmc net"
elif [ $bootsource = net ]; then
global.boot.default="net nand spi emmc mmc"
diff --git
a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/init/bootsource
b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/init/bootsource
index 3f2ff4bcc836..9c9f0ec3810f 100644
--- a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/init/bootsource
+++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/init/bootsource
@@ -8,7 +8,7 @@ if [ $bootsource = mmc ]; then
global.boot.default="mmc nand spi net"
elif [ $bootsource = nand ]; then
global.boot.default="nand spi mmc net"
-elif [ $bootsource = spi ]; then
+elif [ $bootsource = spi-nor ]; then
global.boot.default="spi nand mmc net"
elif [ $bootsource = net ]; then
global.boot.default="net nand spi mmc"
--
2.7.4
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[PATCH] ARM: dts: imx6qdl: phycore: Remove emmc vmmc-supply
There is no driver for the eMMC's vmmc-supply regulator in the barebox.
Use a dummy regulator instead by simply deleting the vmmc-supply
property.
Signed-off-by: Stefan Riedmueller
---
arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
b/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
index 69f252b42382..974e271f453d 100644
--- a/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
+++ b/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
@@ -112,6 +112,7 @@
};
&usdhc4 {
+ /delete-property/ vmmc-supply;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
--
2.7.4
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[PATCH 2/2] ARM: dts: imx6: phycore: Update License, copyright and model description
Make use of SPDX license identifiers and update copyright notices and model
descriptions of the phyCORE-i.MX 6 SOM's.
Signed-off-by: Stefan Riedmueller
---
arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts | 10 ++
arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts | 13 -
arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts | 13 -
arch/arm/dts/imx6q-phytec-phycore-som-nand.dts | 13 -
arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi| 11 +++
arch/arm/dts/imx6qp-phytec-phycore-som-nand.dts | 12 +++-
6 files changed, 20 insertions(+), 52 deletions(-)
diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts
b/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts
index 8ce0066c691d..b2e86eae175a 100644
--- a/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts
+++ b/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts
@@ -1,13 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later)
/*
* Copyright (C) 2015 PHYTEC Messtechnik GmbH,
* Author: Stefan Christ
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
@@ -19,7 +13,7 @@
#include "imx6qdl-phytec-state.dtsi"
/ {
- model = "Phytec phyCORE-i.MX6 DualLite/SOLO with eMMC";
+ model = "PHYTEC phyCORE-i.MX6 DualLite/SOLO with eMMC";
compatible = "phytec,imx6dl-pcm058-emmc", "fsl,imx6dl";
};
diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts
b/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts
index 18d14d6b945c..d747c837a535 100644
--- a/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts
+++ b/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts
@@ -1,12 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later)
/*
- * Copyright 2015 Christian Hemp, Phytec Messtechnik GmbH
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ * Copyright (C) 2015 PHYTEC Messtechnik GmbH
+ * Author: Christian Hemp
*/
/dts-v1/;
@@ -18,7 +13,7 @@
#include "imx6qdl-phytec-state.dtsi"
/ {
- model = "Phytec phyCORE-i.MX6 Duallite/SOLO with NAND";
+ model = "PHYTEC phyCORE-i.MX6 Duallite/SOLO with NAND";
compatible = "phytec,imx6dl-pcm058-nand", "fsl,imx6dl";
};
diff --git a/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts
b/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts
index 2ff4ae7a488a..0acc6493cc51 100644
--- a/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts
+++ b/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts
@@ -1,12 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later)
/*
- * Copyright 2015 Christian Hemp, Phytec Messtechnik GmbH
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ * Copyright (C) 2015 PHYTEC Messtechnik GmbH
+ * Author: Christian Hemp
*/
/dts-v1/;
@@ -18,7 +13,7 @@
#include "imx6qdl-phytec-state.dtsi"
/ {
- model = "Phytec phyCORE-i.MX6 Quad with eMMC";
+ model = "PHYTEC phyCORE-i.MX6 Quad with eMMC";
compatible = "phytec,imx6q-pcm058-emmc", "fsl,imx6q";
};
diff --git a/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts
b/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts
index cc5ef7d11d30..12f2b21f3b11 100644
--- a/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts
+++ b/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts
@@ -1,12 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later)
/*
- * Copyright 2015 Christian Hemp, Phytec Messtechnik GmbH
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ * Copyright (C) 2015 PHYTEC Messtechnik GmbH
+ * Author: Christian Hemp
*/
/dts-v1/;
@@ -18,7 +13,7 @@
#include "imx6qdl-phytec-state.dtsi"
/ {
- model = "Phytec phyCORE-i.MX6 Quad with NAND";
+ model = "PHYTEC phyCORE-i.MX6 Quad with NAND";
compatible = "phytec,imx6q-pcm058-nand", "fsl,imx6q";
};
diff --git a/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
b/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
index 3bb21ce8f761..69f2
[PATCH 1/2] ARM: dts: imx6: phycore: Make use of upstream devicetree
Make use of the upstream devicetree for the phyCORE-i.MX 6 and the
phyBOARD-Mira to reduce code duplication. In this context also add a
Mira devicetree for barebox to better differentiate between phyCORE
related settings and baseboard related settings.
Signed-off-by: Stefan Riedmueller
---
arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts| 23 +-
arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts | 20 +-
arch/arm/dts/imx6dl-phytec-phycore-som-lc-nand.dts | 14 +-
arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts| 17 +-
arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts | 23 +-
arch/arm/dts/imx6q-phytec-phycore-som-nand.dts | 23 +-
arch/arm/dts/imx6qdl-phytec-mira.dtsi | 44
arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi | 286 +++--
arch/arm/dts/imx6qp-phytec-phycore-som-nand.dts| 23 +-
9 files changed, 94 insertions(+), 379 deletions(-)
create mode 100644 arch/arm/dts/imx6qdl-phytec-mira.dtsi
diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts
b/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts
index 21cbb5f944c9..8ce0066c691d 100644
--- a/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts
+++ b/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts
@@ -15,6 +15,7 @@
#include
#include "imx6dl.dtsi"
#include "imx6qdl-phytec-phycore-som.dtsi"
+#include "imx6qdl-phytec-mira.dtsi"
#include "imx6qdl-phytec-state.dtsi"
/ {
@@ -22,10 +23,6 @@
compatible = "phytec,imx6dl-pcm058-emmc", "fsl,imx6dl";
};
-&ecspi1 {
- status = "okay";
-};
-
&eeprom {
status = "okay";
};
@@ -38,7 +35,7 @@
status = "okay";
};
-&flash {
+&m25p80 {
status = "okay";
};
@@ -52,22 +49,6 @@
&usdhc1 {
status = "okay";
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "barebox";
- reg = <0x0 0xe>;
- };
-
- partition@e {
- label = "barebox-environment";
- reg = <0xe 0x2>;
- };
- };
};
&usdhc4 {
diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts
b/arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts
index b8efb95ee08a..bf3a03c4f62a 100644
--- a/arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts
+++ b/arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts
@@ -9,6 +9,7 @@
#include
#include "imx6dl.dtsi"
#include "imx6qdl-phytec-phycore-som.dtsi"
+#include "imx6qdl-phytec-mira.dtsi"
#include "imx6qdl-phytec-state.dtsi"
/ {
@@ -16,10 +17,6 @@
compatible = "phytec,imx6dl-pcm058-emmc", "fsl,imx6dl";
};
-&ecspi1 {
- status = "okay";
-};
-
&eeprom {
status = "okay";
};
@@ -32,7 +29,7 @@
status = "okay";
};
-&flash {
+&m25p80 {
status = "okay";
};
@@ -46,19 +43,6 @@
&usdhc1 {
status = "okay";
-
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "barebox";
- reg = <0x0 0xe>;
- };
-
- partition@e {
- label = "barebox-environment";
- reg = <0xe 0x2>;
- };
};
&usdhc4 {
diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-lc-nand.dts
b/arch/arm/dts/imx6dl-phytec-phycore-som-lc-nand.dts
index 4d38d1698a48..654f6c152dee 100644
--- a/arch/arm/dts/imx6dl-phytec-phycore-som-lc-nand.dts
+++ b/arch/arm/dts/imx6dl-phytec-phycore-som-lc-nand.dts
@@ -9,6 +9,7 @@
#include
#include "imx6dl.dtsi"
#include "imx6qdl-phytec-phycore-som.dtsi"
+#include "imx6qdl-phytec-mira.dtsi"
#include "imx6qdl-phytec-state.dtsi"
/ {
@@ -42,17 +43,4 @@
&usdhc1 {
status = "okay";
-
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "barebox";
- reg = <0x0 0xe>;
- };
-
- partition@e {
- label = "barebox-environment";
- reg = <0xe 0x2>;
- };
};
diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts
b/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts
index 3ad3723d2893..18d14d6b945c 100644
--- a/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts
+++ b/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts
@@ -14,6 +14,7 @@
#include
#include "imx6dl.dtsi"
#include "imx6qdl-phytec-phycore-som.dtsi"
+#include "imx6qdl-phy
[PATCH 2/2] ARM: dts: imx6qdl: pfla02: Remove fec phy-supply
There is no driver for the phyFLEX-i.MX 6 phy-supply regulator in
the barebox. Use a dummy regulator instead by simply deleting the
phy-supply property.
Signed-off-by: Stefan Riedmueller
---
arch/arm/dts/imx6qdl-phytec-pfla02.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
index f0bba2e09881..846ebbe6b18b 100644
--- a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
@@ -86,6 +86,10 @@
};
};
+&fec {
+ /delete-property/ phy-supply;
+};
+
&gpmi {
partitions {
compatible = "fixed-partitions";
--
2.7.4
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[PATCH 1/2] net: fec_imx: Fix resource rollback with regulator errors
When the driver is not able to get or control the phy regulator memory
resources are already acquired and need to be released during rollback.
Signed-off-by: Stefan Riedmueller
---
drivers/net/fec_imx.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/net/fec_imx.c b/drivers/net/fec_imx.c
index 31c91021893a..5ef1d4359e91 100644
--- a/drivers/net/fec_imx.c
+++ b/drivers/net/fec_imx.c
@@ -781,7 +781,8 @@ static int fec_probe(struct device_d *dev)
if (IS_ERR(fec->reg_phy)) {
if (PTR_ERR(fec->reg_phy) == -EPROBE_DEFER) {
ret = -EPROBE_DEFER;
- goto disable_clk;
+ fec->reg_phy = NULL;
+ goto release_res;
}
fec->reg_phy = NULL;
}
@@ -789,7 +790,7 @@ static int fec_probe(struct device_d *dev)
ret = regulator_enable(fec->reg_phy);
if (ret) {
dev_err(dev, "Failed to enable phy regulator: %d\n", ret);
- goto disable_clk;
+ goto release_res;
}
phy_reset = of_get_named_gpio(dev->device_node, "phy-reset-gpios", 0);
--
2.7.4
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[PATCH] nvmem: Fix read/write access to partition devices
Partition devices are not directly associated with the nvmem instance but via
their master cdev. Thus reading and writing needs to be handled via the
master.
Signed-off-by: Stefan Riedmueller
---
drivers/nvmem/core.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/nvmem/core.c b/drivers/nvmem/core.c
index 25924872efa2..82e9d1996428 100644
--- a/drivers/nvmem/core.c
+++ b/drivers/nvmem/core.c
@@ -57,9 +57,14 @@ int nvmem_device_write(struct nvmem_device *nvmem, unsigned
int offset,
static ssize_t nvmem_cdev_read(struct cdev *cdev, void *buf, size_t count,
loff_t offset, unsigned long flags)
{
- struct nvmem_device *nvmem = container_of(cdev, struct nvmem_device,
cdev);
+ struct nvmem_device *nvmem;
ssize_t retlen;
+ if (!cdev->master)
+ nvmem = container_of(cdev, struct nvmem_device, cdev);
+ else
+ nvmem = container_of(cdev->master, struct nvmem_device, cdev);
+
dev_dbg(cdev->dev, "read ofs: 0x%08llx count: 0x%08zx\n",
offset, count);
@@ -71,9 +76,14 @@ static ssize_t nvmem_cdev_read(struct cdev *cdev, void *buf,
size_t count,
static ssize_t nvmem_cdev_write(struct cdev *cdev, const void *buf, size_t
count,
loff_t offset, unsigned long flags)
{
- struct nvmem_device *nvmem = container_of(cdev, struct nvmem_device,
cdev);
+ struct nvmem_device *nvmem;
ssize_t retlen;
+ if (!cdev->master)
+ nvmem = container_of(cdev, struct nvmem_device, cdev);
+ else
+ nvmem = container_of(cdev->master, struct nvmem_device, cdev);
+
dev_dbg(cdev->dev, "write ofs: 0x%08llx count: 0x%08zx\n",
offset, count);
--
2.7.4
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[PATCH v2] mtd: ubi: Max out wear-leveling threshold
Due to the recursive ubi_thread implementation in the barebox, a large amount of wear-leveling can lead to a stack overflow. This was observed during extensive ubi stress tests with the linux kernel and periodic power cycles. We found that if the wear-leveling threshold is exceeded and a large amount of erase blocks need wear-leveling the stack can overflow. The hardware used to observe this was a phyCORE-i.MX 6 with 1GB NAND flash. As the kernel is perfectly capable of handling wear-leveling we can disable wear-leveling in the barebox by maxing out the threshold and removing its Kconfig option. Signed-off-by: Stefan Riedmueller --- Changes in v2: - Remove threshold config completely instead of just maxing out the default --- drivers/mtd/ubi/Kconfig | 17 - drivers/mtd/ubi/build.c | 2 +- drivers/mtd/ubi/ubi.h | 11 +++ drivers/mtd/ubi/wl.c| 8 4 files changed, 12 insertions(+), 26 deletions(-) diff --git a/drivers/mtd/ubi/Kconfig b/drivers/mtd/ubi/Kconfig index 9a344082b7bb..ed2f13d14c30 100644 --- a/drivers/mtd/ubi/Kconfig +++ b/drivers/mtd/ubi/Kconfig @@ -10,23 +10,6 @@ menuconfig MTD_UBI if MTD_UBI -config MTD_UBI_WL_THRESHOLD - int "UBI wear-leveling threshold" - default 4096 - range 2 65536 - help - This parameter defines the maximum difference between the highest - erase counter value and the lowest erase counter value of eraseblocks - of UBI devices. When this threshold is exceeded, UBI starts performing - wear leveling by means of moving data from eraseblock with low erase - counter to eraseblocks with high erase counter. - - The default value should be OK for SLC NAND flashes, NOR flashes and - other flashes which have eraseblock life-cycle 10 or more. - However, in case of MLC NAND flashes which typically have eraseblock - life-cycle less than 1, the threshold should be lessened (e.g., - to 128 or 256, although it does not have to be power of 2). - config MTD_UBI_BEB_LIMIT int "Maximum expected bad eraseblock count per 1024 eraseblocks" default 20 diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c index 493c778c3fdb..604fe87e53b6 100644 --- a/drivers/mtd/ubi/build.c +++ b/drivers/mtd/ubi/build.c @@ -655,7 +655,7 @@ int ubi_attach_mtd_dev(struct mtd_info *mtd, int ubi_num, ubi->vol_count - UBI_INT_VOL_COUNT, UBI_INT_VOL_COUNT, ubi->vtbl_slots); ubi_msg(ubi, "max/mean erase counter: %d/%d, WL threshold: %d, image sequence number: %u", - ubi->max_ec, ubi->mean_ec, CONFIG_MTD_UBI_WL_THRESHOLD, + ubi->max_ec, ubi->mean_ec, UBI_WL_THRESHOLD, ubi->image_seq); ubi_msg(ubi, "available PEBs: %d, total reserved PEBs: %d, PEBs reserved for bad PEB handling: %d", ubi->avail_pebs, ubi->rsvd_pebs, ubi->beb_rsvd_pebs); diff --git a/drivers/mtd/ubi/ubi.h b/drivers/mtd/ubi/ubi.h index 922c1a3c8b49..7d07bbf19720 100644 --- a/drivers/mtd/ubi/ubi.h +++ b/drivers/mtd/ubi/ubi.h @@ -69,6 +69,17 @@ */ #define UBI_PROT_QUEUE_LEN 10 +/* + * Maximum difference between two erase counters. If this threshold is + * exceeded, the WL sub-system starts moving data from used physical + * eraseblocks with low erase counter to free physical eraseblocks with high + * erase counter. + * Extensive wear-leveling in the barebox can lead to stack overflows. Thus + * disable it by setting the threshold to the OS's max configurable value and + * leave wear-leveling to the OS. + */ +#define UBI_WL_THRESHOLD 65536 + /* The volume ID/LEB number/erase counter is unknown */ #define UBI_UNKNOWN -1 diff --git a/drivers/mtd/ubi/wl.c b/drivers/mtd/ubi/wl.c index cf90ecfb2385..013ba3e1ffc7 100644 --- a/drivers/mtd/ubi/wl.c +++ b/drivers/mtd/ubi/wl.c @@ -101,14 +101,6 @@ #define WL_RESERVED_PEBS 1 /* - * Maximum difference between two erase counters. If this threshold is - * exceeded, the WL sub-system starts moving data from used physical - * eraseblocks with low erase counter to free physical eraseblocks with high - * erase counter. - */ -#define UBI_WL_THRESHOLD CONFIG_MTD_UBI_WL_THRESHOLD - -/* * When a physical eraseblock is moved, the WL sub-system has to pick the target * physical eraseblock to move to. The simplest way would be just to pick the * one with the highest erase counter. But in certain workloads this could lead -- 2.7.4 ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH] mtd: ubi: Max out default wear-leveling threshold
Due to the recursive ubi_thread implementation in the barebox, a large amount of wear-leveling can lead to a stack overflow. This was observed during extensive ubi stress tests with the linux kernel and periodic power cycles. We found that if the wear-leveling threshold is exceeded and a large amount of erase blocks need wear-leveling the stack can overflow. The hardware used to observe this was a phyCORE-i.MX 6 with 1GB NAND flash. As the kernel is perfectly capable of handling wear-leveling we can increase the wear-leveling threshold in the barebox to leave it to the kernel. To minimize the chance of wear-leveling in the barebox max out the threshold. Signed-off-by: Stefan Riedmueller --- drivers/mtd/ubi/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/ubi/Kconfig b/drivers/mtd/ubi/Kconfig index 9a344082b7bb..509a1f77ddcd 100644 --- a/drivers/mtd/ubi/Kconfig +++ b/drivers/mtd/ubi/Kconfig @@ -12,7 +12,7 @@ if MTD_UBI config MTD_UBI_WL_THRESHOLD int "UBI wear-leveling threshold" - default 4096 + default 65536 range 2 65536 help This parameter defines the maximum difference between the highest -- 2.7.4 ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH] ARM: dts: am335x-phytec-state: Add backend-storage-type
Add the backend-storage-type for both states and set it to "direct" as the backend is an EEPROM. Signed-off-by: Stefan Riedmueller --- arch/arm/dts/am335x-phytec-state.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/dts/am335x-phytec-state.dtsi b/arch/arm/dts/am335x-phytec-state.dtsi index 1f61cf5a2e6c..af4da4ea6469 100644 --- a/arch/arm/dts/am335x-phytec-state.dtsi +++ b/arch/arm/dts/am335x-phytec-state.dtsi @@ -23,6 +23,7 @@ compatible = "barebox,state"; backend-type = "raw"; backend = <&backend_state_mac_eeprom>; + backend-storage-type = "direct"; backend-stridesize = <40>; keep-previous-content; @@ -44,6 +45,7 @@ compatible = "barebox,state"; backend-type = "raw"; backend = <&backend_state_update_eeprom>; + backend-storage-type = "direct"; backend-stridesize = <54>; keep-previous-content; -- 2.7.4 ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH v2 3/8] ARM: dts: imx6ul: phycore: Add eeprom label
Add a label for the EEPROM to be able to address it for the state
framework.
Signed-off-by: Stefan Riedmueller
---
No changes in v2
---
arch/arm/dts/imx6ul-phytec-phycore-som.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
index 964f91950d93..1ef9d547822e 100644
--- a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
+++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
@@ -79,7 +79,7 @@
clock-frequency = <10>;
status = "disabled";
- eeprom@52 {
+ eeprom: eeprom@52 {
compatible = "cat,24c32";
reg = <0x52>;
};
--
2.7.4
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[PATCH v2 4/8] ARM: dts: imx6ul: phycore: Add state framework
From: Daniel Schultz
Add the state framework with EEPROM backend.
Signed-off-by: Daniel Schultz
Signed-off-by: Stefan Riedmueller
---
Changes in v2:
- Added backend-storage-type
- Added missing Signed-off-by
---
arch/arm/dts/imx6ul-phytec-phycore-som.dts | 5 ++
arch/arm/dts/imx6ul-phytec-state.dtsi | 82 +
arch/arm/dts/imx6ull-phytec-phycore-som.dts | 5 ++
3 files changed, 92 insertions(+)
create mode 100644 arch/arm/dts/imx6ul-phytec-state.dtsi
diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dts
b/arch/arm/dts/imx6ul-phytec-phycore-som.dts
index 6d1876702d1b..11418ea7f038 100644
--- a/arch/arm/dts/imx6ul-phytec-phycore-som.dts
+++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dts
@@ -14,6 +14,7 @@
#include
#include "imx6ul-phytec-phycore-som.dtsi"
+#include "imx6ul-phytec-state.dtsi"
/ {
model = "Phytec phyCORE-i.MX6 Ultra Lite SOM";
@@ -32,6 +33,10 @@
status = "okay";
};
+&state {
+ status = "okay";
+};
+
&uart1 {
status = "okay";
};
diff --git a/arch/arm/dts/imx6ul-phytec-state.dtsi
b/arch/arm/dts/imx6ul-phytec-state.dtsi
new file mode 100644
index ..78a32ed96b03
--- /dev/null
+++ b/arch/arm/dts/imx6ul-phytec-state.dtsi
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 PHYTEC Messtechnik GmbH,
+ * Author: Stefan Riedmueller
+ */
+
+/ {
+ aliases {
+ state = &state;
+ };
+
+ state: imx6ul_phytec_boot_state {
+ magic = <0x883b86a6>;
+ compatible = "barebox,state";
+ backend-type = "raw";
+ backend = <&backend_update_eeprom>;
+ backend-storage-type = "direct";
+ backend-stridesize = <54>;
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ bootstate {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ last_chosen {
+ reg = <0x0 0x4>;
+ type = "uint32";
+ };
+ system0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ remaining_attempts {
+ reg = <0x4 0x4>;
+ type = "uint32";
+ default = <3>;
+ };
+ priority {
+ reg = <0x8 0x4>;
+ type = "uint32";
+ default = <21>;
+ };
+ ok {
+ reg = <0xc 0x4>;
+ type = "uint32";
+ default = <0>;
+ };
+ };
+ system1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ remaining_attempts {
+ reg = <0x10 0x4>;
+ type = "uint32";
+ default = <3>;
+ };
+ priority {
+ reg = <0x14 0x4>;
+ type = "uint32";
+ default = <20>;
+ };
+ ok {
+ reg = <0x18 0x4>;
+ type = "uint32";
+ default = <0>;
+ };
+ };
+ };
+ };
+};
+
+&eeprom {
+ partitions {
+ compatible = "fixed-partitions";
+ #size-cells = <1>;
+ #address-cells = <1>;
+ backend_update_eeprom: state@0 {
+ reg = <0x0 0x100>;
+ label = "update-eeprom";
+ };
+ };
+};
diff --git a/arch/arm/dts/imx6ull-phytec-phycore-som.dts
b/arch/arm/dts/imx6ull-phytec-phycore-som.dts
index 4d73010131ee..86f43a4632a7 100644
--- a/arch/arm/dts/imx6ull-phytec-phycore-som.dts
+++ b/arch/arm/dts/imx6ull-phytec-phycore-som.dts
@@ -14,6 +14
[PATCH v2 8/8] ARM: dts: imx6ul: phycore: Add phyCORE-i.MX 6ULL with eMMC
Add a phyCORE-i.MX 6ULL with eMMC. It has following features:
- i.MX 6ULL Y2 792 MHz
- 512 MB RAM
- 4 GB eMMC
- 10/100 MBits Ethernet
- USB OTG
- USB Host
Signed-off-by: Stefan Riedmueller
---
No changes in v2
---
arch/arm/boards/phytec-som-imx6/lowlevel.c | 1 +
arch/arm/dts/Makefile| 3 +-
arch/arm/dts/imx6ull-phytec-phycore-som-emmc.dts | 43
images/Makefile.imx | 5 +++
4 files changed, 51 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/imx6ull-phytec-phycore-som-emmc.dts
diff --git a/arch/arm/boards/phytec-som-imx6/lowlevel.c
b/arch/arm/boards/phytec-som-imx6/lowlevel.c
index 494087ab1479..07bb0ed1b569 100644
--- a/arch/arm/boards/phytec-som-imx6/lowlevel.c
+++ b/arch/arm/boards/phytec-som-imx6/lowlevel.c
@@ -121,3 +121,4 @@ PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_2gib,
imx6q_phytec_phycore_som_
PHYTEC_ENTRY(start_phytec_phycore_imx6ul_som_nand_512mb,
imx6ul_phytec_phycore_som_nand, SZ_512M, false);
PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_lc_nand_256mb,
imx6ull_phytec_phycore_som_lc_nand, SZ_256M, false);
PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_nand_512mb,
imx6ull_phytec_phycore_som_nand, SZ_512M, false);
+PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_emmc_512mb,
imx6ull_phytec_phycore_som_emmc, SZ_512M, false);
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index c96f040ae311..87ddc57b899c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -68,7 +68,8 @@ pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) +=
imx6q-phytec-pbaa03.dtb.o \
imx6dl-phytec-phycore-som-lc-emmc.dtb.o \
imx6ul-phytec-phycore-som-nand.dtb.o \
imx6ull-phytec-phycore-som-lc-nand.dtb.o \
- imx6ull-phytec-phycore-som-nand.dtb.o
+ imx6ull-phytec-phycore-som-nand.dtb.o \
+ imx6ull-phytec-phycore-som-emmc.dtb.o
pbl-dtb-$(CONFIG_MACH_PHYTEC_PHYCORE_IMX7) += imx7d-phyboard-zeta.dtb.o
pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX8MQ) += imx8mq-phytec-phycore-som.dtb.o
pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) +=
armada-xp-openblocks-ax3-4-bb.dtb.o
diff --git a/arch/arm/dts/imx6ull-phytec-phycore-som-emmc.dts
b/arch/arm/dts/imx6ull-phytec-phycore-som-emmc.dts
new file mode 100644
index ..aa162cc42d07
--- /dev/null
+++ b/arch/arm/dts/imx6ull-phytec-phycore-som-emmc.dts
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright (C) 2019 PHYTEC Messtechnik GmbH
+ * Author: Stefan Riedmueller
+ */
+
+/dts-v1/;
+
+#include
+#include "imx6ul-phytec-phycore-som.dtsi"
+
+/ {
+ model = "PHYTEC phyCORE-i.MX6 ULL SOM with eMMC";
+ compatible = "phytec,imx6ul-pcl063-emmc", "fsl,imx6ull";
+};
+
+&fec1 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&usdhc1 {
+ status = "okay";
+};
+
+&usdhc2 {
+ status = "okay";
+};
+
+&usbotg1 {
+ status = "okay";
+};
+
+&usbotg2 {
+ status = "okay";
+};
diff --git a/images/Makefile.imx b/images/Makefile.imx
index 8aedc906dc84..a287c11c4042 100644
--- a/images/Makefile.imx
+++ b/images/Makefile.imx
@@ -519,6 +519,11 @@
CFG_start_phytec_phycore_imx6ull_som_nand_512mb.pblb.imximg = $(board)/phytec-so
FILE_barebox-phytec-phycore-imx6ull-nand-512mb.img =
start_phytec_phycore_imx6ull_som_nand_512mb.pblb.imximg
image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) +=
barebox-phytec-phycore-imx6ull-nand-512mb.img
+pblb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) +=
start_phytec_phycore_imx6ull_som_emmc_512mb
+CFG_start_phytec_phycore_imx6ull_som_emmc_512mb.pblb.imximg =
$(board)/phytec-som-imx6/flash-header-phytec-pcl063-512mb.imxcfg
+FILE_barebox-phytec-phycore-imx6ull-emmc-512mb.img =
start_phytec_phycore_imx6ull_som_emmc_512mb.pblb.imximg
+image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) +=
barebox-phytec-phycore-imx6ull-emmc-512mb.img
+
pblb-$(CONFIG_MACH_TECHNEXION_PICO_HOBBIT) += start_imx6ul_pico_hobbit_256mb
CFG_start_imx6ul_pico_hobbit_256mb.pblb.imximg =
$(board)/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-256.imxcfg
FILE_barebox-imx6ul-pico-hobbit-256mb.img =
start_imx6ul_pico_hobbit_256mb.pblb.imximg
--
2.7.4
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[PATCH v2 1/8] ARM: phytec-som-imx6: Add low cost variant for imx6dl phycore
The phyCORE-i.MX 6Solo/DualLight is available with low-cost and
full-featured phyBOARD-Mira. One crucial difference is the supported
max. ethernet speed. On the full-featured Mira it is 1000 MBit/s but on
the low-cost Mira it is only 100 MBit/s. To cover this difference two
different images are necessary for low-cost and full-featured. Thus a
low-cost variant is added for the phyCORE-i.MX 6Solo with NAND and the
phyCORE-i.MX 6 DualLight with eMMC.
Signed-off-by: Stefan Riedmueller
---
No changes in v2
---
arch/arm/boards/phytec-som-imx6/lowlevel.c | 2 +
arch/arm/dts/Makefile | 2 +
arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts| 2 +-
arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts | 65 ++
arch/arm/dts/imx6dl-phytec-phycore-som-lc-nand.dts | 57 +++
arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts| 2 +-
images/Makefile.imx| 10
7 files changed, 138 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts
create mode 100644 arch/arm/dts/imx6dl-phytec-phycore-som-lc-nand.dts
diff --git a/arch/arm/boards/phytec-som-imx6/lowlevel.c
b/arch/arm/boards/phytec-som-imx6/lowlevel.c
index 915534ea9455..0f8d591b3a71 100644
--- a/arch/arm/boards/phytec-som-imx6/lowlevel.c
+++ b/arch/arm/boards/phytec-som-imx6/lowlevel.c
@@ -109,8 +109,10 @@ PHYTEC_ENTRY(start_phytec_phyboard_subra_512mb_1bank,
imx6dl_phytec_phyboard_sub
PHYTEC_ENTRY(start_phytec_phyboard_subra_1gib_1bank,
imx6q_phytec_phyboard_subra, SZ_1G, false);
PHYTEC_ENTRY(start_phytec_phycore_imx6dl_som_nand_256mb,
imx6dl_phytec_phycore_som_nand, SZ_256M, true);
+PHYTEC_ENTRY(start_phytec_phycore_imx6dl_som_lc_nand_256mb,
imx6dl_phytec_phycore_som_lc_nand, SZ_256M, true);
PHYTEC_ENTRY(start_phytec_phycore_imx6dl_som_nand_1gib,
imx6dl_phytec_phycore_som_nand, SZ_1G, true);
PHYTEC_ENTRY(start_phytec_phycore_imx6dl_som_emmc_1gib,
imx6dl_phytec_phycore_som_emmc, SZ_1G, true);
+PHYTEC_ENTRY(start_phytec_phycore_imx6dl_som_lc_emmc_1gib,
imx6dl_phytec_phycore_som_lc_emmc, SZ_1G, true);
PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_nand_1gib,
imx6q_phytec_phycore_som_nand, SZ_1G, true);
PHYTEC_ENTRY(start_phytec_phycore_imx6qp_som_nand_1gib,
imx6qp_phytec_phycore_som_nand, SZ_1G, true);
PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_1gib,
imx6q_phytec_phycore_som_emmc, SZ_1G, true);
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 561653930b20..2a2d7a55b820 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -63,7 +63,9 @@ pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) +=
imx6q-phytec-pbaa03.dtb.o \
imx6q-phytec-phycore-som-emmc.dtb.o \
imx6qp-phytec-phycore-som-nand.dtb.o \
imx6dl-phytec-phycore-som-nand.dtb.o \
+ imx6dl-phytec-phycore-som-lc-nand.dtb.o \
imx6dl-phytec-phycore-som-emmc.dtb.o \
+ imx6dl-phytec-phycore-som-lc-emmc.dtb.o \
imx6ul-phytec-phycore-som.dtb.o \
imx6ull-phytec-phycore-som-lc.dtb.o \
imx6ull-phytec-phycore-som.dtb.o
diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts
b/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts
index e602b77e9940..a04e37f80363 100644
--- a/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts
+++ b/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts
@@ -30,7 +30,7 @@
};
ðphy {
- max-speed = <100>;
+ max-speed = <1000>;
};
&fec {
diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts
b/arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts
new file mode 100644
index ..5d9727ec5b80
--- /dev/null
+++ b/arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright (C) 2019 PHYTEC Messtechnik GmbH,
+ * Author: Stefan Riedmueller
+ */
+
+/dts-v1/;
+
+#include
+#include "imx6dl.dtsi"
+#include "imx6qdl-phytec-phycore-som.dtsi"
+
+/ {
+ model = "PHYTEC phyCORE-i.MX6 DualLite/SOLO with eMMC low-cost";
+ compatible = "phytec,imx6dl-pcm058-emmc", "fsl,imx6dl";
+};
+
+&ecspi1 {
+ status = "okay";
+};
+
+&eeprom {
+ status = "okay";
+};
+
+ðphy {
+ max-speed = <100>;
+};
+
+&fec {
+ status = "okay";
+};
+
+&flash {
+ status = "okay";
+};
+
+&usbh1 {
+ status = "okay";
+};
+
+&usbotg {
+ status = "okay";
+};
+
+&usdhc1 {
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "barebox";
+ reg =
[PATCH v2 6/8] ARM: phytec-som-imx: imx6ul: Add eMMC support
Add initial support for phyCORE-i.MX 6UL/ULL with eMMC. Including board
code and default environment.
Signed-off-by: Stefan Riedmueller
---
No changes in v2
---
arch/arm/boards/phytec-som-imx6/board.c| 18 +++---
.../defaultenv-physom-imx6ul-phycore/boot/emmc | 5 +
.../defaultenv-physom-imx6ul-phycore/boot/mmc | 5 +
.../defaultenv-physom-imx6ul-phycore/init/automount| 5 +
.../defaultenv-physom-imx6ul-phycore/init/bootsource | 17 +
5 files changed, 47 insertions(+), 3 deletions(-)
create mode 100644
arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6ul-phycore/boot/emmc
create mode 100644
arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6ul-phycore/boot/mmc
create mode 100644
arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6ul-phycore/init/bootsource
diff --git a/arch/arm/boards/phytec-som-imx6/board.c
b/arch/arm/boards/phytec-som-imx6/board.c
index cf50ad99b2fc..730115702bb0 100644
--- a/arch/arm/boards/phytec-som-imx6/board.c
+++ b/arch/arm/boards/phytec-som-imx6/board.c
@@ -190,7 +190,8 @@ static int physom_imx6_devices_init(void)
default_environment_path = "/chosen/environment-spinor";
default_envdev = "SPI NOR flash";
- } else if (of_machine_is_compatible("phytec,imx6ul-pcl063-nand")) {
+ } else if (of_machine_is_compatible("phytec,imx6ul-pcl063-nand")
+ || of_machine_is_compatible("phytec,imx6ul-pcl063-emmc")) {
barebox_set_hostname("phyCORE-i.MX6UL");
default_environment_path = "/chosen/environment-nand";
default_envdev = "NAND flash";
@@ -236,6 +237,10 @@ static int physom_imx6_devices_init(void)
imx6_bbu_internal_mmc_register_handler("mmc3",
"/dev/mmc3",
BBU_HANDLER_FLAG_DEFAULT);
+ } else if (of_machine_is_compatible("phytec,imx6ul-pcl063-emmc")) {
+ imx6_bbu_internal_mmc_register_handler("mmc1",
+ "/dev/mmc1",
+ BBU_HANDLER_FLAG_DEFAULT);
} else {
imx6_bbu_nand_register_handler("nand",
BBU_HANDLER_FLAG_DEFAULT);
}
@@ -243,13 +248,20 @@ static int physom_imx6_devices_init(void)
defaultenv_append_directory(defaultenv_physom_imx6);
/* Overwrite file /env/init/automount */
- if (of_machine_is_compatible("phytec,imx6qp-pcm058-nand")
+ if (of_machine_is_compatible("phytec,imx6q-pfla02")
+ || of_machine_is_compatible("phytec,imx6dl-pfla02")
+ || of_machine_is_compatible("phytec,imx6s-pfla02")
+ || of_machine_is_compatible("phytec,imx6q-pcaaxl3")) {
+ defaultenv_append_directory(defaultenv_physom_imx6);
+ } else if (of_machine_is_compatible("phytec,imx6qp-pcm058-nand")
|| of_machine_is_compatible("phytec,imx6q-pcm058-nand")
|| of_machine_is_compatible("phytec,imx6q-pcm058-emmc")
|| of_machine_is_compatible("phytec,imx6dl-pcm058-nand")
|| of_machine_is_compatible("phytec,imx6dl-pcm058-emmc")) {
+ defaultenv_append_directory(defaultenv_physom_imx6);
defaultenv_append_directory(defaultenv_physom_imx6_phycore);
- } else if (of_machine_is_compatible("phytec,imx6ul-pcl063-nand")) {
+ } else if (of_machine_is_compatible("phytec,imx6ul-pcl063-nand")
+ || of_machine_is_compatible("phytec,imx6ul-pcl063-emmc")) {
defaultenv_append_directory(defaultenv_physom_imx6ul_phycore);
}
diff --git
a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6ul-phycore/boot/emmc
b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6ul-phycore/boot/emmc
new file mode 100644
index ..15cba6f5ac1b
--- /dev/null
+++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6ul-phycore/boot/emmc
@@ -0,0 +1,5 @@
+#!/bin/sh
+
+global.bootm.image="/mnt/emmc/zImage"
+global.bootm.oftree="/mnt/emmc/oftree"
+global.linux.bootargs.dyn.root="root=/dev/mmcblk1p2
rootflags='discard,data=journal'"
diff --git
a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6ul-phycore/boot/mmc
b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6ul-phycore/boot/mmc
new file mode 100644
index ..8de2efa997d9
--- /dev/null
+++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6ul-phycore/boot/mmc
@@ -0,0 +1,5 @@
+#!/bin/sh
+
+global.bootm.image="/mnt/mmc/zImage"
+global.bootm.oftree="/mnt/mmc/oftree"
[PATCH v2 7/8] ARM: dts: imx6ul: phycore: Add support for eMMC
Add support for phyCORE-i.MX 6UL/ULL modules with eMMC instead of NAND
flash.
Signed-off-by: Stefan Riedmueller
---
No changes in v2
---
arch/arm/dts/imx6ul-phytec-phycore-som.dtsi | 42 +
1 file changed, 42 insertions(+)
diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
index 1ef9d547822e..0ec7eae1eff0 100644
--- a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
+++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
@@ -25,6 +25,12 @@
device-path = &usdhc1, "partname:barebox-environment";
status = "disabled";
};
+
+ environment-sd2 {
+ compatible = "barebox,environment";
+ device-path = &usdhc2, "partname:barebox-environment";
+ status = "disabled";
+ };
};
};
@@ -125,6 +131,27 @@
};
};
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ bus-width = <8>;
+ non-removable;
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "barebox";
+ reg = <0x0 0xe>;
+ };
+
+ partition@e {
+ label = "barebox-environment";
+ reg = <0xe 0x2>;
+ };
+};
+
&iomuxc {
pinctrl-names = "default";
@@ -196,6 +223,21 @@
MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059
/* SD1 CD */
>;
};
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
+ >;
+ };
};
};
--
2.7.4
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[PATCH v2 2/8] ARM: dts: imx6qdl: phycore: Add state framework
From: Daniel Schultz
Add the state framework with EEPROM backend.
Signed-off-by: Daniel Schultz
Signed-off-by: Stefan Riedmueller
---
Changes in v2:
- Added backend-storage-type
---
arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts| 1 +
arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts | 1 +
arch/arm/dts/imx6dl-phytec-phycore-som-lc-nand.dts | 1 +
arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts| 1 +
arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts | 1 +
arch/arm/dts/imx6q-phytec-phycore-som-nand.dts | 1 +
arch/arm/dts/imx6qdl-phytec-state.dtsi | 82 ++
7 files changed, 88 insertions(+)
create mode 100644 arch/arm/dts/imx6qdl-phytec-state.dtsi
diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts
b/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts
index a04e37f80363..21cbb5f944c9 100644
--- a/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts
+++ b/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts
@@ -15,6 +15,7 @@
#include
#include "imx6dl.dtsi"
#include "imx6qdl-phytec-phycore-som.dtsi"
+#include "imx6qdl-phytec-state.dtsi"
/ {
model = "Phytec phyCORE-i.MX6 DualLite/SOLO with eMMC";
diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts
b/arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts
index 5d9727ec5b80..b8efb95ee08a 100644
--- a/arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts
+++ b/arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts
@@ -9,6 +9,7 @@
#include
#include "imx6dl.dtsi"
#include "imx6qdl-phytec-phycore-som.dtsi"
+#include "imx6qdl-phytec-state.dtsi"
/ {
model = "PHYTEC phyCORE-i.MX6 DualLite/SOLO with eMMC low-cost";
diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-lc-nand.dts
b/arch/arm/dts/imx6dl-phytec-phycore-som-lc-nand.dts
index e119e4c0d4fc..4d38d1698a48 100644
--- a/arch/arm/dts/imx6dl-phytec-phycore-som-lc-nand.dts
+++ b/arch/arm/dts/imx6dl-phytec-phycore-som-lc-nand.dts
@@ -9,6 +9,7 @@
#include
#include "imx6dl.dtsi"
#include "imx6qdl-phytec-phycore-som.dtsi"
+#include "imx6qdl-phytec-state.dtsi"
/ {
model = "PHYTEC phyCORE-i.MX6 Duallite/SOLO with NAND low-cost";
diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts
b/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts
index 287d876e41ed..3ad3723d2893 100644
--- a/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts
+++ b/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts
@@ -14,6 +14,7 @@
#include
#include "imx6dl.dtsi"
#include "imx6qdl-phytec-phycore-som.dtsi"
+#include "imx6qdl-phytec-state.dtsi"
/ {
model = "Phytec phyCORE-i.MX6 Duallite/SOLO with NAND";
diff --git a/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts
b/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts
index 94a70389f084..7a86d5b94daf 100644
--- a/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts
+++ b/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts
@@ -14,6 +14,7 @@
#include
#include "imx6q.dtsi"
#include "imx6qdl-phytec-phycore-som.dtsi"
+#include "imx6qdl-phytec-state.dtsi"
/ {
model = "Phytec phyCORE-i.MX6 Quad with eMMC";
diff --git a/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts
b/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts
index 6d82ec34d6e5..96d1de224c9e 100644
--- a/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts
+++ b/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts
@@ -14,6 +14,7 @@
#include
#include "imx6q.dtsi"
#include "imx6qdl-phytec-phycore-som.dtsi"
+#include "imx6qdl-phytec-state.dtsi"
/ {
model = "Phytec phyCORE-i.MX6 Quad with NAND";
diff --git a/arch/arm/dts/imx6qdl-phytec-state.dtsi
b/arch/arm/dts/imx6qdl-phytec-state.dtsi
new file mode 100644
index ..1522b92be15b
--- /dev/null
+++ b/arch/arm/dts/imx6qdl-phytec-state.dtsi
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright (C) 2019 PHYTEC Messtechnik GmbH,
+ * Author: Daniel Schultz
+ */
+
+/ {
+ aliases {
+ state = &state;
+ };
+
+ state: imx6qdl_phytec_boot_state {
+ magic = <0x883b86a6>;
+ compatible = "barebox,state";
+ backend-type = "raw";
+ backend = <&backend_update_eeprom>;
+ backend-storage-type = "direct";
+ backend-stridesize = <54>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ bootstate {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ last_chosen {
+ reg = <0x0 0x4>;
+ type = "uint32";
+ };
+
[PATCH v2 5/8] ARM: imx6ul: phycore: Prepare for eMMC module
Prepare for the new phyCORE-i.MX 6UL/ULL eMMC module by extending the
dts filenames by their boot medium. Also add the boot medium to the
compatible to be able to perform boot medium dependent setup code.
Signed-off-by: Stefan Riedmueller
---
No changes in v2
---
arch/arm/boards/phytec-som-imx6/board.c| 4 +-
arch/arm/boards/phytec-som-imx6/lowlevel.c | 6 +--
arch/arm/dts/Makefile | 6 +--
arch/arm/dts/imx6ul-phytec-phycore-som-nand.dts| 48 +++
arch/arm/dts/imx6ul-phytec-phycore-som.dts | 54 --
dts => imx6ull-phytec-phycore-som-lc-nand.dts} | 6 +--
...som.dts => imx6ull-phytec-phycore-som-nand.dts} | 14 ++
images/Makefile.imx| 28 +--
8 files changed, 77 insertions(+), 89 deletions(-)
create mode 100644 arch/arm/dts/imx6ul-phytec-phycore-som-nand.dts
delete mode 100644 arch/arm/dts/imx6ul-phytec-phycore-som.dts
rename arch/arm/dts/{imx6ull-phytec-phycore-som-lc.dts =>
imx6ull-phytec-phycore-som-lc-nand.dts} (70%)
rename arch/arm/dts/{imx6ull-phytec-phycore-som.dts =>
imx6ull-phytec-phycore-som-nand.dts} (50%)
diff --git a/arch/arm/boards/phytec-som-imx6/board.c
b/arch/arm/boards/phytec-som-imx6/board.c
index d80851797597..cf50ad99b2fc 100644
--- a/arch/arm/boards/phytec-som-imx6/board.c
+++ b/arch/arm/boards/phytec-som-imx6/board.c
@@ -190,7 +190,7 @@ static int physom_imx6_devices_init(void)
default_environment_path = "/chosen/environment-spinor";
default_envdev = "SPI NOR flash";
- } else if (of_machine_is_compatible("phytec,imx6ul-pcl063")) {
+ } else if (of_machine_is_compatible("phytec,imx6ul-pcl063-nand")) {
barebox_set_hostname("phyCORE-i.MX6UL");
default_environment_path = "/chosen/environment-nand";
default_envdev = "NAND flash";
@@ -249,7 +249,7 @@ static int physom_imx6_devices_init(void)
|| of_machine_is_compatible("phytec,imx6dl-pcm058-nand")
|| of_machine_is_compatible("phytec,imx6dl-pcm058-emmc")) {
defaultenv_append_directory(defaultenv_physom_imx6_phycore);
- } else if (of_machine_is_compatible("phytec,imx6ul-pcl063")) {
+ } else if (of_machine_is_compatible("phytec,imx6ul-pcl063-nand")) {
defaultenv_append_directory(defaultenv_physom_imx6ul_phycore);
}
diff --git a/arch/arm/boards/phytec-som-imx6/lowlevel.c
b/arch/arm/boards/phytec-som-imx6/lowlevel.c
index 0f8d591b3a71..494087ab1479 100644
--- a/arch/arm/boards/phytec-som-imx6/lowlevel.c
+++ b/arch/arm/boards/phytec-som-imx6/lowlevel.c
@@ -118,6 +118,6 @@ PHYTEC_ENTRY(start_phytec_phycore_imx6qp_som_nand_1gib,
imx6qp_phytec_phycore_so
PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_1gib,
imx6q_phytec_phycore_som_emmc, SZ_1G, true);
PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_2gib,
imx6q_phytec_phycore_som_emmc, SZ_2G, true);
-PHYTEC_ENTRY(start_phytec_phycore_imx6ul_som_512mb, imx6ul_phytec_phycore_som,
SZ_512M, false);
-PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_lc_256mb,
imx6ull_phytec_phycore_som_lc, SZ_256M, false);
-PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_512mb,
imx6ull_phytec_phycore_som, SZ_512M, false);
+PHYTEC_ENTRY(start_phytec_phycore_imx6ul_som_nand_512mb,
imx6ul_phytec_phycore_som_nand, SZ_512M, false);
+PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_lc_nand_256mb,
imx6ull_phytec_phycore_som_lc_nand, SZ_256M, false);
+PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_nand_512mb,
imx6ull_phytec_phycore_som_nand, SZ_512M, false);
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 2a2d7a55b820..c96f040ae311 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -66,9 +66,9 @@ pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) +=
imx6q-phytec-pbaa03.dtb.o \
imx6dl-phytec-phycore-som-lc-nand.dtb.o \
imx6dl-phytec-phycore-som-emmc.dtb.o \
imx6dl-phytec-phycore-som-lc-emmc.dtb.o \
- imx6ul-phytec-phycore-som.dtb.o \
- imx6ull-phytec-phycore-som-lc.dtb.o \
- imx6ull-phytec-phycore-som.dtb.o
+ imx6ul-phytec-phycore-som-nand.dtb.o \
+ imx6ull-phytec-phycore-som-lc-nand.dtb.o \
+ imx6ull-phytec-phycore-som-nand.dtb.o
pbl-dtb-$(CONFIG_MACH_PHYTEC_PHYCORE_IMX7) += imx7d-phyboard-zeta.dtb.o
pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX8MQ) += imx8mq-phytec-phycore-som.dtb.o
pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) +=
armada-xp-openblocks-ax3-4-bb.dtb.o
diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som-nand.dts
b/arch/arm/dts/imx6ul-phytec-phycore-som-nand.dts
new fil
[PATCH v2] ARM: mach-imx: imx6: Read and print the UID of i.MX6 SOCs
Read the unified ID of the i.MX 6 SOCs and print it in the boot log.
Signed-off-by: Stefan Riedmueller
---
Changes in v2:
- Made function available for others through mach-imx/include/mach/imx6.h
---
arch/arm/mach-imx/imx6.c | 19 +++
arch/arm/mach-imx/include/mach/imx6.h | 2 ++
2 files changed, 21 insertions(+)
diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index e898be9ab545..0fdd9f082fca 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -23,6 +23,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -38,6 +39,9 @@
#define BM_CLPCR_COSC_PWRDOWN (0x1 << 11)
#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21)
+#define MX6_OCOTP_CFG0 0x410
+#define MX6_OCOTP_CFG1 0x420
+
static void imx6_init_lowlevel(void)
{
void __iomem *aips1 = (void *)MX6_AIPS1_ON_BASE_ADDR;
@@ -186,17 +190,30 @@ int imx6_cpu_revision(void)
return soc_revision;
}
+u64 imx6_uid(void)
+{
+ void __iomem *ocotpbase = IOMEM(MX6_OCOTP_BASE_ADDR);
+ u64 uid;
+
+ uid = ((u64)readl(ocotpbase + MX6_OCOTP_CFG0) << 32);
+ uid |= (u64)readl(ocotpbase + MX6_OCOTP_CFG1);
+
+ return uid;
+}
+
int imx6_init(void)
{
const char *cputypestr;
u32 mx6_silicon_revision;
void __iomem *src = IOMEM(MX6_SRC_BASE_ADDR);
+ u64 mx6_uid;
imx6_init_lowlevel();
imx6_boot_save_loc();
mx6_silicon_revision = imx6_cpu_revision();
+ mx6_uid = imx6_uid();
switch (imx6_cpu_type()) {
case IMX6_CPUTYPE_IMX6Q:
@@ -236,6 +253,8 @@ int imx6_init(void)
imx_set_silicon_revision(cputypestr, mx6_silicon_revision);
imx_set_reset_reason(src + IMX_SRC_SRSR, imx_reset_reasons);
+ pr_info("%s unique ID: %llx\n", cputypestr, mx6_uid);
+
imx6_setup_ipu_qos();
imx6ul_enet_clk_init();
diff --git a/arch/arm/mach-imx/include/mach/imx6.h
b/arch/arm/mach-imx/include/mach/imx6.h
index 5701bd480c64..f0d20833fd0f 100644
--- a/arch/arm/mach-imx/include/mach/imx6.h
+++ b/arch/arm/mach-imx/include/mach/imx6.h
@@ -124,4 +124,6 @@ static inline int __imx6_cpu_revision(void)
int imx6_cpu_revision(void);
+u64 imx6_uid(void);
+
#endif /* __MACH_IMX6_H */
--
2.7.4
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[PATCH 2/2] ARM: dts: imx6ul: phycore: Reduce eth drive strength
Reduce the drive strength for the MDC, MDIO and TX pins of fec1 to improve
signal quality and EMC. Also disable internal pull ups on the MDC and
MDIO pins.
Signed-off-by: Stefan Riedmueller
---
arch/arm/dts/imx6ul-phytec-phycore-som.dtsi | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
index 0ec7eae1eff0..c7c657bcd409 100644
--- a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
+++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
@@ -159,16 +159,16 @@
pinctrl_enet1: enet1grp {
fsl,pins = <
- MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
- MX6UL_PAD_GPIO1_IO06__ENET1_MDIO0x1b0b0
+ MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x10010
+ MX6UL_PAD_GPIO1_IO06__ENET1_MDIO0x10010
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
- MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
- MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
- MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
- MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1
0x4001b031
+ MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b010
+ MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b010
+ MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b010
+ MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1
0x4001b010
>;
};
--
2.7.4
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[PATCH 1/2] ARM: dts: imx6qdl: phycore: Set phy-reset-duration for fec
The voltage of the ethernet phy needs to be stable before de-asserting
the reset pin. Thus set the phy-reset-duration to 10 ms.
Signed-off-by: Stefan Riedmueller
---
arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
b/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
index 8fde27bd0c17..1d39368165db 100644
--- a/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
+++ b/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
@@ -110,6 +110,7 @@
phy-handle = <ðphy>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <10>; /* in msecs */
status = "disabled";
mdio {
--
2.7.4
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[PATCH 7/8] ARM: dts: imx6ul: phycore: Add support for eMMC
Add support for phyCORE-i.MX 6UL/ULL modules with eMMC instead of NAND
flash.
Signed-off-by: Stefan Riedmueller
---
arch/arm/dts/imx6ul-phytec-phycore-som.dtsi | 42 +
1 file changed, 42 insertions(+)
diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
index 1ef9d547822e..0ec7eae1eff0 100644
--- a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
+++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
@@ -25,6 +25,12 @@
device-path = &usdhc1, "partname:barebox-environment";
status = "disabled";
};
+
+ environment-sd2 {
+ compatible = "barebox,environment";
+ device-path = &usdhc2, "partname:barebox-environment";
+ status = "disabled";
+ };
};
};
@@ -125,6 +131,27 @@
};
};
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ bus-width = <8>;
+ non-removable;
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "barebox";
+ reg = <0x0 0xe>;
+ };
+
+ partition@e {
+ label = "barebox-environment";
+ reg = <0xe 0x2>;
+ };
+};
+
&iomuxc {
pinctrl-names = "default";
@@ -196,6 +223,21 @@
MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059
/* SD1 CD */
>;
};
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
+ >;
+ };
};
};
--
2.7.4
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[PATCH 8/8] ARM: dts: imx6ul: phycore: Add phyCORE-i.MX 6ULL with eMMC
Add a phyCORE-i.MX 6ULL with eMMC. It has following features:
- i.MX 6ULL Y2 792 MHz
- 512 MB RAM
- 4 GB eMMC
- 10/100 MBits Ethernet
- USB OTG
- USB Host
Signed-off-by: Stefan Riedmueller
---
arch/arm/boards/phytec-som-imx6/lowlevel.c | 1 +
arch/arm/dts/Makefile| 3 +-
arch/arm/dts/imx6ull-phytec-phycore-som-emmc.dts | 43
images/Makefile.imx | 5 +++
4 files changed, 51 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/imx6ull-phytec-phycore-som-emmc.dts
diff --git a/arch/arm/boards/phytec-som-imx6/lowlevel.c
b/arch/arm/boards/phytec-som-imx6/lowlevel.c
index 494087ab1479..07bb0ed1b569 100644
--- a/arch/arm/boards/phytec-som-imx6/lowlevel.c
+++ b/arch/arm/boards/phytec-som-imx6/lowlevel.c
@@ -121,3 +121,4 @@ PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_2gib,
imx6q_phytec_phycore_som_
PHYTEC_ENTRY(start_phytec_phycore_imx6ul_som_nand_512mb,
imx6ul_phytec_phycore_som_nand, SZ_512M, false);
PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_lc_nand_256mb,
imx6ull_phytec_phycore_som_lc_nand, SZ_256M, false);
PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_nand_512mb,
imx6ull_phytec_phycore_som_nand, SZ_512M, false);
+PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_emmc_512mb,
imx6ull_phytec_phycore_som_emmc, SZ_512M, false);
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index c96f040ae311..87ddc57b899c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -68,7 +68,8 @@ pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) +=
imx6q-phytec-pbaa03.dtb.o \
imx6dl-phytec-phycore-som-lc-emmc.dtb.o \
imx6ul-phytec-phycore-som-nand.dtb.o \
imx6ull-phytec-phycore-som-lc-nand.dtb.o \
- imx6ull-phytec-phycore-som-nand.dtb.o
+ imx6ull-phytec-phycore-som-nand.dtb.o \
+ imx6ull-phytec-phycore-som-emmc.dtb.o
pbl-dtb-$(CONFIG_MACH_PHYTEC_PHYCORE_IMX7) += imx7d-phyboard-zeta.dtb.o
pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX8MQ) += imx8mq-phytec-phycore-som.dtb.o
pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) +=
armada-xp-openblocks-ax3-4-bb.dtb.o
diff --git a/arch/arm/dts/imx6ull-phytec-phycore-som-emmc.dts
b/arch/arm/dts/imx6ull-phytec-phycore-som-emmc.dts
new file mode 100644
index ..aa162cc42d07
--- /dev/null
+++ b/arch/arm/dts/imx6ull-phytec-phycore-som-emmc.dts
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright (C) 2019 PHYTEC Messtechnik GmbH
+ * Author: Stefan Riedmueller
+ */
+
+/dts-v1/;
+
+#include
+#include "imx6ul-phytec-phycore-som.dtsi"
+
+/ {
+ model = "PHYTEC phyCORE-i.MX6 ULL SOM with eMMC";
+ compatible = "phytec,imx6ul-pcl063-emmc", "fsl,imx6ull";
+};
+
+&fec1 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&usdhc1 {
+ status = "okay";
+};
+
+&usdhc2 {
+ status = "okay";
+};
+
+&usbotg1 {
+ status = "okay";
+};
+
+&usbotg2 {
+ status = "okay";
+};
diff --git a/images/Makefile.imx b/images/Makefile.imx
index 8aedc906dc84..a287c11c4042 100644
--- a/images/Makefile.imx
+++ b/images/Makefile.imx
@@ -519,6 +519,11 @@
CFG_start_phytec_phycore_imx6ull_som_nand_512mb.pblb.imximg = $(board)/phytec-so
FILE_barebox-phytec-phycore-imx6ull-nand-512mb.img =
start_phytec_phycore_imx6ull_som_nand_512mb.pblb.imximg
image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) +=
barebox-phytec-phycore-imx6ull-nand-512mb.img
+pblb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) +=
start_phytec_phycore_imx6ull_som_emmc_512mb
+CFG_start_phytec_phycore_imx6ull_som_emmc_512mb.pblb.imximg =
$(board)/phytec-som-imx6/flash-header-phytec-pcl063-512mb.imxcfg
+FILE_barebox-phytec-phycore-imx6ull-emmc-512mb.img =
start_phytec_phycore_imx6ull_som_emmc_512mb.pblb.imximg
+image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) +=
barebox-phytec-phycore-imx6ull-emmc-512mb.img
+
pblb-$(CONFIG_MACH_TECHNEXION_PICO_HOBBIT) += start_imx6ul_pico_hobbit_256mb
CFG_start_imx6ul_pico_hobbit_256mb.pblb.imximg =
$(board)/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-256.imxcfg
FILE_barebox-imx6ul-pico-hobbit-256mb.img =
start_imx6ul_pico_hobbit_256mb.pblb.imximg
--
2.7.4
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[PATCH 4/8] ARM: dts: imx6ul: phycore: Add state framework
From: Daniel Schultz
Add the state framework with EEPROM backend.
Signed-off-by: Stefan Riedmueller
---
arch/arm/dts/imx6ul-phytec-phycore-som.dts | 5 ++
arch/arm/dts/imx6ul-phytec-state.dtsi | 81 +
arch/arm/dts/imx6ull-phytec-phycore-som.dts | 5 ++
3 files changed, 91 insertions(+)
create mode 100644 arch/arm/dts/imx6ul-phytec-state.dtsi
diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dts
b/arch/arm/dts/imx6ul-phytec-phycore-som.dts
index 6d1876702d1b..11418ea7f038 100644
--- a/arch/arm/dts/imx6ul-phytec-phycore-som.dts
+++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dts
@@ -14,6 +14,7 @@
#include
#include "imx6ul-phytec-phycore-som.dtsi"
+#include "imx6ul-phytec-state.dtsi"
/ {
model = "Phytec phyCORE-i.MX6 Ultra Lite SOM";
@@ -32,6 +33,10 @@
status = "okay";
};
+&state {
+ status = "okay";
+};
+
&uart1 {
status = "okay";
};
diff --git a/arch/arm/dts/imx6ul-phytec-state.dtsi
b/arch/arm/dts/imx6ul-phytec-state.dtsi
new file mode 100644
index ..a21cb49f00ce
--- /dev/null
+++ b/arch/arm/dts/imx6ul-phytec-state.dtsi
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 PHYTEC Messtechnik GmbH,
+ * Author: Stefan Riedmueller
+ */
+
+/ {
+ aliases {
+ state = &state;
+ };
+
+ state: imx6ul_phytec_boot_state {
+ magic = <0x883b86a6>;
+ compatible = "barebox,state";
+ backend-type = "raw";
+ backend = <&backend_update_eeprom>;
+ backend-stridesize = <54>;
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ bootstate {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ last_chosen {
+ reg = <0x0 0x4>;
+ type = "uint32";
+ };
+ system0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ remaining_attempts {
+ reg = <0x4 0x4>;
+ type = "uint32";
+ default = <3>;
+ };
+ priority {
+ reg = <0x8 0x4>;
+ type = "uint32";
+ default = <21>;
+ };
+ ok {
+ reg = <0xc 0x4>;
+ type = "uint32";
+ default = <0>;
+ };
+ };
+ system1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ remaining_attempts {
+ reg = <0x10 0x4>;
+ type = "uint32";
+ default = <3>;
+ };
+ priority {
+ reg = <0x14 0x4>;
+ type = "uint32";
+ default = <20>;
+ };
+ ok {
+ reg = <0x18 0x4>;
+ type = "uint32";
+ default = <0>;
+ };
+ };
+ };
+ };
+};
+
+&eeprom {
+ partitions {
+ compatible = "fixed-partitions";
+ #size-cells = <1>;
+ #address-cells = <1>;
+ backend_update_eeprom: state@0 {
+ reg = <0x0 0x100>;
+ label = "update-eeprom";
+ };
+ };
+};
diff --git a/arch/arm/dts/imx6ull-phytec-phycore-som.dts
b/arch/arm/dts/imx6ull-phytec-phycore-som.dts
index 4d73010131ee..86f43a4632a7 100644
--- a/arch/arm/dts/imx6ull-phytec-phycore-som.dts
+++ b/arch/arm/dts/imx6ull-phytec-phycore-som.dts
@@ -14,6 +14,7 @@
#include
#include "imx6ul-phytec-phycore-som.dtsi"
+#include "imx6ul-phytec-state.dtsi"
/ {
model = "Phytec phyCORE-i.MX6 ULL SOM";
@@ -32,6 +33,10 @@
status = "okay";
};
+&state {
+ status = "okay";
+};
+
&uart1 {
status = "okay";
};
--
2.7.4
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[PATCH 5/8] ARM: imx6ul: phycore: Prepare for eMMC module
Prepare for the new phyCORE-i.MX 6UL/ULL eMMC module by extending the
dts filenames by their boot medium. Also add the boot medium to the
compatible to be able to perform boot medium dependent setup code.
Signed-off-by: Stefan Riedmueller
---
arch/arm/boards/phytec-som-imx6/board.c| 4 +-
arch/arm/boards/phytec-som-imx6/lowlevel.c | 6 +--
arch/arm/dts/Makefile | 6 +--
arch/arm/dts/imx6ul-phytec-phycore-som-nand.dts| 48 +++
arch/arm/dts/imx6ul-phytec-phycore-som.dts | 54 --
dts => imx6ull-phytec-phycore-som-lc-nand.dts} | 6 +--
...som.dts => imx6ull-phytec-phycore-som-nand.dts} | 14 ++
images/Makefile.imx| 28 +--
8 files changed, 77 insertions(+), 89 deletions(-)
create mode 100644 arch/arm/dts/imx6ul-phytec-phycore-som-nand.dts
delete mode 100644 arch/arm/dts/imx6ul-phytec-phycore-som.dts
rename arch/arm/dts/{imx6ull-phytec-phycore-som-lc.dts =>
imx6ull-phytec-phycore-som-lc-nand.dts} (70%)
rename arch/arm/dts/{imx6ull-phytec-phycore-som.dts =>
imx6ull-phytec-phycore-som-nand.dts} (50%)
diff --git a/arch/arm/boards/phytec-som-imx6/board.c
b/arch/arm/boards/phytec-som-imx6/board.c
index d80851797597..cf50ad99b2fc 100644
--- a/arch/arm/boards/phytec-som-imx6/board.c
+++ b/arch/arm/boards/phytec-som-imx6/board.c
@@ -190,7 +190,7 @@ static int physom_imx6_devices_init(void)
default_environment_path = "/chosen/environment-spinor";
default_envdev = "SPI NOR flash";
- } else if (of_machine_is_compatible("phytec,imx6ul-pcl063")) {
+ } else if (of_machine_is_compatible("phytec,imx6ul-pcl063-nand")) {
barebox_set_hostname("phyCORE-i.MX6UL");
default_environment_path = "/chosen/environment-nand";
default_envdev = "NAND flash";
@@ -249,7 +249,7 @@ static int physom_imx6_devices_init(void)
|| of_machine_is_compatible("phytec,imx6dl-pcm058-nand")
|| of_machine_is_compatible("phytec,imx6dl-pcm058-emmc")) {
defaultenv_append_directory(defaultenv_physom_imx6_phycore);
- } else if (of_machine_is_compatible("phytec,imx6ul-pcl063")) {
+ } else if (of_machine_is_compatible("phytec,imx6ul-pcl063-nand")) {
defaultenv_append_directory(defaultenv_physom_imx6ul_phycore);
}
diff --git a/arch/arm/boards/phytec-som-imx6/lowlevel.c
b/arch/arm/boards/phytec-som-imx6/lowlevel.c
index 0f8d591b3a71..494087ab1479 100644
--- a/arch/arm/boards/phytec-som-imx6/lowlevel.c
+++ b/arch/arm/boards/phytec-som-imx6/lowlevel.c
@@ -118,6 +118,6 @@ PHYTEC_ENTRY(start_phytec_phycore_imx6qp_som_nand_1gib,
imx6qp_phytec_phycore_so
PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_1gib,
imx6q_phytec_phycore_som_emmc, SZ_1G, true);
PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_2gib,
imx6q_phytec_phycore_som_emmc, SZ_2G, true);
-PHYTEC_ENTRY(start_phytec_phycore_imx6ul_som_512mb, imx6ul_phytec_phycore_som,
SZ_512M, false);
-PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_lc_256mb,
imx6ull_phytec_phycore_som_lc, SZ_256M, false);
-PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_512mb,
imx6ull_phytec_phycore_som, SZ_512M, false);
+PHYTEC_ENTRY(start_phytec_phycore_imx6ul_som_nand_512mb,
imx6ul_phytec_phycore_som_nand, SZ_512M, false);
+PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_lc_nand_256mb,
imx6ull_phytec_phycore_som_lc_nand, SZ_256M, false);
+PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_nand_512mb,
imx6ull_phytec_phycore_som_nand, SZ_512M, false);
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 2a2d7a55b820..c96f040ae311 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -66,9 +66,9 @@ pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) +=
imx6q-phytec-pbaa03.dtb.o \
imx6dl-phytec-phycore-som-lc-nand.dtb.o \
imx6dl-phytec-phycore-som-emmc.dtb.o \
imx6dl-phytec-phycore-som-lc-emmc.dtb.o \
- imx6ul-phytec-phycore-som.dtb.o \
- imx6ull-phytec-phycore-som-lc.dtb.o \
- imx6ull-phytec-phycore-som.dtb.o
+ imx6ul-phytec-phycore-som-nand.dtb.o \
+ imx6ull-phytec-phycore-som-lc-nand.dtb.o \
+ imx6ull-phytec-phycore-som-nand.dtb.o
pbl-dtb-$(CONFIG_MACH_PHYTEC_PHYCORE_IMX7) += imx7d-phyboard-zeta.dtb.o
pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX8MQ) += imx8mq-phytec-phycore-som.dtb.o
pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) +=
armada-xp-openblocks-ax3-4-bb.dtb.o
diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som-nand.dts
b/arch/arm/dts/imx6ul-phytec-phycore-som-nand.dts
new file mode 100644
inde
[PATCH 6/8] ARM: phytec-som-imx: imx6ul: Add eMMC support
Add initial support for phyCORE-i.MX 6UL/ULL with eMMC. Including board
code and default environment.
Signed-off-by: Stefan Riedmueller
---
arch/arm/boards/phytec-som-imx6/board.c| 18 +++---
.../defaultenv-physom-imx6ul-phycore/boot/emmc | 5 +
.../defaultenv-physom-imx6ul-phycore/boot/mmc | 5 +
.../defaultenv-physom-imx6ul-phycore/init/automount| 5 +
.../defaultenv-physom-imx6ul-phycore/init/bootsource | 17 +
5 files changed, 47 insertions(+), 3 deletions(-)
create mode 100644
arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6ul-phycore/boot/emmc
create mode 100644
arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6ul-phycore/boot/mmc
create mode 100644
arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6ul-phycore/init/bootsource
diff --git a/arch/arm/boards/phytec-som-imx6/board.c
b/arch/arm/boards/phytec-som-imx6/board.c
index cf50ad99b2fc..730115702bb0 100644
--- a/arch/arm/boards/phytec-som-imx6/board.c
+++ b/arch/arm/boards/phytec-som-imx6/board.c
@@ -190,7 +190,8 @@ static int physom_imx6_devices_init(void)
default_environment_path = "/chosen/environment-spinor";
default_envdev = "SPI NOR flash";
- } else if (of_machine_is_compatible("phytec,imx6ul-pcl063-nand")) {
+ } else if (of_machine_is_compatible("phytec,imx6ul-pcl063-nand")
+ || of_machine_is_compatible("phytec,imx6ul-pcl063-emmc")) {
barebox_set_hostname("phyCORE-i.MX6UL");
default_environment_path = "/chosen/environment-nand";
default_envdev = "NAND flash";
@@ -236,6 +237,10 @@ static int physom_imx6_devices_init(void)
imx6_bbu_internal_mmc_register_handler("mmc3",
"/dev/mmc3",
BBU_HANDLER_FLAG_DEFAULT);
+ } else if (of_machine_is_compatible("phytec,imx6ul-pcl063-emmc")) {
+ imx6_bbu_internal_mmc_register_handler("mmc1",
+ "/dev/mmc1",
+ BBU_HANDLER_FLAG_DEFAULT);
} else {
imx6_bbu_nand_register_handler("nand",
BBU_HANDLER_FLAG_DEFAULT);
}
@@ -243,13 +248,20 @@ static int physom_imx6_devices_init(void)
defaultenv_append_directory(defaultenv_physom_imx6);
/* Overwrite file /env/init/automount */
- if (of_machine_is_compatible("phytec,imx6qp-pcm058-nand")
+ if (of_machine_is_compatible("phytec,imx6q-pfla02")
+ || of_machine_is_compatible("phytec,imx6dl-pfla02")
+ || of_machine_is_compatible("phytec,imx6s-pfla02")
+ || of_machine_is_compatible("phytec,imx6q-pcaaxl3")) {
+ defaultenv_append_directory(defaultenv_physom_imx6);
+ } else if (of_machine_is_compatible("phytec,imx6qp-pcm058-nand")
|| of_machine_is_compatible("phytec,imx6q-pcm058-nand")
|| of_machine_is_compatible("phytec,imx6q-pcm058-emmc")
|| of_machine_is_compatible("phytec,imx6dl-pcm058-nand")
|| of_machine_is_compatible("phytec,imx6dl-pcm058-emmc")) {
+ defaultenv_append_directory(defaultenv_physom_imx6);
defaultenv_append_directory(defaultenv_physom_imx6_phycore);
- } else if (of_machine_is_compatible("phytec,imx6ul-pcl063-nand")) {
+ } else if (of_machine_is_compatible("phytec,imx6ul-pcl063-nand")
+ || of_machine_is_compatible("phytec,imx6ul-pcl063-emmc")) {
defaultenv_append_directory(defaultenv_physom_imx6ul_phycore);
}
diff --git
a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6ul-phycore/boot/emmc
b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6ul-phycore/boot/emmc
new file mode 100644
index ..15cba6f5ac1b
--- /dev/null
+++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6ul-phycore/boot/emmc
@@ -0,0 +1,5 @@
+#!/bin/sh
+
+global.bootm.image="/mnt/emmc/zImage"
+global.bootm.oftree="/mnt/emmc/oftree"
+global.linux.bootargs.dyn.root="root=/dev/mmcblk1p2
rootflags='discard,data=journal'"
diff --git
a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6ul-phycore/boot/mmc
b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6ul-phycore/boot/mmc
new file mode 100644
index ..8de2efa997d9
--- /dev/null
+++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6ul-phycore/boot/mmc
@@ -0,0 +1,5 @@
+#!/bin/sh
+
+global.bootm.image="/mnt/mmc/zImage"
+global.bootm.oftree="/mnt/mmc/oftree"
+global.linux.bootargs.
[PATCH 1/8] ARM: phytec-som-imx6: Add low cost variant for imx6dl phycore
The phyCORE-i.MX 6Solo/DualLight is available with low-cost and
full-featured phyBOARD-Mira. One crucial difference is the supported
max. ethernet speed. On the full-featured Mira it is 1000 MBit/s but on
the low-cost Mira it is only 100 MBit/s. To cover this difference two
different images are necessary for low-cost and full-featured. Thus a
low-cost variant is added for the phyCORE-i.MX 6Solo with NAND and the
phyCORE-i.MX 6 DualLight with eMMC.
Signed-off-by: Stefan Riedmueller
---
arch/arm/boards/phytec-som-imx6/lowlevel.c | 2 +
arch/arm/dts/Makefile | 2 +
arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts| 2 +-
arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts | 65 ++
arch/arm/dts/imx6dl-phytec-phycore-som-lc-nand.dts | 57 +++
arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts| 2 +-
images/Makefile.imx| 10
7 files changed, 138 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts
create mode 100644 arch/arm/dts/imx6dl-phytec-phycore-som-lc-nand.dts
diff --git a/arch/arm/boards/phytec-som-imx6/lowlevel.c
b/arch/arm/boards/phytec-som-imx6/lowlevel.c
index 915534ea9455..0f8d591b3a71 100644
--- a/arch/arm/boards/phytec-som-imx6/lowlevel.c
+++ b/arch/arm/boards/phytec-som-imx6/lowlevel.c
@@ -109,8 +109,10 @@ PHYTEC_ENTRY(start_phytec_phyboard_subra_512mb_1bank,
imx6dl_phytec_phyboard_sub
PHYTEC_ENTRY(start_phytec_phyboard_subra_1gib_1bank,
imx6q_phytec_phyboard_subra, SZ_1G, false);
PHYTEC_ENTRY(start_phytec_phycore_imx6dl_som_nand_256mb,
imx6dl_phytec_phycore_som_nand, SZ_256M, true);
+PHYTEC_ENTRY(start_phytec_phycore_imx6dl_som_lc_nand_256mb,
imx6dl_phytec_phycore_som_lc_nand, SZ_256M, true);
PHYTEC_ENTRY(start_phytec_phycore_imx6dl_som_nand_1gib,
imx6dl_phytec_phycore_som_nand, SZ_1G, true);
PHYTEC_ENTRY(start_phytec_phycore_imx6dl_som_emmc_1gib,
imx6dl_phytec_phycore_som_emmc, SZ_1G, true);
+PHYTEC_ENTRY(start_phytec_phycore_imx6dl_som_lc_emmc_1gib,
imx6dl_phytec_phycore_som_lc_emmc, SZ_1G, true);
PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_nand_1gib,
imx6q_phytec_phycore_som_nand, SZ_1G, true);
PHYTEC_ENTRY(start_phytec_phycore_imx6qp_som_nand_1gib,
imx6qp_phytec_phycore_som_nand, SZ_1G, true);
PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_1gib,
imx6q_phytec_phycore_som_emmc, SZ_1G, true);
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 561653930b20..2a2d7a55b820 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -63,7 +63,9 @@ pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) +=
imx6q-phytec-pbaa03.dtb.o \
imx6q-phytec-phycore-som-emmc.dtb.o \
imx6qp-phytec-phycore-som-nand.dtb.o \
imx6dl-phytec-phycore-som-nand.dtb.o \
+ imx6dl-phytec-phycore-som-lc-nand.dtb.o \
imx6dl-phytec-phycore-som-emmc.dtb.o \
+ imx6dl-phytec-phycore-som-lc-emmc.dtb.o \
imx6ul-phytec-phycore-som.dtb.o \
imx6ull-phytec-phycore-som-lc.dtb.o \
imx6ull-phytec-phycore-som.dtb.o
diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts
b/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts
index e602b77e9940..a04e37f80363 100644
--- a/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts
+++ b/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts
@@ -30,7 +30,7 @@
};
ðphy {
- max-speed = <100>;
+ max-speed = <1000>;
};
&fec {
diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts
b/arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts
new file mode 100644
index ..5d9727ec5b80
--- /dev/null
+++ b/arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright (C) 2019 PHYTEC Messtechnik GmbH,
+ * Author: Stefan Riedmueller
+ */
+
+/dts-v1/;
+
+#include
+#include "imx6dl.dtsi"
+#include "imx6qdl-phytec-phycore-som.dtsi"
+
+/ {
+ model = "PHYTEC phyCORE-i.MX6 DualLite/SOLO with eMMC low-cost";
+ compatible = "phytec,imx6dl-pcm058-emmc", "fsl,imx6dl";
+};
+
+&ecspi1 {
+ status = "okay";
+};
+
+&eeprom {
+ status = "okay";
+};
+
+ðphy {
+ max-speed = <100>;
+};
+
+&fec {
+ status = "okay";
+};
+
+&flash {
+ status = "okay";
+};
+
+&usbh1 {
+ status = "okay";
+};
+
+&usbotg {
+ status = "okay";
+};
+
+&usdhc1 {
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "barebox";
+ reg = <0x0 0xe>
[PATCH 3/8] ARM: dts: imx6ul: phycore: Add eeprom label
Add a label for the EEPROM to be able to address it for the state
framework.
Signed-off-by: Stefan Riedmueller
---
arch/arm/dts/imx6ul-phytec-phycore-som.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
index 964f91950d93..1ef9d547822e 100644
--- a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
+++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
@@ -79,7 +79,7 @@
clock-frequency = <10>;
status = "disabled";
- eeprom@52 {
+ eeprom: eeprom@52 {
compatible = "cat,24c32";
reg = <0x52>;
};
--
2.7.4
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[PATCH 2/8] ARM: dts: imx6qdl: phycore: Add state framework
From: Daniel Schultz
Add the state framework with EEPROM backend.
Signed-off-by: Daniel Schultz
Signed-off-by: Stefan Riedmueller
---
arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts| 1 +
arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts | 1 +
arch/arm/dts/imx6dl-phytec-phycore-som-lc-nand.dts | 1 +
arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts| 1 +
arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts | 1 +
arch/arm/dts/imx6q-phytec-phycore-som-nand.dts | 1 +
arch/arm/dts/imx6qdl-phytec-state.dtsi | 81 ++
7 files changed, 87 insertions(+)
create mode 100644 arch/arm/dts/imx6qdl-phytec-state.dtsi
diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts
b/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts
index a04e37f80363..21cbb5f944c9 100644
--- a/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts
+++ b/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts
@@ -15,6 +15,7 @@
#include
#include "imx6dl.dtsi"
#include "imx6qdl-phytec-phycore-som.dtsi"
+#include "imx6qdl-phytec-state.dtsi"
/ {
model = "Phytec phyCORE-i.MX6 DualLite/SOLO with eMMC";
diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts
b/arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts
index 5d9727ec5b80..b8efb95ee08a 100644
--- a/arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts
+++ b/arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts
@@ -9,6 +9,7 @@
#include
#include "imx6dl.dtsi"
#include "imx6qdl-phytec-phycore-som.dtsi"
+#include "imx6qdl-phytec-state.dtsi"
/ {
model = "PHYTEC phyCORE-i.MX6 DualLite/SOLO with eMMC low-cost";
diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-lc-nand.dts
b/arch/arm/dts/imx6dl-phytec-phycore-som-lc-nand.dts
index e119e4c0d4fc..4d38d1698a48 100644
--- a/arch/arm/dts/imx6dl-phytec-phycore-som-lc-nand.dts
+++ b/arch/arm/dts/imx6dl-phytec-phycore-som-lc-nand.dts
@@ -9,6 +9,7 @@
#include
#include "imx6dl.dtsi"
#include "imx6qdl-phytec-phycore-som.dtsi"
+#include "imx6qdl-phytec-state.dtsi"
/ {
model = "PHYTEC phyCORE-i.MX6 Duallite/SOLO with NAND low-cost";
diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts
b/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts
index 287d876e41ed..3ad3723d2893 100644
--- a/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts
+++ b/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts
@@ -14,6 +14,7 @@
#include
#include "imx6dl.dtsi"
#include "imx6qdl-phytec-phycore-som.dtsi"
+#include "imx6qdl-phytec-state.dtsi"
/ {
model = "Phytec phyCORE-i.MX6 Duallite/SOLO with NAND";
diff --git a/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts
b/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts
index 94a70389f084..7a86d5b94daf 100644
--- a/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts
+++ b/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts
@@ -14,6 +14,7 @@
#include
#include "imx6q.dtsi"
#include "imx6qdl-phytec-phycore-som.dtsi"
+#include "imx6qdl-phytec-state.dtsi"
/ {
model = "Phytec phyCORE-i.MX6 Quad with eMMC";
diff --git a/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts
b/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts
index 6d82ec34d6e5..96d1de224c9e 100644
--- a/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts
+++ b/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts
@@ -14,6 +14,7 @@
#include
#include "imx6q.dtsi"
#include "imx6qdl-phytec-phycore-som.dtsi"
+#include "imx6qdl-phytec-state.dtsi"
/ {
model = "Phytec phyCORE-i.MX6 Quad with NAND";
diff --git a/arch/arm/dts/imx6qdl-phytec-state.dtsi
b/arch/arm/dts/imx6qdl-phytec-state.dtsi
new file mode 100644
index ..76aa15f3e2f7
--- /dev/null
+++ b/arch/arm/dts/imx6qdl-phytec-state.dtsi
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright (C) 2019 PHYTEC Messtechnik GmbH,
+ * Author: Daniel Schultz
+ */
+
+/ {
+ aliases {
+ state = &state;
+ };
+
+ state: imx6qdl_phytec_boot_state {
+ magic = <0x883b86a6>;
+ compatible = "barebox,state";
+ backend-type = "raw";
+ backend = <&backend_update_eeprom>;
+ backend-stridesize = <54>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ bootstate {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ last_chosen {
+ reg = <0x0 0x4>;
+ type = "uint32";
+ };
+ system0 {
+ #address-cells = <1>;
+
[PATCH] ARM: mach-imx: imx6: Read and print the UID of i.MX6 SOCs
Read the unified ID of the i.MX 6 SOCs and print it in the boot log.
Signed-off-by: Stefan Riedmueller
---
arch/arm/mach-imx/imx6.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index e898be9ab545..66f3d22a68a7 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -23,6 +23,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -38,6 +39,9 @@
#define BM_CLPCR_COSC_PWRDOWN (0x1 << 11)
#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21)
+#define MX6_OCOTP_CFG0 0x410
+#define MX6_OCOTP_CFG1 0x420
+
static void imx6_init_lowlevel(void)
{
void __iomem *aips1 = (void *)MX6_AIPS1_ON_BASE_ADDR;
@@ -186,17 +190,30 @@ int imx6_cpu_revision(void)
return soc_revision;
}
+static u64 imx6_uid(void)
+{
+ void __iomem *ocotpbase = IOMEM(MX6_OCOTP_BASE_ADDR);
+ u64 uid;
+
+ uid = ((u64)readl(ocotpbase + MX6_OCOTP_CFG0) << 32);
+ uid |= (u64)readl(ocotpbase + MX6_OCOTP_CFG1);
+
+ return uid;
+}
+
int imx6_init(void)
{
const char *cputypestr;
u32 mx6_silicon_revision;
void __iomem *src = IOMEM(MX6_SRC_BASE_ADDR);
+ u64 mx6_uid;
imx6_init_lowlevel();
imx6_boot_save_loc();
mx6_silicon_revision = imx6_cpu_revision();
+ mx6_uid = imx6_uid();
switch (imx6_cpu_type()) {
case IMX6_CPUTYPE_IMX6Q:
@@ -236,6 +253,8 @@ int imx6_init(void)
imx_set_silicon_revision(cputypestr, mx6_silicon_revision);
imx_set_reset_reason(src + IMX_SRC_SRSR, imx_reset_reasons);
+ pr_info("%s unique ID: %llx\n", cputypestr, mx6_uid);
+
imx6_setup_ipu_qos();
imx6ul_enet_clk_init();
--
2.7.4
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[PATCH] nvmem: ocotp: Fix writing of second mac address fuses on imx6ul
Commit 19a32c0f6bf0 ("nvmem: ocotp: Add support for second mac address
fuses on imx6ul") added support for correctly reading the second MAC
address from fuses of the i.MX 6UL/ULL but not for writing. So also fit
writing of the second MAC address fuses to the correct method.
Signed-off-by: Stefan Riedmueller
---
drivers/nvmem/ocotp.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/nvmem/ocotp.c b/drivers/nvmem/ocotp.c
index e0cf35f0b73c..d904bd08f0c5 100644
--- a/drivers/nvmem/ocotp.c
+++ b/drivers/nvmem/ocotp.c
@@ -446,9 +446,18 @@ static int imx_ocotp_set_mac(struct param_d *param, void
*priv)
{
char buf[MAC_BYTES];
struct ocotp_priv_ethaddr *ethaddr = priv;
+ int ret;
- ethaddr->data->format_mac(buf, ethaddr->value,
- OCOTP_MAC_TO_HW);
+ ret = regmap_bulk_read(ethaddr->map, ethaddr->offset, buf, MAC_BYTES);
+ if (ret < 0)
+ return ret;
+
+ if (ethaddr->offset != IMX6UL_MAC_OFFSET_1)
+ ethaddr->data->format_mac(buf, ethaddr->value,
+ OCOTP_MAC_TO_HW);
+ else
+ ethaddr->data->format_mac(buf + 2, ethaddr->value,
+ OCOTP_MAC_TO_HW);
return regmap_bulk_write(ethaddr->map, ethaddr->offset,
buf, MAC_BYTES);
--
2.7.4
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[PATCH 3/3] ARM: phytec-som-imx6: Add full featured phyCORE-i.MX 6ULL
The phyCORE-i.MX 6ULL now comes in a full featured (Y2 variant) and a
low cost (Y0 variant) version. The main difference for the barebox is
the missing second USB OTG port on the Y0 variant and the RAM configuration.
So to account for these differences the existing low cost version is
renamed and the full featured version added.
The results are following phyCORE-i.MX 6ULL modules:
phyCORE-i.MX 6ULL low cost:
- i.MX 6ULL Y0
- 256 MB RAM
- NAND
- Ethernet 10/100 MBits
- USB OTG
phyCORE-i.MX 6ULL full featured:
- i.MX 6ULL Y2
- 512 MB RAM
- NAND
- Ethernet 10/100 MBits
- USB OTG
- USB Host
Signed-off-by: Stefan Riedmueller
---
arch/arm/boards/phytec-som-imx6/lowlevel.c | 3 +-
arch/arm/dts/Makefile | 1 +
arch/arm/dts/imx6ull-phytec-phycore-som-lc.dts | 39 ++
arch/arm/dts/imx6ull-phytec-phycore-som.dts| 4 +++
images/Makefile.imx| 13 ++---
5 files changed, 55 insertions(+), 5 deletions(-)
create mode 100644 arch/arm/dts/imx6ull-phytec-phycore-som-lc.dts
diff --git a/arch/arm/boards/phytec-som-imx6/lowlevel.c
b/arch/arm/boards/phytec-som-imx6/lowlevel.c
index 05f918f6c9c0..9d81c278ca43 100644
--- a/arch/arm/boards/phytec-som-imx6/lowlevel.c
+++ b/arch/arm/boards/phytec-som-imx6/lowlevel.c
@@ -116,4 +116,5 @@ PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_1gib,
imx6q_phytec_phycore_som_
PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_2gib,
imx6q_phytec_phycore_som_emmc, SZ_2G, true);
PHYTEC_ENTRY(start_phytec_phycore_imx6ul_som_512mb, imx6ul_phytec_phycore_som,
SZ_512M, false);
-PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_256mb,
imx6ull_phytec_phycore_som, SZ_256M, false);
+PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_lc_256mb,
imx6ull_phytec_phycore_som_lc, SZ_256M, false);
+PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_512mb,
imx6ull_phytec_phycore_som, SZ_512M, false);
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 503d9b18f9c1..c08b35a10132 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -63,6 +63,7 @@ pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) +=
imx6q-phytec-pbaa03.dtb.o \
imx6dl-phytec-phycore-som-nand.dtb.o \
imx6dl-phytec-phycore-som-emmc.dtb.o \
imx6ul-phytec-phycore-som.dtb.o \
+ imx6ull-phytec-phycore-som-lc.dtb.o \
imx6ull-phytec-phycore-som.dtb.o
pbl-dtb-$(CONFIG_MACH_PHYTEC_PHYCORE_IMX7) += imx7d-phyboard-zeta.dtb.o
pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) +=
armada-xp-openblocks-ax3-4-bb.dtb.o
diff --git a/arch/arm/dts/imx6ull-phytec-phycore-som-lc.dts
b/arch/arm/dts/imx6ull-phytec-phycore-som-lc.dts
new file mode 100644
index ..94a783075651
--- /dev/null
+++ b/arch/arm/dts/imx6ull-phytec-phycore-som-lc.dts
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright (C) 2018 PHYTEC Messtechnik GmbH
+ * Author: Stefan Riedmueller
+ */
+
+/dts-v1/;
+
+#include
+#include "imx6ul-phytec-phycore-som.dtsi"
+
+/ {
+ model = "Phytec phyCORE-i.MX6 ULL SOM low-cost";
+ compatible = "phytec,imx6ul-pcl063", "fsl,imx6ull";
+};
+
+&fec1 {
+ status = "okay";
+};
+
+&gpmi {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&usdhc1 {
+ status = "okay";
+};
+
+&usbotg1 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/imx6ull-phytec-phycore-som.dts
b/arch/arm/dts/imx6ull-phytec-phycore-som.dts
index ce631460caea..4d73010131ee 100644
--- a/arch/arm/dts/imx6ull-phytec-phycore-som.dts
+++ b/arch/arm/dts/imx6ull-phytec-phycore-som.dts
@@ -43,3 +43,7 @@
&usbotg1 {
status = "okay";
};
+
+&usbotg2 {
+ status = "okay";
+};
diff --git a/images/Makefile.imx b/images/Makefile.imx
index 9b5cd577d285..507e20a7c6ce 100644
--- a/images/Makefile.imx
+++ b/images/Makefile.imx
@@ -471,10 +471,15 @@ CFG_start_phytec_phycore_imx6ul_som_512mb.pblx.imximg =
$(board)/phytec-som-imx6
FILE_barebox-phytec-phycore-imx6ul-512mb.img =
start_phytec_phycore_imx6ul_som_512mb.pblx.imximg
image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-phycore-imx6ul-512mb.img
-pblx-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += start_phytec_phycore_imx6ull_som_256mb
-CFG_start_phytec_phycore_imx6ull_som_256mb.pblx.imximg =
$(board)/phytec-som-imx6/flash-header-phytec-pcl063-256mb.imxcfg
-FILE_barebox-phytec-phycore-imx6ull-256mb.img =
start_phytec_phycore_imx6ull_som_256mb.pblx.imximg
-image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) +=
barebox-phytec-phycore-imx6ull-256mb.img
+pblx-$(CONFIG_MACH_PHYTEC_SOM_IMX6) +=
start_phytec_phycore_imx6ull_som_lc_256mb
+CF
[PATCH 2/3] ARM: dts: phyCORE-i.MX 6UL/ULL: Enable USB OTG on port 1
From: Fabian Godehardt
Enable USB OTG support on USB OTG port 1 of the phyCORE-i.MX 6UL/ULL.
Signed-off-by: Fabian Godehardt
Signed-off-by: Stefan Riedmueller
---
arch/arm/dts/imx6ul-phytec-phycore-som.dts | 4
arch/arm/dts/imx6ul-phytec-phycore-som.dtsi | 14 ++
arch/arm/dts/imx6ull-phytec-phycore-som.dts | 4
3 files changed, 22 insertions(+)
diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dts
b/arch/arm/dts/imx6ul-phytec-phycore-som.dts
index 509424347082..6d1876702d1b 100644
--- a/arch/arm/dts/imx6ul-phytec-phycore-som.dts
+++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dts
@@ -40,6 +40,10 @@
status = "okay";
};
+&usbotg1 {
+ status = "okay";
+};
+
&usbotg2 {
status = "okay";
};
diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
index 05bf18d6f1b2..d829fdd6fb29 100644
--- a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
+++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
@@ -89,6 +89,14 @@
status = "disabled";
};
+&usbotg1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_otg1>;
+ dr_mode = "otg";
+ disable-over-current;
+ status = "disabled";
+};
+
&usbotg2 {
dr_mode = "host";
disable-over-current;
@@ -169,6 +177,12 @@
>;
};
+ pinctrl_usb_otg1: usbotg1grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID0x17059
+ >;
+ };
+
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
diff --git a/arch/arm/dts/imx6ull-phytec-phycore-som.dts
b/arch/arm/dts/imx6ull-phytec-phycore-som.dts
index de04132a02e7..ce631460caea 100644
--- a/arch/arm/dts/imx6ull-phytec-phycore-som.dts
+++ b/arch/arm/dts/imx6ull-phytec-phycore-som.dts
@@ -39,3 +39,7 @@
&usdhc1 {
status = "okay";
};
+
+&usbotg1 {
+ status = "okay";
+};
--
2.7.4
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[PATCH 1/3] ARM: dts: phyCORE-i.MX 6UL: Enable USB host port
The phyBOARD-Segin baseboard of the phyCORE-i.MX 6UL features a USB
type A connector on the second USB OTG port of the i.MX 6UL. So enable this
port as a host port.
Signed-off-by: Stefan Riedmueller
---
arch/arm/dts/imx6ul-phytec-phycore-som.dts | 4
arch/arm/dts/imx6ul-phytec-phycore-som.dtsi | 6 ++
2 files changed, 10 insertions(+)
diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dts
b/arch/arm/dts/imx6ul-phytec-phycore-som.dts
index 73f7dbe9a6b3..509424347082 100644
--- a/arch/arm/dts/imx6ul-phytec-phycore-som.dts
+++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dts
@@ -39,3 +39,7 @@
&usdhc1 {
status = "okay";
};
+
+&usbotg2 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
index 2504c9729dd1..05bf18d6f1b2 100644
--- a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
+++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
@@ -89,6 +89,12 @@
status = "disabled";
};
+&usbotg2 {
+ dr_mode = "host";
+ disable-over-current;
+ status = "disabled";
+};
+
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
--
2.7.4
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[PATCH] phytec-som-imx6: ksz8081_phy_fixup: Don't override B-CAST_OFF strap-in
From: Jan Remmet
As PHY address 0 is not used on PHYTEC i.MX 6 and i.MX 6UL SOMs we do
not have to override the B-CAST_OFF strap-in which disables broadcast
on PHY address 0.
Also add some comments about the magic values.
Signed-off-by: Jan Remmet
Signed-off-by: Stefan Riedmueller
---
arch/arm/boards/phytec-som-imx6/board.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boards/phytec-som-imx6/board.c
b/arch/arm/boards/phytec-som-imx6/board.c
index 4079bc9de1b3..38a2ef641e47 100644
--- a/arch/arm/boards/phytec-som-imx6/board.c
+++ b/arch/arm/boards/phytec-som-imx6/board.c
@@ -99,8 +99,17 @@ static unsigned int get_module_rev(void)
static int ksz8081_phy_fixup(struct phy_device *phydev)
{
+ /*
+* 0x8100 default
+* 0x0080 RMII 50 MHz clock mode
+* 0x0010 LED Mode 1
+*/
phy_write(phydev, 0x1f, 0x8190);
- phy_write(phydev, 0x16, 0x202);
+ /*
+* 0x0002 Override strap-in for RMII mode
+* This should be default but after reset we occasionally read 0x0001
+*/
+ phy_write(phydev, 0x16, 0x2);
return 0;
}
--
2.7.4
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[PATCH] nvmem: ocotp: Add support for second mac address fuses on imx6ul
From: Christian Hemp
The i.MX 6UL/ULL has fuses for two MAC addresses. Both MAC addresses
share the fuse address 0x23.
-
0x22| MAC0 | MAC0 | MAC0 | MAC0 |
-
0x23| MAC0 | MAC0 | MAC1 | MAC1 |
-
0x24| MAC1 | MAC1 | MAC1 | MAC1 |
-
So to read the second MAC address the first two bytes of 0x23 need to be
skipped.
Signed-off-by: Christian Hemp
Signed-off-by: Stefan Riedmueller
---
drivers/nvmem/ocotp.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/nvmem/ocotp.c b/drivers/nvmem/ocotp.c
index e689559ee362..e0cf35f0b73c 100644
--- a/drivers/nvmem/ocotp.c
+++ b/drivers/nvmem/ocotp.c
@@ -70,6 +70,7 @@
#define IMX6_OTP_DATA_ERROR_VAL0xBADABADA
#define DEF_RELAX 20
#define MAC_OFFSET_0 (0x22 * 4)
+#define IMX6UL_MAC_OFFSET_1(0x23 * 4)
#define MAC_OFFSET_1 (0x24 * 4)
#define MAX_MAC_OFFSETS2
#define MAC_BYTES 8
@@ -421,10 +422,14 @@ static int imx_ocotp_read_mac(const struct imx_ocotp_data
*data,
int ret;
ret = regmap_bulk_read(map, offset, buf, MAC_BYTES);
+
if (ret < 0)
return ret;
- data->format_mac(mac, buf, OCOTP_HW_TO_MAC);
+ if (offset != IMX6UL_MAC_OFFSET_1)
+ data->format_mac(mac, buf, OCOTP_HW_TO_MAC);
+ else
+ data->format_mac(mac, buf + 2, OCOTP_HW_TO_MAC);
return 0;
}
@@ -639,6 +644,14 @@ static struct imx_ocotp_data imx6sl_ocotp_data = {
.format_mac = imx_ocotp_format_mac,
};
+static struct imx_ocotp_data imx6ul_ocotp_data = {
+ .num_regs = 512,
+ .addr_to_offset = imx6q_addr_to_offset,
+ .mac_offsets_num = 2,
+ .mac_offsets = { MAC_OFFSET_0, IMX6UL_MAC_OFFSET_1 },
+ .format_mac = imx_ocotp_format_mac,
+};
+
static struct imx_ocotp_data vf610_ocotp_data = {
.num_regs = 512,
.addr_to_offset = vf610_addr_to_offset,
@@ -667,7 +680,7 @@ static __maybe_unused struct of_device_id
imx_ocotp_dt_ids[] = {
.data = &imx6sl_ocotp_data,
}, {
.compatible = "fsl,imx6ul-ocotp",
- .data = &imx6q_ocotp_data,
+ .data = &imx6ul_ocotp_data,
}, {
.compatible = "fsl,imx8mq-ocotp",
.data = &imx8mq_ocotp_data,
--
2.7.4
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[PATCH] commands: of_display_timings: Add simple-panel support
Display timings can now be set with simple-panel method which selects
the required timings by the compatible of the simple panel devicetree
node.
This patch adds an option to set simple panel timings with the
of_display_timings command by setting the compatible of the display node.
The options -P and -c were implemented. The -P option requires the display
node path as argument and the -c option requires the compatible to set.
This has one downside. The available simple panel timings cannot be
listed since the timings are defined in the kernel. Account for this in the
help text.
Signed-off-by: Stefan Riedmueller
---
commands/of_display_timings.c | 65 ---
1 file changed, 61 insertions(+), 4 deletions(-)
diff --git a/commands/of_display_timings.c b/commands/of_display_timings.c
index ccf2db0..ca8275f 100644
--- a/commands/of_display_timings.c
+++ b/commands/of_display_timings.c
@@ -28,6 +28,39 @@
#include
#include
+struct panel_info {
+ char *displaypath;
+ char *compatible;
+};
+
+static int of_panel_timing(struct device_node *root, void *context)
+{
+ int ret = 0;
+ struct panel_info *panel = (struct panel_info*)context;
+ struct device_node *display;
+
+ display = of_find_node_by_path_from(root, panel->displaypath);
+ if (!display) {
+ pr_err("Path to display node is not vaild.\n");
+ ret = -EINVAL;
+ goto out;
+ }
+
+ ret = of_set_property(display, "compatible",
+ panel->compatible,
+ strlen(panel->compatible) + 1, 1);
+
+ if (ret < 0) {
+ pr_err("Could not update compatible property\n");
+ goto out;
+ }
+
+ ret = of_device_enable(display);
+
+out:
+ return ret;
+}
+
static int of_display_timing(struct device_node *root, void *timingpath)
{
int ret = 0;
@@ -55,10 +88,12 @@ static int do_of_display_timings(int argc, char *argv[])
struct device_node *root = NULL;
struct device_node *display = NULL;
struct device_node *timings = NULL;
+ struct panel_info *panel = NULL;
char *timingpath = NULL;
char *dtbfile = NULL;
+ char *compatible = NULL;
- while ((opt = getopt(argc, argv, "sS:lf:")) > 0) {
+ while ((opt = getopt(argc, argv, "sS:lf:c:P:")) > 0) {
switch (opt) {
case 'l':
list = 1;
@@ -69,10 +104,18 @@ static int do_of_display_timings(int argc, char *argv[])
case 's':
selected = 1;
break;
+ case 'c':
+ compatible = optarg;
+ break;
case 'S':
timingpath = xzalloc(strlen(optarg) + 1);
strcpy(timingpath, optarg);
break;
+ case 'P':
+ panel = xzalloc(sizeof(struct panel_info));
+ panel->displaypath = xzalloc(strlen(optarg) + 1);
+ strcpy(panel->displaypath, optarg);
+ break;
default:
return COMMAND_ERROR_USAGE;
}
@@ -140,6 +183,18 @@ static int do_of_display_timings(int argc, char *argv[])
printf("No selected display-timings found.\n");
}
+ if (panel) {
+ if (!compatible) {
+ pr_err("No compatible argument. -P option requires
compatible with -c option\n");
+ return -EINVAL;
+ } else {
+ panel->compatible = xzalloc(strlen(compatible) + 1);
+ strcpy(panel->compatible, compatible);
+ }
+
+ of_register_fixup(of_panel_timing, panel);
+ }
+
if (timingpath)
of_register_fixup(of_display_timing, timingpath);
@@ -148,16 +203,18 @@ static int do_of_display_timings(int argc, char *argv[])
BAREBOX_CMD_HELP_START(of_display_timings)
BAREBOX_CMD_HELP_TEXT("Options:")
-BAREBOX_CMD_HELP_OPT("-l", "list path of all available display-timings\n")
-BAREBOX_CMD_HELP_OPT("-s", "list path of all selected display-timings\n")
+BAREBOX_CMD_HELP_OPT("-l", "list path of all available
display-timings\n\t\tNOTE: simple-panel timings cannot be listed\n")
+BAREBOX_CMD_HELP_OPT("-s", "list path of all selected
display-timings\n\t\tNOTE: simple-panel timings cannot be listed\n")
+BAREBOX_CMD_HELP_OPT("-c", "display compatible to enable with -P option. Has
no effect on -S option\n")
BAREBOX_CMD_HELP_OPT("-S path&qu
[PATCH 2/3] ARM: i.MX6ul: Add Clock support for i.MX6ull
>From linux-4.10 clock support, only skipped some unnecessary clocks
Signed-off-by: Stefan Riedmueller
---
drivers/clk/imx/clk-imx6ul.c | 73 +---
1 file changed, 62 insertions(+), 11 deletions(-)
diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
index f28660d..b0a6bb0 100644
--- a/drivers/clk/imx/clk-imx6ul.c
+++ b/drivers/clk/imx/clk-imx6ul.c
@@ -66,10 +66,24 @@ static const char *perclk_sels[] = { "ipg", "osc", };
static const char *lcdif_sels[] = { "lcdif_podf", "ipp_di0", "ipp_di1",
"ldb_di0", "ldb_di1", };
static const char *csi_sels[] = { "osc", "pll2_pfd2_396m", "pll3_120m",
"pll3_pfd1_540m", };
static const char *sim_sels[] = { "sim_podf", "ipp_di0", "ipp_di1", "ldb_di0",
"ldb_di1", };
+/* epdc_pre_sels, epdc_sels, esai_sels only exists on i.MX6ULL */
+static const char *epdc_pre_sels[] = { "pll2_bus", "pll3_usb_otg",
"pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd2_508m", };
+static const char *esai_sels[] = { "pll4_audio_div", "pll3_pfd2_508m",
"pll5_video_div", "pll3_usb_otg", };
+static const char *epdc_sels[] = { "epdc_podf", "ipp_di0", "ipp_di1",
"ldb_di0", "ldb_di1", };
static struct clk *clks[IMX6UL_CLK_END];
static struct clk_onecell_data clk_data;
+static inline int clk_on_imx6ul(void)
+{
+ return of_machine_is_compatible("fsl,imx6ul");
+}
+
+static inline int clk_on_imx6ull(void)
+{
+ return of_machine_is_compatible("fsl,imx6ull");
+}
+
static int const clks_init_on[] __initconst = {
IMX6UL_CLK_AIPSTZ1, IMX6UL_CLK_AIPSTZ2, IMX6UL_CLK_AIPSTZ3,
IMX6UL_CLK_AXI, IMX6UL_CLK_ARM, IMX6UL_CLK_ROM,
@@ -206,12 +220,19 @@ static int imx6_ccm_probe(struct device_d *dev)
clks[IMX6UL_CLK_QSPI1_SEL]= imx_clk_mux("qspi1_sel",base +
0x1c, 7, 3, qspi1_sels, ARRAY_SIZE(qspi1_sels));
clks[IMX6UL_CLK_PERCLK_SEL] = imx_clk_mux("perclk_sel", base +
0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels));
clks[IMX6UL_CLK_CAN_SEL] = imx_clk_mux("can_sel", base +
0x20, 8, 2, can_sels, ARRAY_SIZE(can_sels));
+ if (clk_on_imx6ull())
+ clks[IMX6ULL_CLK_ESAI_SEL]= imx_clk_mux("esai_sel",
base + 0x20, 19, 2, esai_sels, ARRAY_SIZE(esai_sels));
clks[IMX6UL_CLK_UART_SEL] = imx_clk_mux("uart_sel", base +
0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels));
clks[IMX6UL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel", base +
0x2c, 15, 3, enfc_sels, ARRAY_SIZE(enfc_sels));
clks[IMX6UL_CLK_LDB_DI0_SEL] = imx_clk_mux("ldb_di0_sel", base +
0x2c, 9, 3, ldb_di0_sels, ARRAY_SIZE(ldb_di0_sels));
clks[IMX6UL_CLK_SPDIF_SEL]= imx_clk_mux("spdif_sel",base +
0x30, 20, 2, spdif_sels, ARRAY_SIZE(spdif_sels));
- clks[IMX6UL_CLK_SIM_PRE_SEL] = imx_clk_mux("sim_pre_sel", base +
0x34, 15, 3, sim_pre_sels, ARRAY_SIZE(sim_pre_sels));
- clks[IMX6UL_CLK_SIM_SEL] = imx_clk_mux("sim_sel", base +
0x34, 9, 3, sim_sels, ARRAY_SIZE(sim_sels));
+ if (clk_on_imx6ul()) {
+ clks[IMX6UL_CLK_SIM_PRE_SEL] = imx_clk_mux("sim_pre_sel",
base + 0x34, 15, 3, sim_pre_sels, ARRAY_SIZE(sim_pre_sels));
+ clks[IMX6UL_CLK_SIM_SEL] = imx_clk_mux("sim_sel",
base + 0x34, 9, 3, sim_sels, ARRAY_SIZE(sim_sels));
+ } else if (clk_on_imx6ull()) {
+ clks[IMX6ULL_CLK_EPDC_PRE_SEL]= imx_clk_mux("epdc_pre_sel",
base + 0x34, 15, 3, epdc_pre_sels, ARRAY_SIZE(epdc_pre_sels));
+ clks[IMX6ULL_CLK_EPDC_SEL]= imx_clk_mux("epdc_sel",
base + 0x34, 9, 3, epdc_sels, ARRAY_SIZE(epdc_sels));
+ }
clks[IMX6UL_CLK_ECSPI_SEL]= imx_clk_mux("ecspi_sel",base +
0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels));
clks[IMX6UL_CLK_LCDIF_PRE_SEL]= imx_clk_mux("lcdif_pre_sel", base +
0x38, 15, 3, lcdif_pre_sels, ARRAY_SIZE(lcdif_pre_sels));
clks[IMX6UL_CLK_LCDIF_SEL]= imx_clk_mux("lcdif_sel",base +
0x38, 9, 3, lcdif_sels, ARRAY_SIZE(lcdif_sels));
@@ -244,6 +265,10 @@ static int imx6_ccm_probe(struct device_d *dev)
clks[IMX6UL_CLK_SAI3_PODF] = imx_clk_divider("sai3_podf",
"sai3_pred", base + 0x28, 16, 6);
clks[IMX6UL_CLK_SAI1_PRED] = imx_clk_divider("sai1_pred",
"sai1_sel", base + 0x28, 6, 3);
clks[IMX6UL_CLK_SAI1_PODF] = im
[PATCH 3/3] ARCH: ARM: Add support for phytec-phycore-imx6ull
Created imx6ull devicetree to support Phytec phyCORE-i.MX6ULL.
- 256 MB RAM
- 128 MB NAND
- 10/100 Mbit Ethernet
Signed-off-by: Stefan Riedmueller
---
.../flash-header-phytec-pcl063-256mb.imxcfg| 9 ++
arch/arm/boards/phytec-som-imx6/lowlevel.c | 7 +-
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/imx6ul-phytec-phycore-som.dts | 146 +
arch/arm/dts/imx6ul-phytec-phycore-som.dtsi| 178 +
arch/arm/dts/imx6ull-phytec-phycore-som.dts| 41 +
images/Makefile.imx| 5 +
7 files changed, 241 insertions(+), 148 deletions(-)
create mode 100644
arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063-256mb.imxcfg
create mode 100644 arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
create mode 100644 arch/arm/dts/imx6ull-phytec-phycore-som.dts
diff --git
a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063-256mb.imxcfg
b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063-256mb.imxcfg
new file mode 100644
index 000..4a827e4
--- /dev/null
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063-256mb.imxcfg
@@ -0,0 +1,9 @@
+
+#define SETUP_MDCFG0 \
+ wm 32 0x021B000C 0x676B52F3
+
+#define SETUP_MDASP_MDCTL \
+ wm 32 0x021B0040 0x0047;\
+ wm 32 0x021B 0x8318
+
+#include "flash-header-phytec-pcl063.h"
diff --git a/arch/arm/boards/phytec-som-imx6/lowlevel.c
b/arch/arm/boards/phytec-som-imx6/lowlevel.c
index 3ab88f4..07ac443 100644
--- a/arch/arm/boards/phytec-som-imx6/lowlevel.c
+++ b/arch/arm/boards/phytec-som-imx6/lowlevel.c
@@ -54,7 +54,8 @@ static void __noreturn start_imx6_phytec_common(uint32_t size,
int cpu_type = __imx6_cpu_type();
void *fdt;
- if (cpu_type == IMX6_CPUTYPE_IMX6UL) {
+ if (cpu_type == IMX6_CPUTYPE_IMX6UL
+ || cpu_type == IMX6_CPUTYPE_IMX6ULL) {
arm_cpu_lowlevel_init();
/* OCRAM Free Area is 0x00907000 to 0x00918000 (68KB) */
arm_setup_stack(0x0091 - 8);
@@ -69,7 +70,8 @@ static void __noreturn start_imx6_phytec_common(uint32_t size,
fdt = fdt_blob_fixed_offset - get_runtime_offset();
- if (cpu_type == IMX6_CPUTYPE_IMX6UL)
+ if (cpu_type == IMX6_CPUTYPE_IMX6UL
+ || cpu_type == IMX6_CPUTYPE_IMX6ULL)
barebox_arm_entry(0x8000, size, fdt);
else
barebox_arm_entry(0x1000, size, fdt);
@@ -111,3 +113,4 @@ PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_1gib,
imx6q_phytec_phycore_som_
PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_2gib,
imx6q_phytec_phycore_som_emmc, SZ_2G, true);
PHYTEC_ENTRY(start_phytec_phycore_imx6ul_som_512mb, imx6ul_phytec_phycore_som,
SZ_512M, false);
+PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_256mb,
imx6ull_phytec_phycore_som, SZ_256M, false);
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 2342d35..ec291ce 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -53,7 +53,8 @@ pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) +=
imx6q-phytec-pbaa03.dtb.o \
imx6q-phytec-phycore-som-emmc.dtb.o \
imx6dl-phytec-phycore-som-nand.dtb.o \
imx6dl-phytec-phycore-som-emmc.dtb.o \
- imx6ul-phytec-phycore-som.dtb.o
+ imx6ul-phytec-phycore-som.dtb.o \
+ imx6ull-phytec-phycore-som.dtb.o
pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) +=
armada-xp-openblocks-ax3-4-bb.dtb.o
pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) +=
kirkwood-openblocks_a6-bb.dtb.o
pbl-dtb-$(CONFIG_MACH_RADXA_ROCK) += rk3188-radxarock.dtb.o
diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dts
b/arch/arm/dts/imx6ul-phytec-phycore-som.dts
index 65a9365..73f7dbe 100644
--- a/arch/arm/dts/imx6ul-phytec-phycore-som.dts
+++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dts
@@ -13,173 +13,29 @@
/dts-v1/;
#include
+#include "imx6ul-phytec-phycore-som.dtsi"
/ {
model = "Phytec phyCORE-i.MX6 Ultra Lite SOM";
compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul";
-
- chosen {
- linux,stdout-path = &uart1;
-
- environment-nand {
- compatible = "barebox,environment";
- device-path = &gpmi, "partname:barebox-environment";
- status = "disabled";
- };
-
- environment-sd1 {
- compatible = "barebox,environment";
- device-path = &usdhc1, "partname:barebox-environment";
- status = "disabled";
- };
- };
};
&fec1 {
- pinctrl-names = "default"
[PATCH 1/3] ARM: i.MX: Add i.MX6 ULL support
Signed-off-by: Stefan Riedmueller
---
arch/arm/mach-imx/imx.c | 2 ++
arch/arm/mach-imx/imx6.c | 3 +++
arch/arm/mach-imx/include/mach/imx6.h | 2 ++
3 files changed, 7 insertions(+)
diff --git a/arch/arm/mach-imx/imx.c b/arch/arm/mach-imx/imx.c
index 1990739..9400105 100644
--- a/arch/arm/mach-imx/imx.c
+++ b/arch/arm/mach-imx/imx.c
@@ -67,6 +67,8 @@ static int imx_soc_from_dt(void)
return IMX_CPU_IMX6;
if (of_machine_is_compatible("fsl,imx6ul"))
return IMX_CPU_IMX6;
+ if (of_machine_is_compatible("fsl,imx6ull"))
+ return IMX_CPU_IMX6;
if (of_machine_is_compatible("fsl,imx7s"))
return IMX_CPU_IMX7;
if (of_machine_is_compatible("fsl,imx7d"))
diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index 44a8dbe..7b3fc1d 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -160,6 +160,9 @@ int imx6_init(void)
case IMX6_CPUTYPE_IMX6UL:
cputypestr = "i.MX6 UltraLite";
break;
+ case IMX6_CPUTYPE_IMX6ULL:
+ cputypestr = "i.MX6 ULL";
+ break;
default:
cputypestr = "unknown i.MX6";
break;
diff --git a/arch/arm/mach-imx/include/mach/imx6.h
b/arch/arm/mach-imx/include/mach/imx6.h
index 327676b..6ad5343 100644
--- a/arch/arm/mach-imx/include/mach/imx6.h
+++ b/arch/arm/mach-imx/include/mach/imx6.h
@@ -18,6 +18,7 @@ void imx6_init_lowlevel(void);
#define IMX6_CPUTYPE_IMX6D 0x263
#define IMX6_CPUTYPE_IMX6Q 0x463
#define IMX6_CPUTYPE_IMX6UL0x164
+#define IMX6_CPUTYPE_IMX6ULL 0x165
#define SCU_CONFIG 0x04
@@ -82,6 +83,7 @@ DEFINE_MX6_CPU_TYPE(mx6d, IMX6_CPUTYPE_IMX6D);
DEFINE_MX6_CPU_TYPE(mx6sx, IMX6_CPUTYPE_IMX6SX);
DEFINE_MX6_CPU_TYPE(mx6sl, IMX6_CPUTYPE_IMX6SL);
DEFINE_MX6_CPU_TYPE(mx6ul, IMX6_CPUTYPE_IMX6UL);
+DEFINE_MX6_CPU_TYPE(mx6ull, IMX6_CPUTYPE_IMX6ULL);
static inline int __imx6_cpu_revision(void)
{
--
1.9.1
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