Re: [PATCH] gpio: Add designware gpio controller support

2013-10-17 Thread Steffen Trumtrar 
On Thu, Oct 17, 2013 at 10:24:11AM +0200, Sebastian Hesselbarth wrote:
> On 10/17/2013 10:04 AM, Steffen Trumtrar wrote:
> >On Mon, Sep 09, 2013 at 06:28:48PM +0200, Sebastian Hesselbarth wrote:
> >>On 09/09/13 16:54, Sascha Hauer wrote:
> >>>Signed-off-by: Sascha Hauer 
> >>>---
> >>>  drivers/gpio/Kconfig   |   6 ++
> >>>  drivers/gpio/Makefile  |   1 +
> >>>  drivers/gpio/gpio-dw.c | 151 
> >>> +
> >>>  3 files changed, 158 insertions(+)
> >>>  create mode 100644 drivers/gpio/gpio-dw.c
> >>>
> >>>diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
> >>>index d5ac532..18d3135 100644
> >>>--- a/drivers/gpio/Kconfig
> >>>+++ b/drivers/gpio/Kconfig
> >>>@@ -54,6 +54,12 @@ config GPIO_TEGRA
> >>>   help
> >>> Say yes here to include the driver for the GPIO controller found on 
> >>> the
> >>> Tegra line of SoCs.
> >>>+
> >>>+config GPIO_DESIGNWARE
> >>>+  tristate "Synopsys DesignWare GPIO driver"
> >>
> >>Sascha,
> >>
> >>I know DW's GPIO is also used on Armada 1500 which I currently work on.
> >>Precisely, the IP is named dw-apb-gpio. Maybe the above should also
> >>reflect APB.
> >>
> >>[...]
> >>
> >>Please add "snps,dw-apb-gpio", that's what the linux driver
> >>will look for if make to pick it up for Armada 1500.
> >>
> >
> >Are you talking about the 'old' linux driver that was posted sometime around
> >January 2012 or are you working on your own?
> 
> Cannot recall the actual version or time posted. I didn't find time to
> work on a linux driver for dw-apb-gpio, yet. My idea was to pick up the
> latest driver posted plus make it more general. IIRC the one posted was
> very limited to socfpga.
> 

The one I found, is already used in a picoxcell dts. Altough, no driver is 
present.
Altera has a driver in their kernel, but the binding is different.
Actually, that is where Sascha got it from. So, let's try and use at least the
binding from Altera ;-)

> >Do you have a working pre-release version somewhere?
> 
> Sorry, nothing started, yet.
> 

Okay.

> Are you going to work on it? If so, feel free to involve me in patches
> and reviews.

If time permits, yes.

Regards,
Steffen

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Re: [PATCH] gpio: Add designware gpio controller support

2013-10-17 Thread Sebastian Hesselbarth 

On 10/17/2013 10:04 AM, Steffen Trumtrar wrote:

On Mon, Sep 09, 2013 at 06:28:48PM +0200, Sebastian Hesselbarth wrote:

On 09/09/13 16:54, Sascha Hauer wrote:

Signed-off-by: Sascha Hauer 
---
  drivers/gpio/Kconfig   |   6 ++
  drivers/gpio/Makefile  |   1 +
  drivers/gpio/gpio-dw.c | 151 +
  3 files changed, 158 insertions(+)
  create mode 100644 drivers/gpio/gpio-dw.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index d5ac532..18d3135 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -54,6 +54,12 @@ config GPIO_TEGRA
help
  Say yes here to include the driver for the GPIO controller found on 
the
  Tegra line of SoCs.
+
+config GPIO_DESIGNWARE
+   tristate "Synopsys DesignWare GPIO driver"


Sascha,

I know DW's GPIO is also used on Armada 1500 which I currently work on.
Precisely, the IP is named dw-apb-gpio. Maybe the above should also
reflect APB.

[...]

Please add "snps,dw-apb-gpio", that's what the linux driver
will look for if make to pick it up for Armada 1500.



Are you talking about the 'old' linux driver that was posted sometime around
January 2012 or are you working on your own?


Cannot recall the actual version or time posted. I didn't find time to
work on a linux driver for dw-apb-gpio, yet. My idea was to pick up the
latest driver posted plus make it more general. IIRC the one posted was
very limited to socfpga.


Do you have a working pre-release version somewhere?


Sorry, nothing started, yet.

Are you going to work on it? If so, feel free to involve me in patches
and reviews.

Sebastian


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Re: [PATCH] gpio: Add designware gpio controller support

2013-10-17 Thread Steffen Trumtrar 
Hi!

On Mon, Sep 09, 2013 at 06:28:48PM +0200, Sebastian Hesselbarth wrote:
> On 09/09/13 16:54, Sascha Hauer wrote:
> >Signed-off-by: Sascha Hauer 
> >---
> >  drivers/gpio/Kconfig   |   6 ++
> >  drivers/gpio/Makefile  |   1 +
> >  drivers/gpio/gpio-dw.c | 151 
> > +
> >  3 files changed, 158 insertions(+)
> >  create mode 100644 drivers/gpio/gpio-dw.c
> >
> >diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
> >index d5ac532..18d3135 100644
> >--- a/drivers/gpio/Kconfig
> >+++ b/drivers/gpio/Kconfig
> >@@ -54,6 +54,12 @@ config GPIO_TEGRA
> > help
> >   Say yes here to include the driver for the GPIO controller found on 
> > the
> >   Tegra line of SoCs.
> >+
> >+config GPIO_DESIGNWARE
> >+tristate "Synopsys DesignWare GPIO driver"
> 
> Sascha,
> 
> I know DW's GPIO is also used on Armada 1500 which I currently work on.
> Precisely, the IP is named dw-apb-gpio. Maybe the above should also
> reflect APB.
> 
> [...]
> 
> Please add "snps,dw-apb-gpio", that's what the linux driver
> will look for if make to pick it up for Armada 1500.
> 

Are you talking about the 'old' linux driver that was posted sometime around
January 2012 or are you working on your own?

Do you have a working pre-release version somewhere?

Thanks,
Steffen

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Re: [PATCH] gpio: Add designware gpio controller support

2013-09-10 Thread Sascha Hauer 
On Tue, Sep 10, 2013 at 10:56:52AM +0200, Sebastian Hesselbarth wrote:
> On 09/10/2013 09:48 AM, Sascha Hauer wrote:
> >On Mon, Sep 09, 2013 at 06:28:48PM +0200, Sebastian Hesselbarth wrote:
> >>I have seen this driver and think it can be improved by exploiting
> >>its config1/2 registers where synthesis settings are stored. Please
> >>also look at [1] pp.1229; you can read out number of ports, port
> >>width, interrupt, and debounce features.
> >
> >Ok, the port width feature is easy enough to implement. Will add it in
> >the next version.
> >
> >I also added a check for multiple ports, but just ignore the additional
> >ports for now since I don't know the register offsets and also have no
> >hardware to actually test it (The SoCFPGA only has one port)
> 
> Ok, fair enough. IIRC the Armada 1500 uses multiple instances instead
> of multiple ports, too.
> 
> >>Unfortunately, I am not ready to run barebox on Armada 1500 and I
> >>don't have a socfpga to test. So if you are not eager to modify it now,
> >>I can add config reg based read-out later.
> >>
> >>[1] http://www.altera.com/literature/hb/arria-v/hps.pdf
> >>
> >>[...]
> >>>+static __maybe_unused struct of_device_id dwgpio_match[] = {
> >>>+  {
> >>>+  .compatible = "snps,dw-gpio",
> >>>+  }, {
> >>
> >>Please add "snps,dw-apb-gpio", that's what the linux driver
> >>will look for if make to pick it up for Armada 1500.
> >
> >I'll better just change it to "snps,dw-apb-gpio". There already is a
> >dtsi file in the kernel which uses this binding (although it looks like
> >it hasn't been approved by anyone)
> 
> The driver got Acks, but must have slipped through. I have seen your
> v2 but it still uses "snps,dw-gpio".

Fixed this now for real.

Sascha

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Re: [PATCH] gpio: Add designware gpio controller support

2013-09-10 Thread Sebastian Hesselbarth 

On 09/10/2013 09:48 AM, Sascha Hauer wrote:

On Mon, Sep 09, 2013 at 06:28:48PM +0200, Sebastian Hesselbarth wrote:

I have seen this driver and think it can be improved by exploiting
its config1/2 registers where synthesis settings are stored. Please
also look at [1] pp.1229; you can read out number of ports, port
width, interrupt, and debounce features.


Ok, the port width feature is easy enough to implement. Will add it in
the next version.

I also added a check for multiple ports, but just ignore the additional
ports for now since I don't know the register offsets and also have no
hardware to actually test it (The SoCFPGA only has one port)


Ok, fair enough. IIRC the Armada 1500 uses multiple instances instead
of multiple ports, too.


Unfortunately, I am not ready to run barebox on Armada 1500 and I
don't have a socfpga to test. So if you are not eager to modify it now,
I can add config reg based read-out later.

[1] http://www.altera.com/literature/hb/arria-v/hps.pdf

[...]

+static __maybe_unused struct of_device_id dwgpio_match[] = {
+   {
+   .compatible = "snps,dw-gpio",
+   }, {


Please add "snps,dw-apb-gpio", that's what the linux driver
will look for if make to pick it up for Armada 1500.


I'll better just change it to "snps,dw-apb-gpio". There already is a
dtsi file in the kernel which uses this binding (although it looks like
it hasn't been approved by anyone)


The driver got Acks, but must have slipped through. I have seen your
v2 but it still uses "snps,dw-gpio".

Sebastian


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Re: [PATCH] gpio: Add designware gpio controller support

2013-09-10 Thread Sascha Hauer 
On Mon, Sep 09, 2013 at 06:28:48PM +0200, Sebastian Hesselbarth wrote:
> I have seen this driver and think it can be improved by exploiting
> its config1/2 registers where synthesis settings are stored. Please
> also look at [1] pp.1229; you can read out number of ports, port
> width, interrupt, and debounce features.

Ok, the port width feature is easy enough to implement. Will add it in
the next version.

I also added a check for multiple ports, but just ignore the additional
ports for now since I don't know the register offsets and also have no
hardware to actually test it (The SoCFPGA only has one port)

> 
> Unfortunately, I am not ready to run barebox on Armada 1500 and I
> don't have a socfpga to test. So if you are not eager to modify it now,
> I can add config reg based read-out later.
> 
> [1] http://www.altera.com/literature/hb/arria-v/hps.pdf
> 
> [...]
> >+static __maybe_unused struct of_device_id dwgpio_match[] = {
> >+{
> >+.compatible = "snps,dw-gpio",
> >+}, {
> 
> Please add "snps,dw-apb-gpio", that's what the linux driver
> will look for if make to pick it up for Armada 1500.

I'll better just change it to "snps,dw-apb-gpio". There already is a
dtsi file in the kernel which uses this binding (although it looks like
it hasn't been approved by anyone)

Sascha

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Re: [PATCH] gpio: Add designware gpio controller support

2013-09-09 Thread Sebastian Hesselbarth 

On 09/09/13 16:54, Sascha Hauer wrote:

Signed-off-by: Sascha Hauer 
---
  drivers/gpio/Kconfig   |   6 ++
  drivers/gpio/Makefile  |   1 +
  drivers/gpio/gpio-dw.c | 151 +
  3 files changed, 158 insertions(+)
  create mode 100644 drivers/gpio/gpio-dw.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index d5ac532..18d3135 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -54,6 +54,12 @@ config GPIO_TEGRA
help
  Say yes here to include the driver for the GPIO controller found on 
the
  Tegra line of SoCs.
+
+config GPIO_DESIGNWARE
+   tristate "Synopsys DesignWare GPIO driver"


Sascha,

I know DW's GPIO is also used on Armada 1500 which I currently work on.
Precisely, the IP is named dw-apb-gpio. Maybe the above should also
reflect APB.

[...]

diff --git a/drivers/gpio/gpio-dw.c b/drivers/gpio/gpio-dw.c
new file mode 100644
index 000..54e7452
--- /dev/null
+++ b/drivers/gpio/gpio-dw.c
@@ -0,0 +1,151 @@

[...]

+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define GPIO_INT_EN_REG_OFFSET 0x30
+#define GPIO_INT_MASK_REG_OFFSET   0x34
+#define GPIO_INT_TYPE_LEVEL_REG_OFFSET 0x38
+#define GPIO_INT_POLARITY_REG_OFFSET   0x3c
+#define GPIO_INT_STATUS_REG_OFFSET 0x40
+#define GPIO_PORT_A_EOI_REG_OFFSET 0x4c


I have seen this driver and think it can be improved by exploiting
its config1/2 registers where synthesis settings are stored. Please
also look at [1] pp.1229; you can read out number of ports, port
width, interrupt, and debounce features.

Unfortunately, I am not ready to run barebox on Armada 1500 and I
don't have a socfpga to test. So if you are not eager to modify it now,
I can add config reg based read-out later.

[1] http://www.altera.com/literature/hb/arria-v/hps.pdf

[...]

+static __maybe_unused struct of_device_id dwgpio_match[] = {
+   {
+   .compatible = "snps,dw-gpio",
+   }, {


Please add "snps,dw-apb-gpio", that's what the linux driver
will look for if make to pick it up for Armada 1500.

Sebastian


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[PATCH] gpio: Add designware gpio controller support

2013-09-09 Thread Sascha Hauer 
Signed-off-by: Sascha Hauer 
---
 drivers/gpio/Kconfig   |   6 ++
 drivers/gpio/Makefile  |   1 +
 drivers/gpio/gpio-dw.c | 151 +
 3 files changed, 158 insertions(+)
 create mode 100644 drivers/gpio/gpio-dw.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index d5ac532..18d3135 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -54,6 +54,12 @@ config GPIO_TEGRA
help
  Say yes here to include the driver for the GPIO controller found on 
the
  Tegra line of SoCs.
+
+config GPIO_DESIGNWARE
+   tristate "Synopsys DesignWare GPIO driver"
+   help
+ Say Y or M here to build support for the Synopsys DesignWare APB
+ GPIO block.
 endmenu
 
 endif
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index adb668f..dc9fb13 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_GPIO_ORION)+= gpio-orion.o
 obj-$(CONFIG_GPIO_PL061)   += gpio-pl061.o
 obj-$(CONFIG_GPIO_STMPE)   += gpio-stmpe.o
 obj-$(CONFIG_GPIO_TEGRA)   += gpio-tegra.o
+obj-$(CONFIG_GPIO_DESIGNWARE)  += gpio-dw.o
diff --git a/drivers/gpio/gpio-dw.c b/drivers/gpio/gpio-dw.c
new file mode 100644
index 000..54e7452
--- /dev/null
+++ b/drivers/gpio/gpio-dw.c
@@ -0,0 +1,151 @@
+/*
+ * Designware GPIO support functions
+ *
+ * Copyright (C) 2012 Altera
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define GPIO_INT_EN_REG_OFFSET 0x30
+#define GPIO_INT_MASK_REG_OFFSET   0x34
+#define GPIO_INT_TYPE_LEVEL_REG_OFFSET 0x38
+#define GPIO_INT_POLARITY_REG_OFFSET   0x3c
+#define GPIO_INT_STATUS_REG_OFFSET 0x40
+#define GPIO_PORT_A_EOI_REG_OFFSET 0x4c
+
+#define GPIO_DDR_OFFSET_PORT   0x4
+#define DW_GPIO_EXT0x50
+#define DW_GPIO_DR 0x0
+
+struct dw_gpio_instance {
+   struct gpio_chip chip;
+   u32 gpio_state; /* GPIO state shadow register */
+   u32 gpio_dir;   /* GPIO direction shadow register */
+   void __iomem *regs;
+};
+
+static inline struct dw_gpio_instance *to_dw_gpio(struct gpio_chip *gc)
+{
+   return container_of(gc, struct dw_gpio_instance, chip);
+}
+
+static int dw_gpio_get(struct gpio_chip *gc, unsigned offset)
+{
+   struct dw_gpio_instance *chip = to_dw_gpio(gc);
+
+   return (readl(chip->regs + DW_GPIO_EXT) >> offset) & 1;
+}
+
+static void dw_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
+{
+   struct dw_gpio_instance *chip = to_dw_gpio(gc);
+   u32 data_reg;
+
+   data_reg = readl(chip->regs + DW_GPIO_DR);
+   data_reg = (data_reg & ~(1regs + GPIO_DDR_OFFSET_PORT);
+   gpio_ddr &= ~(1 << offset);
+   writel(gpio_ddr, chip->regs + GPIO_DDR_OFFSET_PORT);
+
+   return 0;
+}
+
+static int dw_gpio_direction_output(struct gpio_chip *gc,
+   unsigned offset, int value)
+{
+   struct dw_gpio_instance *chip = to_dw_gpio(gc);
+   u32 gpio_ddr;
+
+   dw_gpio_set(gc, offset, value);
+
+   /* Set pin as output, assumes software controlled IP */
+   gpio_ddr = readl(chip->regs + GPIO_DDR_OFFSET_PORT);
+   gpio_ddr |= (1 << offset);
+   writel(gpio_ddr, chip->regs + GPIO_DDR_OFFSET_PORT);
+
+   return 0;
+}
+
+static struct gpio_ops imx_gpio_ops = {
+   .direction_input = dw_gpio_direction_input,
+   .direction_output = dw_gpio_direction_output,
+   .get = dw_gpio_get,
+   .set = dw_gpio_set,
+};
+
+static int dw_gpio_probe(struct device_d *dev)
+{
+   struct dw_gpio_instance *chip;
+   int ret;
+
+   chip = xzalloc(sizeof(*chip));
+   chip->regs = dev_request_mem_region(dev, 0);
+   if (!chip->regs)
+   return -EBUSY;
+
+   chip->chip.ops = &imx_gpio_ops;
+   if (dev->id < 0) {
+   chip->chip.base = of_alias_get_id(dev->device_node, "gpio");
+   if (chip->chip.base < 0)
+   return chip->chip.base;
+   chip->chip.base