Re: [PATCH] i2c: Add support for DesignWare controllers
On Sat, Oct 31, 2015 at 09:30:41PM -0700, Andrey Smirnov wrote:
> Add a driver for DesignWare I2C controller IP block found on several
> SoCs including Altera SoC products
>
> Tested using Terrasic SoCKit board and GPIO expander board with I2C
> EEPROM on it
>
> Signed-off-by: Andrey Smirnov
> ---
Looks mostly fine. Two small nitpicks inside.
> +static int i2c_dw_probe(struct device_d *pdev)
> +{
> + struct dw_i2c_dev *dw;
> + struct i2c_platform_data *pdata;
> + int ret, bitrate;
> + uint32_t ic_con, ic_comp_type_value;
> +
> + pdata = pdev->platform_data;
> +
> + dw = kzalloc(sizeof(*dw), GFP_KERNEL);
kzalloc can fail. You should use xzalloc here which cannot fail.
> +
> + if (IS_ENABLED(CONFIG_COMMON_CLK)) {
> + dw->clk = clk_get(pdev, NULL);
> + if (IS_ERR(dw->clk)) {
> + ret = PTR_ERR(dw->clk);
> + goto fail;
> + }
> + }
> +
> + dw->adapter.master_xfer = i2c_dw_xfer;
> + dw->adapter.nr = pdev->id;
> + dw->adapter.dev.parent = pdev;
> + dw->adapter.dev.device_node = pdev->device_node;
> +
> + dw->base = dev_request_mem_region(pdev, 0);
> + if (IS_ERR(dw->base)) {
> + ret = PTR_ERR(dw->base);
> + goto fail;
> + }
> +
> + ic_comp_type_value = readl(dw->base + DW_IC_COMP_TYPE);
> + if (ic_comp_type_value != DW_IC_COMP_TYPE_VALUE) {
> + dev_err(pdev,
> + "unknown DesignWare IP block 0x%08x",
> + ic_comp_type_value);
> + ret = -ENODEV;
> + goto fail;
> + }
> +
> + i2c_dw_enable(dw, false);
> +
> + if (IS_ENABLED(CONFIG_COMMON_CLK))
> + i2c_dw_setup_timings(dw);
> +
> + bitrate = (pdata && pdata->bitrate) ? pdata->bitrate : DW_I2C_BIT_RATE;
> +
> + /*
> + * We have to clear 'ic_10bitaddr_master' in 'ic_tar'
> + * register, otherwise 'ic_10bitaddr_master' in 'ic_con'
> + * wouldn't clear. We don't care about preserving the contents
> + * of that register so we set it to zero.
> + */
> + writel(0, dw->base + DW_IC_TAR);
> +
> + switch (bitrate) {
> + case 40:
> + ic_con = DW_IC_CON_SPEED_FAST;
> + break;
> + default:
> + dev_warn(pdev, "requested bitrate (%d) is not supported."
> + " Falling back to 100kHz", bitrate);
> + case 10:/* FALLTHROUGH */
> + ic_con = DW_IC_CON_SPEED_STD;
> + break;
> + }
> +
> + ic_con |= DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE;
> +
> + writel(ic_con, dw->base + DW_IC_CON);
> +
> + /*
> + * Since we will be working in polling mode set both
> + * thresholds to their minimum
> + */
> + writel(0, dw->base + DW_IC_RX_TL);
> + writel(0, dw->base + DW_IC_TX_TL);
> +
> + /* Disable and clear all interrrupts */
> + writel(0, dw->base + DW_IC_INTR_MASK);
> + readl(dw->base + DW_IC_CLR_INTR);
> +
> + i2c_dw_enable(dw, true);
> +
> + ret = i2c_add_numbered_adapter(&dw->adapter);
> +fail:
> + if (ret < 0) {
> + dev_err(pdev, "registration failed\n");
This message is unnecessary. The driver core will warn you when probe
fails anyway.
Sascha
--
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[PATCH] i2c: Add support for DesignWare controllers
Add a driver for DesignWare I2C controller IP block found on several SoCs including Altera SoC products Tested using Terrasic SoCKit board and GPIO expander board with I2C EEPROM on it Signed-off-by: Andrey Smirnov --- drivers/i2c/busses/Kconfig | 6 + drivers/i2c/busses/Makefile | 1 + drivers/i2c/busses/i2c-designware.c | 576 3 files changed, 583 insertions(+) create mode 100644 drivers/i2c/busses/i2c-designware.c diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 181321b..a25a871 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -25,6 +25,12 @@ config I2C_IMX for many i.MX ARM based SoCs, for MPC85xx and MPC5200 PowerPC based SoCs. +config I2C_DESIGNWARE + bool "Synopsys DesignWare I2C Master driver" + help + If you say yes to this option, support will be included for the + Synopsys DesignWare I2C adapter. Only master mode is supported. + config I2C_MV64XXX bool "Marvell mv64xxx I2C Controller" depends on HAVE_CLK && OFDEVICE diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index 1dbfbdf..8dccc38 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -5,3 +5,4 @@ obj-$(CONFIG_I2C_MV64XXX) += i2c-mv64xxx.o obj-$(CONFIG_I2C_OMAP) += i2c-omap.o obj-$(CONFIG_I2C_TEGRA)+= i2c-tegra.o obj-$(CONFIG_I2C_VERSATILE)+= i2c-versatile.o +obj-$(CONFIG_I2C_DESIGNWARE) += i2c-designware.o diff --git a/drivers/i2c/busses/i2c-designware.c b/drivers/i2c/busses/i2c-designware.c new file mode 100644 index 000..333d312 --- /dev/null +++ b/drivers/i2c/busses/i2c-designware.c @@ -0,0 +1,576 @@ +/* + * Synopsys DesignWare I2C adapter driver (master only). + * + * Partly based on code of similar driver from U-Boot: + *Copyright (C) 2009 ST Micoelectronics + * + * and corresponding code from Linux Kernel + *Copyright (C) 2006 Texas Instruments. + *Copyright (C) 2007 MontaVista Software Inc. + *Copyright (C) 2009 Provigent Ltd. + * + * Copyright (C) 2014 Andrey Smirnov + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define DW_I2C_BIT_RATE10 + +#define DW_IC_CON 0x0 +#define DW_IC_CON_MASTER (1 << 0) +#define DW_IC_CON_SPEED_STD(1 << 1) +#define DW_IC_CON_SPEED_FAST (1 << 2) +#define DW_IC_CON_SLAVE_DISABLE(1 << 6) + +#define DW_IC_TAR 0x4 + +#define DW_IC_DATA_CMD 0x10 +#define DW_IC_DATA_CMD_CMD (1 << 8) +#define DW_IC_DATA_CMD_STOP(1 << 9) + +#define DW_IC_SS_SCL_HCNT 0x14 +#define DW_IC_SS_SCL_LCNT 0x18 +#define DW_IC_FS_SCL_HCNT 0x1c +#define DW_IC_FS_SCL_LCNT 0x20 + +#define DW_IC_INTR_MASK0x30 + +#define DW_IC_RAW_INTR_STAT0x34 +#define DW_IC_INTR_RX_UNDER(1 << 0) +#define DW_IC_INTR_RX_OVER (1 << 1) +#define DW_IC_INTR_RX_FULL (1 << 2) +#define DW_IC_INTR_TX_OVER (1 << 3) +#define DW_IC_INTR_TX_EMPTY(1 << 4) +#define DW_IC_INTR_RD_REQ (1 << 5) +#define DW_IC_INTR_TX_ABRT (1 << 6) +#define DW_IC_INTR_RX_DONE (1 << 7) +#define DW_IC_INTR_ACTIVITY(1 << 8) +#define DW_IC_INTR_STOP_DET(1 << 9) +#define DW_IC_INTR_START_DET (1 << 10) +#define DW_IC_INTR_GEN_CALL(1 << 11) + +#define DW_IC_RX_TL0x38 +#define DW_IC_TX_TL0x3c +#define DW_IC_CLR_INTR 0x40 +#define DW_IC_CLR_TX_ABRT 0x54 + +#define DW_IC_ENABLE 0x6c +#define DW_IC_ENABLE_ENABLE(1 << 0) + +#define DW_IC_STATUS 0x70 +#define DW_IC_STATUS_TFNF (1 << 1) +#define DW_IC_STATUS_TFE (1 << 2) +#define DW_IC_STATUS_RFNE (1 << 3) +#define DW_IC_STATUS_MST_ACTIVITY (1 << 5) + +#define DW_IC_TX_ABRT_SOURCE 0x80 + +#define DW_IC_ENABLE_STATUS0x9c +#define DW_IC_ENABLE_STATUS_IC_EN (1 << 0) + +#define DW_IC_COMP_TYPE0xfc +#define DW_IC_COMP_TYPE_VALUE 0x44570140 + +#define MAX_T_POLL_COUNT 100 + +#define DW_TIMEOUT_IDLE
