The core has a bit for swapping packet data endianism.
Reset default from Cadence is off. Xilinx however, that uses this core on the
Zynq SoCs, opted for on. Turn it off for all devices.
Signed-off-by: Steffen Trumtrar <s.trumt...@pengutronix.de>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagn...@jcrosoft.com>
---
Notes:
This fix was already applied to next for the linux driver counterpart.
drivers/net/macb.c | 1 +
drivers/net/macb.h | 2 ++
2 files changed, 3 insertions(+)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 14a0689..4c0f206 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -307,6 +307,7 @@ static void macb_configure_dma(struct macb_device *bp)
dmacfg |= GEM_BF(FBLDO, 16);
dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
dmacfg |= GEM_BIT(DDRP);
+ dmacfg &= ~GEM_BIT(ENDIA);
gem_writel(bp, DMACFG, dmacfg);
}
}
diff --git a/drivers/net/macb.h b/drivers/net/macb.h
index cadd561..1be9ff9 100644
--- a/drivers/net/macb.h
+++ b/drivers/net/macb.h
@@ -168,6 +168,8 @@
/* Bitfields in DMACFG. */
#define GEM_FBLDO_OFFSET 0
#define GEM_FBLDO_SIZE 5
+#define GEM_ENDIA_OFFSET 7
+#define GEM_ENDIA_SIZE 1
#define GEM_RXBMS_OFFSET 8
#define GEM_RXBMS_SIZE 2
#define GEM_TXPBMS_OFFSET 10
--
1.8.2.rc2
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