Re: [PATCH 7/9] RISC-V: add initial LiteX SoC support
On Wed, 05 May 2021 12:45:23 +0200 Jan Lübbe wrote: > On Wed, 2021-05-05 at 13:08 +0300, Antony Pavlov wrote: > > LiteX is a Migen-based System on Chip, supporting softcore > > VexRiscv CPU, a 32-bits Linux Capable RISC-V CPU. > > > > See https://github.com/enjoy-digital/litex and > > https://github.com/litex-hub/linux-on-litex-vexriscv > > for details. > > > > Signed-off-by: Antony Pavlov > > --- > > > > > > > > +config MACH_LITEX > > + bool "litex family" > > + select ARCH_RV32I > > + select HAS_DEBUG_LL > > + select HAS_NMON > > + select USE_COMPRESSED_DTB > > + select RISCV_SBI > > + > > > Hmm, there is also https://github.com/litex-hub/linux-on-litex-rocket/ which > uses the 64-bit RocketChip CPU. How would that fit into this naming scheme? > Would it be a different MACH? Rocket is a 64-bit core, VexRiscv is a 32-bit core. All LiteX family SoC use the same peripheral IP cores, but different CPU cores. The situation is similar to MIPS Malta FPGA devboard, main FPGA can be burned with very different CPU bitstreams: config MIPS_MALTA bool "MIPS Malta board" ... select SYS_HAS_CPU_MIPS32_R1 select SYS_HAS_CPU_MIPS32_R2 select SYS_HAS_CPU_MIPS32_R3_5 select SYS_HAS_CPU_MIPS32_R5 select SYS_HAS_CPU_MIPS32_R6 select SYS_HAS_CPU_MIPS64_R1 select SYS_HAS_CPU_MIPS64_R2 select SYS_HAS_CPU_MIPS64_R6 select SYS_HAS_CPU_NEVADA select SYS_HAS_CPU_RM7000 I'll investigate the problem more carefully. Thanks for noting! -- Best regards, Antony Pavlov ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH 7/9] RISC-V: add initial LiteX SoC support
On Wed, 2021-05-05 at 13:08 +0300, Antony Pavlov wrote:
> LiteX is a Migen-based System on Chip, supporting softcore
> VexRiscv CPU, a 32-bits Linux Capable RISC-V CPU.
>
> See https://github.com/enjoy-digital/litex and
> https://github.com/litex-hub/linux-on-litex-vexriscv
> for details.
>
> Signed-off-by: Antony Pavlov
> ---
>
>
> +config MACH_LITEX
> + bool "litex family"
> + select ARCH_RV32I
> + select HAS_DEBUG_LL
> + select HAS_NMON
> + select USE_COMPRESSED_DTB
> + select RISCV_SBI
> +
Hmm, there is also https://github.com/litex-hub/linux-on-litex-rocket/ which
uses the 64-bit RocketChip CPU. How would that fit into this naming scheme?
Would it be a different MACH?
> +/dts-v1/;
> +
> +/ {
> + compatible = "litex,vexriscv-soc-linux";
> +
> + #address-cells = <1>;
>
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Re: [PATCH 7/9] RISC-V: add initial LiteX SoC support
Hello Antony,
On 05.05.21 12:08, Antony Pavlov wrote:
> LiteX is a Migen-based System on Chip, supporting softcore
> VexRiscv CPU, a 32-bits Linux Capable RISC-V CPU.
>
> See https://github.com/enjoy-digital/litex and
> https://github.com/litex-hub/linux-on-litex-vexriscv
> for details.
>
> Signed-off-by: Antony Pavlov
> ---
> arch/riscv/Kconfig| 9 ++
> arch/riscv/Makefile | 1 +
> arch/riscv/dts/litex_soc_linux.dtsi | 49 +++
> arch/riscv/mach-litex/Kconfig | 8 ++
> arch/riscv/mach-litex/Makefile| 3 +
> arch/riscv/mach-litex/include/mach/debug_ll.h | 124 ++
> 6 files changed, 194 insertions(+)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index c0583f3153..40dfd7dd93 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -34,6 +34,14 @@ config MACH_ERIZO
> select RISCV_M_MODE
> select RISCV_TIMER
>
> +config MACH_LITEX
> + bool "litex family"
> + select ARCH_RV32I
> + select HAS_DEBUG_LL
> + select HAS_NMON
> + select USE_COMPRESSED_DTB
> + select RISCV_SBI
> +
> config MACH_VIRT
> bool "virt family"
> select BOARD_RISCV_GENERIC_DT
> @@ -83,6 +91,7 @@ config 64BIT
> select PHYS_ADDR_T_64BIT
>
> source "arch/riscv/mach-erizo/Kconfig"
> +source "arch/riscv/mach-litex/Kconfig"
>
> config BOARD_RISCV_GENERIC_DT
> select BOARD_GENERIC_DT
> diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
> index aba4526bba..bc22786368 100644
> --- a/arch/riscv/Makefile
> +++ b/arch/riscv/Makefile
> @@ -20,6 +20,7 @@ cflags-y += $(riscv-cflags-y)
> LDFLAGS_barebox += -nostdlib
>
> machine-$(CONFIG_MACH_ERIZO) := erizo
> +machine-$(CONFIG_MACH_LITEX) := litex
Could you rebase on barebox next?
I dropped machine directories for RISC-V. They were only
used for and there is an
now that can be extended instead.
This reduces boilerplate and allows building all RISC-V
images in one go.
> machine-$(CONFIG_MACH_VIRT) := virt
>
> LDFLAGS_barebox += $(riscv-ldflags-y)
> diff --git a/arch/riscv/dts/litex_soc_linux.dtsi
> b/arch/riscv/dts/litex_soc_linux.dtsi
> new file mode 100644
> index 00..32382b8dc2
> --- /dev/null
> +++ b/arch/riscv/dts/litex_soc_linux.dtsi
Is "linux" a well-nown LiteX configuration?
Otherwise would maybe litex-vexrisc.dtsi be a better name?
> @@ -0,0 +1,49 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +
> +/dts-v1/;
> +
> +/ {
> + compatible = "litex,vexriscv-soc-linux";
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + timebase-frequency = <1>; // 100 MHz
> +
> + cpu@0 {
> + device_type = "cpu";
> + compatible = "spinalhdl,vexriscv", "riscv";
> + reg = <0>;
> + };
> + };
> +
> + uart0: serial@f0001000 {
> + compatible = "litex,uart";
> + reg = <0xf0001000 0x18>;
> + status = "disabled";
> + };
> +
> + mac0: mac@f0009000 {
> + compatible = "litex,liteeth";
> + reg = <0xf0009000 0x7c /* base */
> + 0xf0009800 0x0a /* mdio_base */
> + 0xb000 0x2000>; /* buf_base */
> + tx-fifo-depth = <2>;
> + rx-fifo-depth = <2>;
> + status = "disabled";
> + };
> +
> + spi0: spi@f000b800 {
> + compatible = "litex,spiflash";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + reg = <0xf000b800 0x100>;
> + status = "disabled";
> + };
> +};
> diff --git a/arch/riscv/mach-litex/Kconfig b/arch/riscv/mach-litex/Kconfig
> new file mode 100644
> index 00..19d5927e44
> --- /dev/null
> +++ b/arch/riscv/mach-litex/Kconfig
> @@ -0,0 +1,8 @@
> +if MACH_LITEX
> +
> +choice
> + prompt "Board type"
> +
> +endchoice
> +
> +endif
> diff --git a/arch/riscv/mach-litex/Makefile b/arch/riscv/mach-litex/Makefile
> new file mode 100644
> index 00..d9c51e74c3
> --- /dev/null
> +++ b/arch/riscv/mach-litex/Makefile
> @@ -0,0 +1,3 @@
> +# just to build a built-in.o. Otherwise compilation fails when no o-files is
> +# created.
> +obj- += dummy.o
> diff --git a/arch/riscv/mach-litex/include/mach/debug_ll.h
> b/arch/riscv/mach-litex/include/mach/debug_ll.h
> new file mode 100644
> index 00..df7032716d
> --- /dev/null
> +++ b/arch/riscv/mach-litex/include/mach/debug_ll.h
> @@ -0,0 +1,124 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (C) 2019 Antony Pavlov
> + *
> + * This file is part of barebox.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>
[PATCH 7/9] RISC-V: add initial LiteX SoC support
LiteX is a Migen-based System on Chip, supporting softcore
VexRiscv CPU, a 32-bits Linux Capable RISC-V CPU.
See https://github.com/enjoy-digital/litex and
https://github.com/litex-hub/linux-on-litex-vexriscv
for details.
Signed-off-by: Antony Pavlov
---
arch/riscv/Kconfig| 9 ++
arch/riscv/Makefile | 1 +
arch/riscv/dts/litex_soc_linux.dtsi | 49 +++
arch/riscv/mach-litex/Kconfig | 8 ++
arch/riscv/mach-litex/Makefile| 3 +
arch/riscv/mach-litex/include/mach/debug_ll.h | 124 ++
6 files changed, 194 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index c0583f3153..40dfd7dd93 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -34,6 +34,14 @@ config MACH_ERIZO
select RISCV_M_MODE
select RISCV_TIMER
+config MACH_LITEX
+ bool "litex family"
+ select ARCH_RV32I
+ select HAS_DEBUG_LL
+ select HAS_NMON
+ select USE_COMPRESSED_DTB
+ select RISCV_SBI
+
config MACH_VIRT
bool "virt family"
select BOARD_RISCV_GENERIC_DT
@@ -83,6 +91,7 @@ config 64BIT
select PHYS_ADDR_T_64BIT
source "arch/riscv/mach-erizo/Kconfig"
+source "arch/riscv/mach-litex/Kconfig"
config BOARD_RISCV_GENERIC_DT
select BOARD_GENERIC_DT
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index aba4526bba..bc22786368 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -20,6 +20,7 @@ cflags-y += $(riscv-cflags-y)
LDFLAGS_barebox += -nostdlib
machine-$(CONFIG_MACH_ERIZO) := erizo
+machine-$(CONFIG_MACH_LITEX) := litex
machine-$(CONFIG_MACH_VIRT):= virt
LDFLAGS_barebox += $(riscv-ldflags-y)
diff --git a/arch/riscv/dts/litex_soc_linux.dtsi
b/arch/riscv/dts/litex_soc_linux.dtsi
new file mode 100644
index 00..32382b8dc2
--- /dev/null
+++ b/arch/riscv/dts/litex_soc_linux.dtsi
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/dts-v1/;
+
+/ {
+ compatible = "litex,vexriscv-soc-linux";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ timebase-frequency = <1>; // 100 MHz
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "spinalhdl,vexriscv", "riscv";
+ reg = <0>;
+ };
+ };
+
+ uart0: serial@f0001000 {
+ compatible = "litex,uart";
+ reg = <0xf0001000 0x18>;
+ status = "disabled";
+ };
+
+ mac0: mac@f0009000 {
+ compatible = "litex,liteeth";
+ reg = <0xf0009000 0x7c /* base */
+ 0xf0009800 0x0a /* mdio_base */
+ 0xb000 0x2000>; /* buf_base */
+ tx-fifo-depth = <2>;
+ rx-fifo-depth = <2>;
+ status = "disabled";
+ };
+
+ spi0: spi@f000b800 {
+ compatible = "litex,spiflash";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <0xf000b800 0x100>;
+ status = "disabled";
+ };
+};
diff --git a/arch/riscv/mach-litex/Kconfig b/arch/riscv/mach-litex/Kconfig
new file mode 100644
index 00..19d5927e44
--- /dev/null
+++ b/arch/riscv/mach-litex/Kconfig
@@ -0,0 +1,8 @@
+if MACH_LITEX
+
+choice
+ prompt "Board type"
+
+endchoice
+
+endif
diff --git a/arch/riscv/mach-litex/Makefile b/arch/riscv/mach-litex/Makefile
new file mode 100644
index 00..d9c51e74c3
--- /dev/null
+++ b/arch/riscv/mach-litex/Makefile
@@ -0,0 +1,3 @@
+# just to build a built-in.o. Otherwise compilation fails when no o-files is
+# created.
+obj- += dummy.o
diff --git a/arch/riscv/mach-litex/include/mach/debug_ll.h
b/arch/riscv/mach-litex/include/mach/debug_ll.h
new file mode 100644
index 00..df7032716d
--- /dev/null
+++ b/arch/riscv/mach-litex/include/mach/debug_ll.h
@@ -0,0 +1,124 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2019 Antony Pavlov
+ *
+ * This file is part of barebox.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_LITEX_DEBUG_LL__
+#define __MACH_LITEX_DEBUG_LL__
+
+/** @file
+ * This File contains declaration for early output support
+ */
+
+#include
+
+#define DEBUG_LL_UART_ADDR 0xf0001000
+#define UART_RXTX 0x00
+#define UART_TXFULL0x04
+#define UART_RXEMPTY 0x08
+#define UART_EV_PENDING0x10
+#define UART_EV_RX(1 << 1)
+#define UART_EV_ENABLE 0x14
+
+
+#ifndef __ASSEMBLY__
+
+/*
+ * C macros
+ */
+
+#include
+
+static inline void PUTC_LL(char ch)
+{
+#ifdef CONFIG_DEBUG_LL
+ /*
