Many thanks ksuzik, I had the same issue with mcspi0 as master. Setting SCLK to input by default solved it.
пятница, 11 марта 2016 г., 6:10:07 UTC+3 пользователь ksuzuk...@gmail.com написал: > > Hi, guy. > > I had had the same problem. > But I solved it. > > The problem was very simple. > We have to set "RXACTIVE" bit to CLK Pin's "Conrol Module > Resiters(PINMUX)". > > So dts file is follows > spi0_pins: pinmux_spi0_pins { > pinctrl-single,pins = < > 0x150 ( PIN_INPUT_PULLUP | MUX_MODE0 ) /* (P23) > spi0_sclk.spi0_sclk */ > 0x154 ( PIN_INPUT_PULLUP | MUX_MODE0 ) /* (T22) > spi0_d0.spi0_d0 */ > 0x158 ( PIN_OUTPUT_PULLUP | MUX_MODE0 ) /* (T21) > spi0_d1.spi0_d1 */ > 0x15c ( PIN_OUTPUT_PULLUP | MUX_MODE0 ) /* (T20) > spi0_cs0.spi0_cs0 */ > >; > }; > > And, we can see in "Technical Reference Manual" 26.2.3. > It is said "SPI serial clock (output when master, input when slave)" > And it also said "(1) This output signal is also *used as a re-timing > input*. The associated CONF_<module>_<pin>_RXACTIVE bit for the* output > clock must be set to 1 to enable the clock input back* to the module." > > > -- For more options, visit http://beagleboard.org/discuss --- You received this message because you are subscribed to the Google Groups "BeagleBoard" group. To unsubscribe from this group and stop receiving emails from it, send an email to beagleboard+unsubscr...@googlegroups.com. To view this discussion on the web visit https://groups.google.com/d/msgid/beagleboard/f627a0ce-41b7-4975-94c8-9078385a928f%40googlegroups.com. For more options, visit https://groups.google.com/d/optout.