Tobias,
I believe the PRU is connected directly to the L3 interconnect, so it
has direct access to the DDR memory similar to a DMA controller.
-chris
On Thursday, January 16, 2014 7:37:48 AM UTC-5, tm9...@googlemail.com wrote:
>
> Hello!
>
> I'm afraid this is not really a BeagleBone question. But since PRU is not
> officially supported by TI, I hope someone out here is enlightened... ;-)
> The PRU can access the whole global address range of the Sitara, right?
> But are a PRU's memory accesses run through the MMU?
> My goal is to protect given memory areas and/or peripherals from being
> accessed by PRU code. Is that possible?
>
> Thanks in advance.
>
> Greetings
> Tobias
>
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