From: Junyan He <junyan...@linux.intel.com> Also add setSrc0WithAcc and setSrc1WithAcc help functions to set the correct special accumulator fields of instruction.
Signed-off-by: Junyan He <junyan...@linux.intel.com> --- backend/src/backend/gen8_encoder.cpp | 61 +++++++++++++++++++++++++++++++++++- backend/src/backend/gen8_encoder.hpp | 5 +++ backend/src/backend/gen_defs.hpp | 11 +++++++ 3 files changed, 76 insertions(+), 1 deletion(-) diff --git a/backend/src/backend/gen8_encoder.cpp b/backend/src/backend/gen8_encoder.cpp index 69eabb2..0af27a3 100644 --- a/backend/src/backend/gen8_encoder.cpp +++ b/backend/src/backend/gen8_encoder.cpp @@ -360,6 +360,46 @@ namespace gbe gen8_insn->bits1.da1.dest_horiz_stride = dest.hstride; } + void Gen8Encoder::setSrc0WithAcc(GenNativeInstruction *insn, GenRegister reg, uint32_t accN) { + Gen8NativeInstruction *gen8_insn = &insn->gen8_insn; + assert(reg.file == GEN_GENERAL_REGISTER_FILE); + assert(reg.nr < 128); + assert(gen8_insn->header.access_mode == GEN_ALIGN_16); + assert(reg.subnr == 0); + assert(gen8_insn->header.execution_size >= GEN_WIDTH_4); + + gen8_insn->bits1.da16acc.src0_reg_file = reg.file; + gen8_insn->bits1.da16acc.src0_reg_type = reg.type; + gen8_insn->bits2.da16acc.src0_abs = reg.absolute; + gen8_insn->bits2.da16acc.src0_negate = reg.negation; + gen8_insn->bits2.da16acc.src0_address_mode = reg.address_mode; + gen8_insn->bits2.da16acc.src0_subreg_nr = reg.subnr / 16; + gen8_insn->bits2.da16acc.src0_reg_nr = reg.nr; + gen8_insn->bits2.da16acc.src0_specal_acc_lo = accN; + gen8_insn->bits2.da16acc.src0_specal_acc_hi = 0; + gen8_insn->bits2.da16acc.src0_vert_stride = reg.vstride; + } + + void Gen8Encoder::setSrc1WithAcc(GenNativeInstruction *insn, GenRegister reg, uint32_t accN) { + Gen8NativeInstruction *gen8_insn = &insn->gen8_insn; + assert(reg.file == GEN_GENERAL_REGISTER_FILE); + assert(reg.nr < 128); + assert(gen8_insn->header.access_mode == GEN_ALIGN_16); + assert(reg.subnr == 0); + assert(gen8_insn->header.execution_size >= GEN_WIDTH_4); + + gen8_insn->bits2.da16acc.src1_reg_file = reg.file; + gen8_insn->bits2.da16acc.src1_reg_type = reg.type; + gen8_insn->bits3.da16acc.src1_abs = reg.absolute; + gen8_insn->bits3.da16acc.src1_negate = reg.negation; + gen8_insn->bits3.da16acc.src1_address_mode = reg.address_mode; + gen8_insn->bits3.da16acc.src1_subreg_nr = reg.subnr / 16; + gen8_insn->bits3.da16acc.src1_reg_nr = reg.nr; + gen8_insn->bits3.da16acc.src1_specal_acc_lo = accN; + gen8_insn->bits3.da16acc.src1_specal_acc_hi = 0; + gen8_insn->bits3.da16acc.src1_vert_stride = reg.vstride; + } + void Gen8Encoder::setSrc0(GenNativeInstruction *insn, GenRegister reg) { Gen8NativeInstruction *gen8_insn = &insn->gen8_insn; if (reg.file != GEN_ARCHITECTURE_REGISTER_FILE) @@ -372,7 +412,7 @@ namespace gbe gen8_insn->bits2.da1.src0_negate = reg.negation; gen8_insn->bits2.da1.src0_address_mode = reg.address_mode; if (reg.file == GEN_IMMEDIATE_VALUE) { - if (reg.type == GEN_TYPE_L || reg.type == GEN_TYPE_UL) { + if (reg.type == GEN_TYPE_L || reg.type == GEN_TYPE_UL || reg.type == GEN_TYPE_DF_IMM) { gen8_insn->bits3.ud = (uint32_t)(reg.value.i64 >> 32); gen8_insn->bits2.ud = (uint32_t)(reg.value.i64); } else { @@ -532,4 +572,23 @@ namespace gbe gen8_insn->bits3.da3src.src2_reg_nr++; } } + + void Gen8Encoder::MATH_WITH_ACC(GenRegister dst, uint32_t function, GenRegister src0, GenRegister src1, + uint32_t dstAcc, uint32_t src0Acc, uint32_t src1Acc) + { + GenNativeInstruction *insn = this->next(GEN_OPCODE_MATH); + Gen8NativeInstruction *gen8_insn = &insn->gen8_insn; + assert(dst.file == GEN_GENERAL_REGISTER_FILE); + assert(src0.file == GEN_GENERAL_REGISTER_FILE); + assert(src1.file == GEN_GENERAL_REGISTER_FILE); + assert(dst.hstride == GEN_HORIZONTAL_STRIDE_1 || dst.hstride == GEN_HORIZONTAL_STRIDE_0); + + gen8_insn->header.access_mode = GEN_ALIGN_16; + insn->header.destreg_or_condmod = function; + this->setHeader(insn); + this->setDst(insn, dst); + gen8_insn->bits1.da16acc.dst_specal_acc = dstAcc; + this->setSrc0WithAcc(insn, src0, src0Acc); + this->setSrc1WithAcc(insn, src1, src1Acc); + } } /* End of the name space. */ diff --git a/backend/src/backend/gen8_encoder.hpp b/backend/src/backend/gen8_encoder.hpp index 504e13d..53ec3d1 100644 --- a/backend/src/backend/gen8_encoder.hpp +++ b/backend/src/backend/gen8_encoder.hpp @@ -69,6 +69,11 @@ namespace gbe virtual unsigned setAtomicMessageDesc(GenNativeInstruction *insn, unsigned function, unsigned bti, unsigned srcNum); virtual unsigned setUntypedReadMessageDesc(GenNativeInstruction *insn, unsigned bti, unsigned elemNum); virtual unsigned setUntypedWriteMessageDesc(GenNativeInstruction *insn, unsigned bti, unsigned elemNum); + void setSrc0WithAcc(GenNativeInstruction *insn, GenRegister reg, uint32_t accN); + void setSrc1WithAcc(GenNativeInstruction *insn, GenRegister reg, uint32_t accN); + + void MATH_WITH_ACC(GenRegister dst, uint32_t function, GenRegister src0, GenRegister src1, + uint32_t dstAcc, uint32_t src0Acc, uint32_t src1Acc); }; } #endif /* __GBE_GEN8_ENCODER_HPP__ */ diff --git a/backend/src/backend/gen_defs.hpp b/backend/src/backend/gen_defs.hpp index 1ca148c..a1bd8dd 100644 --- a/backend/src/backend/gen_defs.hpp +++ b/backend/src/backend/gen_defs.hpp @@ -463,6 +463,17 @@ enum GenMessageTarget { #define GEN_UPDATE_GATEWAT_STATE 0b101 #define GEN_MMIO_READ_WRITE 0b110 +/* Accumulator acc2~acc9 in instruction */ +#define GEN8_INSN_ACC2 0 +#define GEN8_INSN_ACC3 1 +#define GEN8_INSN_ACC4 2 +#define GEN8_INSN_ACC5 3 +#define GEN8_INSN_ACC6 4 +#define GEN8_INSN_ACC7 5 +#define GEN8_INSN_ACC8 6 +#define GEN8_INSN_ACC9 7 +#define GEN8_INSN_NOACC 8 + ///////////////////////////////////////////////////////////////////////////// // Gen EU structures ///////////////////////////////////////////////////////////////////////////// -- 1.9.1 _______________________________________________ Beignet mailing list Beignet@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/beignet