[Bug gas/16109] Incorrect listing (single line comment after multiline one causes line mis-alignment)

2013-11-19 Thread cvs-commit at gcc dot gnu.org
http://sourceware.org/bugzilla/show_bug.cgi?id=16109

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The branch, master has been updated
   via  cf3f45fad7811e89d6b586a1a429a314e3db9f53 (commit)
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- Log -
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=cf3f45fad7811e89d6b586a1a429a314e3db9f53

commit cf3f45fad7811e89d6b586a1a429a314e3db9f53
Author: Alexey Makhalov makhal...@gmail.com
Date:   Tue Nov 19 08:19:21 2013 +

PR gas/16109
* app.c (do_scrub_chars): Only insert a newline character if
end-of-file has been reached.

---

Summary of changes:
 gas/ChangeLog |6 ++
 gas/app.c |   11 +--
 2 files changed, 15 insertions(+), 2 deletions(-)

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[Bug gas/16109] Incorrect listing (single line comment after multiline one causes line mis-alignment)

2013-11-19 Thread nickc at redhat dot com
https://sourceware.org/bugzilla/show_bug.cgi?id=16109

Nick Clifton nickc at redhat dot com changed:

   What|Removed |Added

 CC||nickc at redhat dot com
 Resolution|WORKSFORME  |FIXED

--- Comment #4 from Nick Clifton nickc at redhat dot com ---
Hi Alexey,

  Thanks for the bug report and patch.  Sorry that it took me so long to get
around to reviewing it.  The patch is fine - I have checked it in to the
sources. 

Cheers
  Nick

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[Bug ld/16017] LD creates invalid PLT instructions on CORTEX-M3

2013-11-19 Thread lotharlutz at gmx dot de
https://sourceware.org/bugzilla/show_bug.cgi?id=16017

--- Comment #5 from Markus Mayer lotharlutz at gmx dot de ---
As I don't know what limitations exists for PLT entries I will provide
different solutions.

Base assumptions:
- The IP register must contain the (absolute)address of the GOT entry (I think
it is needed for lazy binding)

- If any register (except the IP register) is modified during the PLT
execution, its state must be restored before the end of the PLT

- All PLT entries must have equal sizes


Solution 1:
1: b401push{r0}
2: f8df 0010   ldr.w   r0, [pc, #16]   ; load GOT index
3: f8df c010   ldr.w   ip, [pc, #16]   ; load (relative) GOT address
4: 4484add ip, r0
5: 44fcadd ip, pc
6: bc01pop {r0}
7: f8dc f000   ldr.w   pc, [ip]
8: ; GOT index
9: ; GOT address relative to instruction in line 5

Pros: capable to handle arbitrary large GOT indexes as well as arbitrary
offsets of the GOT
Cons: 28 Bytes per entry, 3 Load Instructions

Solution 2:
1: f8df c008   ldr.w   ip, [pc, #8]; load (relative)GOT entry address
2: 44fcadd ip, pc
3: f8dc f000   ldr.w   pc, [ip]
4: ; padding to make the address aligned
5: ; (GOT + GOT index) relative to instruction in line 2

Pros: only 16 Bytes per entry
Cons: still 2 load instructions, GOT and GOT index must be combined (is this
possible?)

Solution 3:
1: f04f 0c00   mov.w   ip, #0
2: ea4f 3c0c   mov.w   ip, ip, lsl #12
3: f20f 0c00   addwip, pc, #0
4: f8dc f000   ldr.w   pc, [ip]

The GOT entry address is encoded in line 1 and line 3.
Pro: 16 Bytes per entry, only one load instruction
Con: only offsets up to 24 Bit are possible. (Note this limitation also exists
for the current arm PLT)

I favour solution 3. I will provide code the generate a thumb plt later the
day.

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[Bug ld/16017] LD creates invalid PLT instructions on CORTEX-M3

2013-11-19 Thread lotharlutz at gmx dot de
https://sourceware.org/bugzilla/show_bug.cgi?id=16017

--- Comment #6 from Markus Mayer lotharlutz at gmx dot de ---
Created attachment 7285
  -- https://sourceware.org/bugzilla/attachment.cgi?id=7285action=edit
Patch for thumb plt entries

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[Bug ld/16017] LD creates invalid PLT instructions on CORTEX-M3

2013-11-19 Thread lotharlutz at gmx dot de
https://sourceware.org/bugzilla/show_bug.cgi?id=16017

--- Comment #7 from Markus Mayer lotharlutz at gmx dot de ---
I have attached a patch to create thumb plt entries. 

The patch has some issues:
- The plt entries are using tumb-2 instructions. When on an thumb only thumb-1
device, an error should be emitted.

- The plt0_entry for thumb-only is not converted yet. I will take care of it
the next couple of days

- The size of a plt entry is set the thumb-entry size (which breaks normal arm
linking). The plt size must be set according to whether we are on thumb-only,
or not. I have tried using 'using_thumb_only', but it seams like 'abfd' is not
fully initialized inside 'elf32_arm_link_hash_table_create' to work with
'using_thumb_only'.


Any help and feedback is welcome

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[Bug binutils/16192] New: [PATCH] * ld/pe-dll.c: clear memory after allocating it but before using it.

2013-11-19 Thread erinn at torproject dot org
http://sourceware.org/bugzilla/show_bug.cgi?id=16192

Bug ID: 16192
   Summary: [PATCH] * ld/pe-dll.c: clear memory after allocating
it but before using it.
   Product: binutils
   Version: unspecified
Status: NEW
  Severity: normal
  Priority: P2
 Component: binutils
  Assignee: unassigned at sourceware dot org
  Reporter: erinn at torproject dot org

Created attachment 7286
  -- http://sourceware.org/bugzilla/attachment.cgi?id=7286action=edit
[PATCH] * ld/pe-dll.c: clear memory after allocating it but before using it.

I work for The Tor Project and in the process of working on deterministic
builds of win64 we discovered that there were phantom bytes we couldn't account
for. After researching for a few days, one of our developers found the cause
and I'm attaching a patch for ld in binutils. This patch is a few days old but
should still apply cleanly to master. The text to explain the bug better:

Currently, in pe-dll.c , extern_rt_rel_d is allocated but not cleared before
using it.  This leads (apparently) to uninitialized heap contents leaking into
the generated files, which is a problem for reproducible builds. It appears
that elsewhere in pe-dll.c, the pattern is to clear memory like this after
allocating it but before using it.  That's the approach that this patch takes.

Patch written by bobnomnom.

The fix has been tested in both win64 and win32 in our Gitian infrastructure
and successfully creates reproducible, identical binaries.

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