[Bug binutils/25371] [objcopy] add support for setting SHF_EXCLUDE flag for sections
https://sourceware.org/bugzilla/show_bug.cgi?id=25371 --- Comment #4 from Fangrui Song --- https://sourceware.org/ml/binutils/2020-01/msg00186.html in the spirit of a previous patch by HJ. Lu that makes SHF_EXCLUDE generic rather than processor-specific. -- You are receiving this mail because: You are on the CC list for the bug.
[Bug ld/25389] - -Wl,--wrap -fuse-ld=bfd not supported with LTO
https://sourceware.org/bugzilla/show_bug.cgi?id=25389 H.J. Lu changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|--- |INVALID --- Comment #1 from H.J. Lu --- The testcase is invalid since '--wrap=SYMBOL' Use a wrapper function for SYMBOL. Any undefined reference to SYMBOL will be resolved to '__wrap_SYMBOL'. Any undefined reference to '__real_SYMBOL' will be resolved to SYMBOL. This can be used to provide a wrapper for a system function. The wrapper function should be called '__wrap_SYMBOL'. If it wishes to call the system function, it should call '__real_SYMBOL'. When SYMBOL definition is compiled with LTO, LTO will resolve all SYMBOL references to SYMBOL definition in LTO since LTO doesn't know --wrap. -- You are receiving this mail because: You are on the CC list for the bug.
[Bug gas/25406] New: [ARM] pcrel relocations referencing STB_GLOBAL symbols are resolved at assembly time
https://sourceware.org/bugzilla/show_bug.cgi?id=25406 Bug ID: 25406 Summary: [ARM] pcrel relocations referencing STB_GLOBAL symbols are resolved at assembly time Product: binutils Version: unspecified Status: UNCONFIRMED Severity: normal Priority: P2 Component: gas Assignee: unassigned at sourceware dot org Reporter: i at maskray dot me Target Milestone: --- % cat pcrel-global.s .syntax unified .globl foo foo: ldrd r0, r1, foo @ arm_pcrel_10_unscaled vldr d0, foo @ arm_pcrel_10 adr r2, foo @ arm_adr_pcrel_12 ldr r0, foo @ arm_ldst_pcrel_12 .thumb .thumb_func .globl bar bar: adr r0, bar @ thumb_adr_pcrel_10 adr.w r0, bar@ t2_adr_pcrel_12 ldr.w pc, bar@ t2_ldst_pcrel_12 % arm-linux-gnueabi-as -mfpu=vfp pcrel-global.s -o /tmp/c/a.o % readelf -r /tmp/c/a.o There are no relocations in this file. If the definitions of foo and bar are deleted, each instruction can issue an error. STB_GLOBAL STV_DEFAULT symbols can be preemptible (if in a shared object). Should relocations be emitted? On many other architectures, relocations will be emitted. -- You are receiving this mail because: You are on the CC list for the bug.
[Bug ld/25389] - -Wl,--wrap -fuse-ld=bfd not supported with LTO
https://sourceware.org/bugzilla/show_bug.cgi?id=25389 H.J. Lu changed: What|Removed |Added Depends on||24406 Referenced Bugs: https://sourceware.org/bugzilla/show_bug.cgi?id=24406 [Bug 24406] -Wl,--wrap= incompatible with -flto -- You are receiving this mail because: You are on the CC list for the bug.
[Bug ld/24406] -Wl,--wrap= incompatible with -flto
https://sourceware.org/bugzilla/show_bug.cgi?id=24406 H.J. Lu changed: What|Removed |Added Blocks||25389 Referenced Bugs: https://sourceware.org/bugzilla/show_bug.cgi?id=25389 [Bug 25389] - -Wl,--wrap -fuse-ld=bfd not supported with LTO -- You are receiving this mail because: You are on the CC list for the bug.
[Bug ld/24753] [2.33 Regression] ld: section size (0x1e50 bytes) is larger than file size (0x5a0 bytes), can not size stub section: memory exhausted
https://sourceware.org/bugzilla/show_bug.cgi?id=24753
--- Comment #15 from cvs-commit at gcc dot gnu.org ---
The binutils-2_33-branch branch has been updated by Tamar Christina
:
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=69a29b6e0642a98df15e65c0d5acfcb9c9cad2cb
commit 69a29b6e0642a98df15e65c0d5acfcb9c9cad2cb
Author: Tamar Christina
Date: Thu Jan 2 14:06:01 2020 +
AArch64: Revert SEC_LINKER_CREATED for AArch64 stubs (PR/25210)
The SEC_LINKER_CREATED flag was added as a fix for PR 24753. I believe
that
part of the fix in compress.c to still be correct as linker created
sections
don't have a size on disk and it fixes the Arm bootstrap regression.
So I'm partially revert this change so that we don't have to manage the
section
manually as implied by SEC_LINKER_CREATED as it's causing an error when
both
errata workarounds are used together and it wasn't needed. This can also
be
seen from that the arm bootstrap was fixed and no flag was added to it's
stubs.
ld/ChangeLog:
PR 25210
PR 24753
* emultempl/aarch64elf.em (elf${ELFSIZE}_aarch64_add_stub_section):
Remove SEC_LINKER_CREATED.
* testsuite/ld-aarch64/aarch64-elf.exp: Add erratum835769-843419.
* testsuite/ld-aarch64/erratum835769-843419.d: New test.
(cherry picked from commit 0db131fb835e4c4f6a024e86743467e7e01c965e)
Signed-off-by: Tamar Christina
--
You are receiving this mail because:
You are on the CC list for the bug.
[Bug ld/25210] aarch64: -fix-cortex-a53-835769 --fix-cortex-a53-843419 lead to invalid operation
https://sourceware.org/bugzilla/show_bug.cgi?id=25210
--- Comment #6 from cvs-commit at gcc dot gnu.org ---
The binutils-2_33-branch branch has been updated by Tamar Christina
:
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=69a29b6e0642a98df15e65c0d5acfcb9c9cad2cb
commit 69a29b6e0642a98df15e65c0d5acfcb9c9cad2cb
Author: Tamar Christina
Date: Thu Jan 2 14:06:01 2020 +
AArch64: Revert SEC_LINKER_CREATED for AArch64 stubs (PR/25210)
The SEC_LINKER_CREATED flag was added as a fix for PR 24753. I believe
that
part of the fix in compress.c to still be correct as linker created
sections
don't have a size on disk and it fixes the Arm bootstrap regression.
So I'm partially revert this change so that we don't have to manage the
section
manually as implied by SEC_LINKER_CREATED as it's causing an error when
both
errata workarounds are used together and it wasn't needed. This can also
be
seen from that the arm bootstrap was fixed and no flag was added to it's
stubs.
ld/ChangeLog:
PR 25210
PR 24753
* emultempl/aarch64elf.em (elf${ELFSIZE}_aarch64_add_stub_section):
Remove SEC_LINKER_CREATED.
* testsuite/ld-aarch64/aarch64-elf.exp: Add erratum835769-843419.
* testsuite/ld-aarch64/erratum835769-843419.d: New test.
(cherry picked from commit 0db131fb835e4c4f6a024e86743467e7e01c965e)
Signed-off-by: Tamar Christina
--
You are receiving this mail because:
You are on the CC list for the bug.
[Bug binutils/25403] New: [AArch64, ARMv8.4] objdump doesn't disassemble cfinv correctly
https://sourceware.org/bugzilla/show_bug.cgi?id=25403 Bug ID: 25403 Summary: [AArch64, ARMv8.4] objdump doesn't disassemble cfinv correctly Product: binutils Version: 2.34 (HEAD) Status: UNCONFIRMED Severity: minor Priority: P2 Component: binutils Assignee: unassigned at sourceware dot org Reporter: james.boyle at arm dot com Target Milestone: --- cfinv (opcode 0xd500401f) for flag manipulation instruction (from ARMv8.4 extension) decodes incorrectly as: msr s0_0_c4_c0_0, xzr It should decode as: cfinv I used: $ echo "cfinv" | aarch64-none-linux-gnu-as -march=armv8.4-a Which assembles ok. Then running: $ ./objdump -D a.out: file format elf64-littleaarch64 Disassembly of section .text: <.text>: 0: d500401fmsr s0_0_c4_c0_0, xzr It looks like in commit e9dbdd80cb02ac66cf7d4cd1207ec11928db2c95 (Thu, 16 Nov 2017) a change was made to support this along with other flag manipulation instructions, but cfinv disassembly seems to have been broken from the outset. Looking at test gas/testsuite/gas/aarch64/armv8_4-a.d it never appeared. I think the other v8.4 flag manipulation instructions are disassembling correctly. -- You are receiving this mail because: You are on the CC list for the bug.
[Bug ld/20694] PDP11 TARGET_PAGE_SIZE is incorrect
https://sourceware.org/bugzilla/show_bug.cgi?id=20694 --- Comment #6 from Stephen Casner --- Thanks for making this fix. I can’t do any testing immediately but will do so in a couple of weeks. -- You are receiving this mail because: You are on the CC list for the bug.
[Bug gas/25376] Setting FPU reset's MVE feature bits but FPU can't set MVE feature bits
https://sourceware.org/bugzilla/show_bug.cgi?id=25376 --- Comment #1 from cvs-commit at gcc dot gnu.org --- The master branch has been updated by Andre Simoes Dias Vieira : https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=2da2eaf4ce299c84c5a1f1bc6f7944266cb36d6e commit 2da2eaf4ce299c84c5a1f1bc6f7944266cb36d6e Author: Andre Vieira Date: Thu Jan 16 13:50:52 2020 + [binutils][arm] PR25376 Change MVE into a CORE_HIGH feature This patch moves MVE feature bits into the CORE_HIGH section. This makes sure .fpu and -mfpu does not reset the bits set by MVE. This is important because .fpu has no option to "set" these same bits and thus, mimic'ing GCC, we choose to define MVE as an architecture extension rather than put it together with other the legacy fpu features. This will enable the following behavior: .arch armv8.1-m.main .arch mve .fpu fpv5-sp-d16 #does not disable mve. vadd.i32 q0, q1, q2 This patch also makes sure MVE is not taken into account during auto-detect. This was already the case, but because we moved the MVE bits to the architecture feature space we must make sure ARM_ANY does not include MVE. gas/ChangeLog: 2020-01-16 Andre Vieira PR 25376 * config/tc-arm.c (mve_ext, mve_fp_ext): Use CORE_HIGH. (armv8_1m_main_ext_table): Use CORE_HIGH for mve. * testsuite/arm/armv8_1-m-fpu-mve-1.s: New. * testsuite/arm/armv8_1-m-fpu-mve-1.d: New. * testsuite/arm/armv8_1-m-fpu-mve-2.s: New. * testsuite/arm/armv8_1-m-fpu-mve-2.d: New. include/ChangeLog: 2020-01-16 Andre Vieira PR 25376 * opcodes/arm.h (FPU_MVE, FPU_MVE_FPU): Move these features to... (ARM_EXT2_MVE, ARM_EXT2_MVE_FP): ... the CORE_HIGH space. (ARM_ANY): Redefine to not include any MVE bits. (ARM_FEATURE_ALL): Removed. opcodes/ChangeLog: 2020-01-16 Andre Vieira PR 25376 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits. (neon_opcodes): Likewise. (select_arm_features): Make sure we enable MVE bits when selecting armv8.1-m.main. Make sure we do not enable MVE bits when not selecting any architecture. -- You are receiving this mail because: You are on the CC list for the bug.
