[Bug gas/27436] RISC-V inconsistent handling of rv32 shift with count > 31
https://sourceware.org/bugzilla/show_bug.cgi?id=27436 Nelson Chu changed: What|Removed |Added Resolution|--- |FIXED CC||nelsonc1225 at sourceware dot org Status|NEW |RESOLVED --- Comment #3 from Nelson Chu --- Now I can have the expected results by using mainline binutils, nelson@LAPTOP-QFSGI1F2:~$ riscv32-unknown-elf-as -march=rv64g tmp.s nelson@LAPTOP-QFSGI1F2:~$ riscv32-unknown-elf-as -march=rv64gc tmp.s nelson@LAPTOP-QFSGI1F2:~$ riscv32-unknown-elf-as -march=rv32g tmp.s tmp.s: Assembler messages: tmp.s:1: Error: improper shift amount (63) nelson@LAPTOP-QFSGI1F2:~$ riscv32-unknown-elf-as -march=rv32gc tmp.s tmp.s: Assembler messages: tmp.s:1: Error: improper shift amount (63) I convert the immediate to unsigned long first, and then only check if it is invalid when the value >= xlen. This is the same as the checking of operand '>'. Marked as Resolved and Fixed. If the above behavior has risk, then we can reopen the PR and use another way to fix it. Thanks -- You are receiving this mail because: You are on the CC list for the bug.
[Bug gas/27436] RISC-V inconsistent handling of rv32 shift with count > 31
https://sourceware.org/bugzilla/show_bug.cgi?id=27436 --- Comment #2 from cvs-commit at gcc dot gnu.org --- The master branch has been updated by Nelson Chu : https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=768589d18042a55f0e1f77f466568a1c102ab099 commit 768589d18042a55f0e1f77f466568a1c102ab099 Author: Nelson Chu Date: Fri Apr 16 14:50:32 2021 +0800 RISC-V: PR27436, make operand C> work the same as >. gas/ PR 27436 * config/tc-riscv.c (riscv_ip): make operand C> work the same as >. * testsuite/gas/riscv/shamt-32.d: New testcase. * testsuite/gas/riscv/shamt-32.l: Likewise. * testsuite/gas/riscv/shamt-32.s: Likewise. * testsuite/gas/riscv/shamt-64.d: Likewise. * testsuite/gas/riscv/shamt-64.l: Likewise. * testsuite/gas/riscv/shamt-64.s: Likewise. -- You are receiving this mail because: You are on the CC list for the bug.
[Bug gas/27436] RISC-V inconsistent handling of rv32 shift with count > 31
https://sourceware.org/bugzilla/show_bug.cgi?id=27436 --- Comment #1 from Jim Wilson --- that should be > 31 not > 32 -- You are receiving this mail because: You are on the CC list for the bug.
[Bug gas/27436] RISC-V inconsistent handling of rv32 shift with count > 31
https://sourceware.org/bugzilla/show_bug.cgi?id=27436 Jim Wilson changed: What|Removed |Added Summary|RISC-V inconsistent |RISC-V inconsistent |handling of rv32 shift with |handling of rv32 shift with |count > 32 |count > 31 -- You are receiving this mail because: You are on the CC list for the bug.
