[Bug ld/16017] LD creates invalid PLT instructions on CORTEX-M3
http://sourceware.org/bugzilla/show_bug.cgi?id=16017 --- Comment #1 from cvs-commit at gcc dot gnu.org --- This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "gdb and binutils". The branch, master has been updated via 57460bcf82df9e5e335be84ecc9bdef33dddc934 (commit) from c7e8af9b3bc0881c59c999d7b78348d359383efe (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log - https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=57460bcf82df9e5e335be84ecc9bdef33dddc934 commit 57460bcf82df9e5e335be84ecc9bdef33dddc934 Author: Nick Clifton Date: Thu Nov 14 15:39:51 2013 + PR ld/16017 * elf32-arm.c (elf32_arm_populate_plt_entry): Return a boolean value, TRUE for success, FALSE for failure. Fail if attempting to create a PLT entry for a thumb only target. (elf32_arm_final_link_relocate): Check result of calling elf32_arm_populate_plt_entry. (elf32_arm_finish_dynamic_symbol): Likewise. --- Summary of changes: bfd/ChangeLog | 10 ++ bfd/elf32-arm.c | 31 --- 2 files changed, 34 insertions(+), 7 deletions(-) -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug ld/16017] LD creates invalid PLT instructions on CORTEX-M3
https://sourceware.org/bugzilla/show_bug.cgi?id=16017 Nick Clifton changed: What|Removed |Added Status|NEW |ASSIGNED CC||nickc at redhat dot com --- Comment #2 from Nick Clifton --- Hi Markus, I do not have a solution for this problem, but I have checked in a patch to make the linker fail, with a suitable error message if an attempt is made to generate a PLT entry for a thumb-only processor. Cheers Nick -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug ld/16017] LD creates invalid PLT instructions on CORTEX-M3
https://sourceware.org/bugzilla/show_bug.cgi?id=16017 --- Comment #3 from Markus Mayer --- Hi Nick, thanks for your reply. I have tried to fix it myself, but I am not familiar enough with the code base. Is there anything I can do to help with this issue? e.g. providing assembler code for plt entries. -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug ld/16017] LD creates invalid PLT instructions on CORTEX-M3
http://sourceware.org/bugzilla/show_bug.cgi?id=16017 --- Comment #4 from Nick Clifton --- Hi Markus, > Is there anything I can do to help with this issue? e.g. providing assembler > code for plt entries. Yes please - that would help a lot. Cheers Nick -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug ld/16017] LD creates invalid PLT instructions on CORTEX-M3
https://sourceware.org/bugzilla/show_bug.cgi?id=16017
--- Comment #5 from Markus Mayer ---
As I don't know what limitations exists for PLT entries I will provide
different solutions.
Base assumptions:
- The IP register must contain the (absolute)address of the GOT entry (I think
it is needed for lazy binding)
- If any register (except the IP register) is modified during the PLT
execution, its state must be restored before the end of the PLT
- All PLT entries must have equal sizes
Solution 1:
1: b401push{r0}
2: f8df 0010 ldr.w r0, [pc, #16] ; load GOT index
3: f8df c010 ldr.w ip, [pc, #16] ; load (relative) GOT address
4: 4484add ip, r0
5: 44fcadd ip, pc
6: bc01pop {r0}
7: f8dc f000 ldr.w pc, [ip]
8: ; GOT index
9: ; GOT address relative to instruction in line 5
Pros: capable to handle arbitrary large GOT indexes as well as arbitrary
offsets of the GOT
Cons: 28 Bytes per entry, 3 Load Instructions
Solution 2:
1: f8df c008 ldr.w ip, [pc, #8]; load (relative)GOT entry address
2: 44fcadd ip, pc
3: f8dc f000 ldr.w pc, [ip]
4: ; padding to make the address aligned
5: ; (GOT + GOT index) relative to instruction in line 2
Pros: only 16 Bytes per entry
Cons: still 2 load instructions, GOT and GOT index must be combined (is this
possible?)
Solution 3:
1: f04f 0c00 mov.w ip, #0
2: ea4f 3c0c mov.w ip, ip, lsl #12
3: f20f 0c00 addwip, pc, #0
4: f8dc f000 ldr.w pc, [ip]
The GOT entry address is encoded in line 1 and line 3.
Pro: 16 Bytes per entry, only one load instruction
Con: only offsets up to 24 Bit are possible. (Note this limitation also exists
for the current arm PLT)
I favour solution 3. I will provide code the generate a thumb plt later the
day.
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[Bug ld/16017] LD creates invalid PLT instructions on CORTEX-M3
https://sourceware.org/bugzilla/show_bug.cgi?id=16017 --- Comment #6 from Markus Mayer --- Created attachment 7285 --> https://sourceware.org/bugzilla/attachment.cgi?id=7285&action=edit Patch for thumb plt entries -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug ld/16017] LD creates invalid PLT instructions on CORTEX-M3
https://sourceware.org/bugzilla/show_bug.cgi?id=16017 --- Comment #7 from Markus Mayer --- I have attached a patch to create thumb plt entries. The patch has some issues: - The plt entries are using tumb-2 instructions. When on an thumb only thumb-1 device, an error should be emitted. - The plt0_entry for thumb-only is not converted yet. I will take care of it the next couple of days - The size of a plt entry is set the thumb-entry size (which breaks normal arm linking). The plt size must be set according to whether we are on thumb-only, or not. I have tried using 'using_thumb_only', but it seams like 'abfd' is not fully initialized inside 'elf32_arm_link_hash_table_create' to work with 'using_thumb_only'. Any help and feedback is welcome -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug ld/16017] LD creates invalid PLT instructions on CORTEX-M3
https://sourceware.org/bugzilla/show_bug.cgi?id=16017 Nick Clifton changed: What|Removed |Added Status|ASSIGNED|WAITING --- Comment #8 from Nick Clifton --- Hi Markus, > The size of a plt entry is set the thumb-entry size (which breaks > normal arm linking). Have you tried setting the entry size in elf32_arm_create_dynamic_sections() ? > The plt entries are using tumb-2 instructions. When on an thumb only > thumb-1 device, an error should be emitted. You can use "! using_thumb2()" for this. The patch itself looks good so far... Cheers Nick -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug ld/16017] LD creates invalid PLT instructions on CORTEX-M3
https://sourceware.org/bugzilla/show_bug.cgi?id=16017 Markus Mayer changed: What|Removed |Added Attachment #7285|0 |1 is obsolete|| --- Comment #9 from Markus Mayer --- Created attachment 7291 --> https://sourceware.org/bugzilla/attachment.cgi?id=7291&action=edit [Rev2] Patch for thumb plt entries -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug ld/16017] LD creates invalid PLT instructions on CORTEX-M3
https://sourceware.org/bugzilla/show_bug.cgi?id=16017 --- Comment #10 from Markus Mayer --- Hi Nick, I have attached a new version of my previous patch. Changes: - convert pl0 to thumb - Show error when using thumb-1 thumb-only targets - Rename 'elf32_thumb_plt_entry' to 'elf32_thumb2_plt_entry' - Set 'plt_entry_size' inside 'elf32_arm_create_dynamic_sections' - Move 'using_thumb_only' and 'using_thumb2' upwards, to make it available inside 'elf32_arm_create_dynamic_sections' Open issues: - 'plt_entry_size' is still set incorrectly. 'using_thumb_only' return false inside 'elf32_arm_create_dynamic_sections' - When calling the plt entry from the .text segment a 'BLX ' instruction is used. This instruction is not available in thumb mode. 'BL ' must be used here. Can you help me out with these issues? Regards Markus -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug ld/16017] LD creates invalid PLT instructions on CORTEX-M3
https://sourceware.org/bugzilla/show_bug.cgi?id=16017 Markus Mayer changed: What|Removed |Added CC||lotharlutz at gmx dot de -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug ld/16017] LD creates invalid PLT instructions on CORTEX-M3
https://sourceware.org/bugzilla/show_bug.cgi?id=16017 --- Comment #11 from Nick Clifton --- Created attachment 7314 --> https://sourceware.org/bugzilla/attachment.cgi?id=7314&action=edit 3rd version of patch Hi Markus, [Sorry for the delay in responding - I have been sidetracked by other tasks]. Re: Detecting thumb_only inside create_dynamic_sections(). You are right - the normal function does not work. This is because at the time that create_dynamic_sections is called the attributes have not been copied from the input bfd to the output bfd. But... the attributes are still present in the input bfd, so you can test those. Re: Not converting BL into BLX - these was some code in final_link_relocate that assumed that PLT entries would always be in ARM mode, and so a BLX would always be needed. I have uploaded a revised version of your v2 patch with fixes for both of these problems. Please try it out and let me know if it works for you. Cheers Nick -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug ld/16017] LD creates invalid PLT instructions on CORTEX-M3
https://sourceware.org/bugzilla/show_bug.cgi?id=16017 Markus Mayer changed: What|Removed |Added Status|WAITING |SUSPENDED --- Comment #12 from Markus Mayer --- Hi Nick, I've applied your patch and check the disassembly of a create test library. As far as I can tell it looks correct. I haven't tested it on a real system, because my thumb-only system isn't available till late January. If there are any problems left, it's like an error in the plt-code (which I can fix myself). I will report my hardware test results as soon as there are available. Regards Markus -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug ld/16017] LD creates invalid PLT instructions on CORTEX-M3
http://sourceware.org/bugzilla/show_bug.cgi?id=16017 --- Comment #13 from cvs-commit at gcc dot gnu.org --- This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "gdb and binutils". The annotated tag, hjl/linux/release/2.24.51.0.2 has been created at bc64dc5b95aa848d7274e4648d667b9b1065d88c (tag) tagging bbd7f545f1639be4573ba06ed688b8db670d4597 (commit) replaces hjl/linux/release/2.24.51.0.1 tagged by H.J. Lu on Fri Dec 13 08:44:03 2013 -0800 - Log - Linux binutils 2.24.51.0.2 Alan Modra (47): daily update daily update daily update daily update daily update Correct elf64-ppc.c handling of protected symbols PowerPC64 ELFv2, allocate dynreloc space for ifunc daily update daily update daily update daily update PowerPC64 ELFv2 trampoline match Fixes to powerpc64 gold ELFv2 support Add missing ChangeLog for 88b8e63904fda25c029deaf25d7b4e489b351470 daily update daily update daily update daily update daily update daily update daily update Import config.sub and config.guess from upstream. daily update daily update daily update daily update daily update daily update daily update daily update daily update daily update daily update PowerPC64 linking of --just-symbols objects (klibc) More PowerPC64 ELFv2 --just-symbols fixes daily update daily update daily update daily update daily update Fix --as-needed undefined symbol references from dynamic libraries. correct file reference daily update daily update daily update daily update daily update Alexey Makhalov (1): PR gas/16109 Andreas Arnez (3): S390: Fix TDB regset recognition Fix GDB crash with upstream GCC due to qsort(NULL, ...) Fix GDB crash with upstream GCC due to memcpy(NULL, ...) Andrew Burgess (6): Mark entirely optimized out value as non-lazy. Tighten regexp in gdb.base/setshow.exp Make "set debug frame 1" use the standard print routine for optimized out values. Print entirely unavailable struct/union values as a single . Add support for DW_OP_bit_piece and DW_OP_plus_uconst to DWARF assembler. Add call to get_compiler_info to gdb_compile_shlib. Andrew Pinski (2): ld/ChangeLog: ld/ChangeLog: Anthony Green (1): Add software single step support to moxie port Cary Coutant (6): Fix assert failure with --emit-relocs and .eh_frame sections. Fix race condition while building EH frame header. Add --verify-only option to DWP. Revert "Fix race condition while building EH frame header." Use in-tree assembler for exception_x86_64_bnd_test. Add check for which library is needed for dlopen. Catherine Moore (4): 2013-11-11 Catherine Moore Fix ChangeLog entries from earlier commit. 2013-11-19 Catherine Moore 2013-11-19 Catherine Moore Chung-Lin Tang (1): Separate emulations for nios2-elf and nios2-linux. Conrad Hoffmann (1): * gprof.c (inline_file_names): New variable. Cory Fields (1): * windres.c (define_resource): Use zero for timestamp, making Doug Evans (42): * gdb.python/py-arch.exp: Tweak test name for bad memory access test. Add pretty-printing of .debug_gnu_pubnames, .debug_gnu_pubtypes. PR 11786 Fix email address in earlier entry. Change "set debug symtab-create" to take a verbosity level. Change "set debug dwarf2-read" to take a verbosity level. * gdb.arch/arm-bl-branch-dest.exp: Use gdb_test_file_name instead Work around gold/15646. * gdb.base/fileio.exp: Make $dir2 writable after the test is done * breakpoint.c (bpstat_check_breakpoint_conditions): Assert fix email address in earlier commit * breakpoint.c (breakpoint_cond_eval): Fix and enhance comment. * breakpoint.c (bpstat_check_breakpoint_conditions): For thread * gdb.python/py-breakpoint.exp: Split up into several functions, * gdb.python/py-breakpoint.exp: Reformat for 80 columns. * gdb.python/py-breakpoint.exp: Make tests have unique names. * linux-low.c (resume_status_pending_p): Tweak comment. * linux-low.c (linux_set_resume_request): Fix comment. Move types_deeply_equal from py-type.c to gdbtypes.c. cli/cli-script.c (multi_line_command_p): New function. * python/py-frame.c (frapy_block): Fix error message text. * python/py-frame.c (gdbpy_initialize_frames): Remove FIRST_ERROR, * gdb.python/python.exp: Don't call skip_python_tests, we still want Fix long line in earlier entry. * gdb.python/py-symbol.exp: Fix white
[Bug ld/16017] LD creates invalid PLT instructions on CORTEX-M3
https://sourceware.org/bugzilla/show_bug.cgi?id=16017 Meador Inge changed: What|Removed |Added CC||meadori at codesourcery dot com --- Comment #14 from Meador Inge --- I have a need for these patches as well. While testing them, we noticed that the current PLT stubs have a bug: 0x0c00f240,/* movwip, #0x*/ 0x3c0cea4f,/* lsl ip, #12*/ 0x0c00f20f,/* addwip, pc, #0xNNN */ 0xf000f8dc,/* ldr pc, [ip] */ The third instructions clobbers 'ip'. Thus for non-zero 'ip' values this will not work. -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug ld/16017] LD creates invalid PLT instructions on CORTEX-M3
https://sourceware.org/bugzilla/show_bug.cgi?id=16017
Irfan Ahmad changed:
What|Removed |Added
CC||h.IrfanAhmad at gmail dot com
--- Comment #15 from Irfan Ahmad ---
One problem in coming up with a compact PLT, in present case, is that PC is not
allowed to be a source operand in ADD (and OR) instructions that take register
parameters (e.g. - add ip, pc - is illegal). So an intermediate register is
needed. I suggest the following variant:
1: b401push{r0}
2: f20f addwr0, pc, #0
3: f240 0c00 movwip, #0x ; Lower 16 bits of GOT entry offset from
PC
4: f2c0 0c00 movtip, #0x ; Upper 16 bits of GOT entry offset from
PC
5: 4484add ip, r0
6: bc01pop {r0}
7: f8dc f000 ldr.w pc, [ip]
This comes to 22 bytes but has the plus side that 32-bit offsets can be handled
allowing GOT to be anywhere in the 32-bit address space.
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[Bug ld/16017] LD creates invalid PLT instructions on CORTEX-M3
https://sourceware.org/bugzilla/show_bug.cgi?id=16017
--- Comment #16 from Markus Mayer ---
Will thinking about it, I came to the following conclusion (only line 2
differs). It safes 2 byte.
1: push{r0}
2: mov r0, pc
3: movwip, #0x ; Lower 16 bits of GOT entry offset from PC
4: movtip, #0x ; Upper 16 bits of GOT entry offset from PC
5: add ip, r0
6: pop {r0}
7: ldr.w pc, [ip]
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[Bug ld/16017] LD creates invalid PLT instructions on CORTEX-M3
https://sourceware.org/bugzilla/show_bug.cgi?id=16017 --- Comment #17 from Irfan Ahmad --- I missed an && in the ARM reference manual, :( addip, pc Should be legal addw ip, pc, #0 is not. So we can rework my suggestion to: 1: f240 0c00 movwip, #0x ; Lower 16 bits of GOT entry offset 2: f2c0 0c00 movtip, #0x ; Upper 16 bits of GOT entry offset 3: 44fcadd ip, pc 4: f8dc f000 ldr.w pc, [ip] This will result in the same size as in the Solution 3 by Markus. -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug ld/16017] LD creates invalid PLT instructions on CORTEX-M3
https://sourceware.org/bugzilla/show_bug.cgi?id=16017 --- Comment #18 from Meador Inge --- Right, my reading of the ARM manuals suggest that with 'ADD , ' (T2 encoding) that Rm can be PC. Only things like 'ADD PC, Rm' and 'ADD PC, PC' are unpredictable. I came up with a similar encoding: 0:f240 0c00 movwip, #0 4:f2c0 0c00 movtip, #0 8:44fc addip, pc a:f8dc f000 ldr.wpc, [ip] e:bf00 nop We might need the nop to group things into a multiple of 4. -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug ld/16017] LD creates invalid PLT instructions on CORTEX-M3
https://sourceware.org/bugzilla/show_bug.cgi?id=16017 Nick Clifton changed: What|Removed |Added Attachment #7291|0 |1 is obsolete|| Attachment #7314|0 |1 is obsolete|| --- Comment #19 from Nick Clifton --- Created attachment 7414 --> https://sourceware.org/bugzilla/attachment.cgi?id=7414&action=edit v4 of patch, now with added mapping symbols Hi Guys, I have uploaded a revised version of the patch containing the fixed PLT entry code. If someone can confirm that this works I will be happy to check it in. Note - this version of the patch also adds in setting the mapping symbols correctly so that the .plt section can be disassembled correctly. Cheers Nick -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug ld/16017] LD creates invalid PLT instructions on CORTEX-M3
https://sourceware.org/bugzilla/show_bug.cgi?id=16017 --- Comment #20 from Meador Inge --- Hi Nick, Thanks for the update. A few questions/observations: 1. I think the third mask on 'elf32_thumb2_plt_entry[1]' when applying the constants should be '0x0800' instead of '0x08000800'. 2. Why do we limit the offset to 24 bits? It seems the encoding allows for a full 32 bits, e.g. a fourth line that does: | ((got_displacement & 0xf000) >> 28) I understand why the 'elf32_arm_plt_entry' has this limitation. -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug ld/16017] LD creates invalid PLT instructions on CORTEX-M3
https://sourceware.org/bugzilla/show_bug.cgi?id=16017 Nick Clifton changed: What|Removed |Added Attachment #7414|0 |1 is obsolete|| --- Comment #21 from Nick Clifton --- Created attachment 7415 --> https://sourceware.org/bugzilla/attachment.cgi?id=7415&action=edit Fix typo. Extend supported GOT offsets to 32-bits Hi Meadori, Ooops - you are right. The mask was a typo, and the lack of full 32-bit GOT offset support was just plain laziness. Please try out this revised version instead. Cheers Nick -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug ld/16017] LD creates invalid PLT instructions on CORTEX-M3
https://sourceware.org/bugzilla/show_bug.cgi?id=16017 --- Comment #22 from Meador Inge --- Hi Nick, I just noticed that the mask for 'elf32_thumb2_plt_entry[0]' has the same typo, but the upper 8 needs to be removed instead. I had to squint to see it :-) Also, we should remove the 'BFD_ASSERT ((got_displacement & 0xf000) == 0)' assert now that 32-bit support is there. Other than that, looks good to me! -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug ld/16017] LD creates invalid PLT instructions on CORTEX-M3
https://sourceware.org/bugzilla/show_bug.cgi?id=16017 Nick Clifton changed: What|Removed |Added Attachment #7415|0 |1 is obsolete|| --- Comment #23 from Nick Clifton --- Created attachment 7416 --> https://sourceware.org/bugzilla/attachment.cgi?id=7416&action=edit Fix another typo; remove assert Hi Meadori, Thanks again for checking the patch. I have uploaded another version. This time it will work and no-one will have to be nailed to anything. (Sorry - old quote...) Cheers Nick -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug ld/16017] LD creates invalid PLT instructions on CORTEX-M3
https://sourceware.org/bugzilla/show_bug.cgi?id=16017 --- Comment #24 from Meador Inge --- Thanks Nick! The last version looks good. We will try some runtime testing on it. -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug ld/16017] LD creates invalid PLT instructions on CORTEX-M3
https://sourceware.org/bugzilla/show_bug.cgi?id=16017 --- Comment #25 from Meador Inge --- Hi Nick, The runtime testing we did with this patch worked for our use cases. Thanks again. -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug ld/16017] LD creates invalid PLT instructions on CORTEX-M3
https://sourceware.org/bugzilla/show_bug.cgi?id=16017 --- Comment #26 from cvs-commit at gcc dot gnu.org --- This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "gdb and binutils". The branch, master has been updated via eed94f8f8eddbd2268fc317508044bedc81a4e70 (commit) from 1a8a700e3a6fd88bcd5b3988a1f738da463f5b1b (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log - https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=eed94f8f8eddbd2268fc317508044bedc81a4e70 commit eed94f8f8eddbd2268fc317508044bedc81a4e70 Author: Nick Clifton Date: Tue Mar 4 15:25:53 2014 + Install patch for PR ld/16017. This adds support for generating PLT entries using Thumb2 instructions for those cores which do not support the ARM ISA. * elf32-arm.c (elf32_thumb2_plt0_entry): New array. (elf32_thumb2_plt_entry): New array. (elf32_arm_create_dynamic_sections): Set PLT entry sizes when using thumb2 based PLT. (elf32_arm_populate_plt_entry): Handle generating Thumb2 based PLT entries. (elf32_arm_final_link_relocate): Do not bias jumps to Thumb based PLT entries. (elf32_arm_finish_dynamic_sections): Handle creation of Thumb2 based PLT 0-entry. (elf32_arm_output_plt_map_1): Handle creation of local symbols for Thumb2 based PLT 0-entry. (elf32_arm_output_arch_local_syms): Handle creation of local symbols for Thumb2 based PLT entries. --- Summary of changes: bfd/ChangeLog | 18 + bfd/elf32-arm.c | 188 ++ 2 files changed, 164 insertions(+), 42 deletions(-) -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug ld/16017] LD creates invalid PLT instructions on CORTEX-M3
https://sourceware.org/bugzilla/show_bug.cgi?id=16017 Nick Clifton changed: What|Removed |Added Status|SUSPENDED |RESOLVED Resolution|--- |FIXED --- Comment #27 from Nick Clifton --- I have checked in the final version of the patch. -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug ld/16017] LD creates invalid PLT instructions on CORTEX-M3
https://sourceware.org/bugzilla/show_bug.cgi?id=16017 Tamar Christina changed: What|Removed |Added Resolution|FIXED |--- Status|RESOLVED|REOPENED CC||tnfchris at sourceware dot org --- Comment #28 from Tamar Christina --- Looks like the initial GOT entries pointing to PLT0 are missing Thumb bit being set. The current version will transition out of Thumb mode and crash. -- You are receiving this mail because: You are on the CC list for the bug.
[Bug ld/16017] LD creates invalid PLT instructions on CORTEX-M3
https://sourceware.org/bugzilla/show_bug.cgi?id=16017 Tamar Christina changed: What|Removed |Added Target Milestone|--- |2.34 Assignee|unassigned at sourceware dot org |tnfchris at sourceware dot org -- You are receiving this mail because: You are on the CC list for the bug.
[Bug ld/16017] LD creates invalid PLT instructions on CORTEX-M3
https://sourceware.org/bugzilla/show_bug.cgi?id=16017
--- Comment #29 from cvs-commit at gcc dot gnu.org ---
The master branch has been updated by Tamar Christina
:
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=a7618269b727da9cf56727c22cb538ff5f0e4d25
commit a7618269b727da9cf56727c22cb538ff5f0e4d25
Author: Tamar Christina
Date: Wed Apr 1 10:47:18 2020 +0100
Arm: Fix LSB of GOT for Thumb2 only PLT.
When you have a Thumb only PLT then the address in the GOT for PLT0 needs
to
have the Thumb bit set since the instruction used in PLTn to get there is
`ldr.w pc` which is an inter-working instruction:
the PLT sequence in question is
0120 :
120: f240 0c98 movwip, #152; 0x98
124: f2c0 0c01 movtip, #1
128: 44fcadd ip, pc
12a: f8dc f000 ldr.w pc, [ip]
12e: e7fcb.n 12a
Disassembly of section .text:
0130 :
130: b580push{r7, lr}
132: af00add r7, sp, #0
134: f7ff fff4 bl 120
and previously the linker would generate
Hex dump of section '.got':
...
0x000101b8 40010100 1001 @...
Which would make it jump and transition out of thumb mode and crash since
you
only have thumb mode on such cores.
Now it correctly generates
Hex dump of section '.got':
...
0x000101b8 40010100 1101 @...
Thanks to Amol for testing patch and to rgujju for reporting it.
bfd/ChangeLog:
PR ld/16017
* elf32-arm.c (elf32_arm_populate_plt_entry): Set LSB of the PLT0
address in the GOT if in thumb only mode.
ld/ChangeLog:
PR ld/16017
* testsuite/ld-arm/arm-elf.exp (thumb-plt-got): New.
* testsuite/ld-arm/thumb-plt-got.d: New test.
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[Bug ld/16017] LD creates invalid PLT instructions on CORTEX-M3
https://sourceware.org/bugzilla/show_bug.cgi?id=16017 --- Comment #30 from cvs-commit at gcc dot gnu.org --- The master branch has been updated by Tamar Christina : https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=3ce23ca1de4c769c4b7247f0724a10ef5fb24a11 commit 3ce23ca1de4c769c4b7247f0724a10ef5fb24a11 Author: Tamar Christina Date: Wed Apr 1 18:31:22 2020 +0100 Arm: Skip Thumb2 PLT tests on NaCL. NaCL does not support dynamic linking and so these tests should be skipped under it. ld/ChangeLog: PR ld/16017 * testsuite/ld-arm/arm-elf.exp (thumb-plt, thumb-plt-got): Skip for NaCL. -- You are receiving this mail because: You are on the CC list for the bug.
[Bug ld/16017] LD creates invalid PLT instructions on CORTEX-M3
https://sourceware.org/bugzilla/show_bug.cgi?id=16017
--- Comment #31 from cvs-commit at gcc dot gnu.org ---
The binutils-2_34-branch branch has been updated by Tamar Christina
:
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=aaf3f0599a210699a76767c07a7d7f62d7633d71
commit aaf3f0599a210699a76767c07a7d7f62d7633d71
Author: Tamar Christina
Date: Wed Apr 1 10:47:18 2020 +0100
Arm: Fix LSB of GOT for Thumb2 only PLT.
When you have a Thumb only PLT then the address in the GOT for PLT0 needs
to
have the Thumb bit set since the instruction used in PLTn to get there is
`ldr.w pc` which is an inter-working instruction:
the PLT sequence in question is
0120 :
120: f240 0c98 movwip, #152; 0x98
124: f2c0 0c01 movtip, #1
128: 44fcadd ip, pc
12a: f8dc f000 ldr.w pc, [ip]
12e: e7fcb.n 12a
Disassembly of section .text:
0130 :
130: b580push{r7, lr}
132: af00add r7, sp, #0
134: f7ff fff4 bl 120
and previously the linker would generate
Hex dump of section '.got':
...
0x000101b8 40010100 1001 @...
Which would make it jump and transition out of thumb mode and crash since
you
only have thumb mode on such cores.
Now it correctly generates
Hex dump of section '.got':
...
0x000101b8 40010100 1101 @...
Thanks to Amol for testing patch and to rgujju for reporting it.
bfd/ChangeLog:
PR ld/16017
* elf32-arm.c (elf32_arm_populate_plt_entry): Set LSB of the PLT0
address in the GOT if in thumb only mode.
ld/ChangeLog:
PR ld/16017
* testsuite/ld-arm/arm-elf.exp (thumb-plt-got): New.
* testsuite/ld-arm/thumb-plt-got.d: New test.
(cherry picked from commit a7618269b727da9cf56727c22cb538ff5f0e4d25)
(cherry picked from commit 3ce23ca1de4c769c4b7247f0724a10ef5fb24a11)
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[Bug ld/16017] LD creates invalid PLT instructions on CORTEX-M3
https://sourceware.org/bugzilla/show_bug.cgi?id=16017 Tamar Christina changed: What|Removed |Added Resolution|--- |FIXED Status|REOPENED|RESOLVED --- Comment #32 from Tamar Christina --- fixed in master and 2.34 -- You are receiving this mail because: You are on the CC list for the bug.
