[Bug ld/20868] ld relaxes TLS access erroneously for aarch64 in ilp32 mode
https://sourceware.org/bugzilla/show_bug.cgi?id=20868 --- Comment #5 from cvs-commit at gcc dot gnu.org --- The master branch has been updated by Nick Clifton : https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=5cd1d8bcc24e948e86a636161e6d72f6316545a7 commit 5cd1d8bcc24e948e86a636161e6d72f6316545a7 Author: Yury Norov Date: Thu Dec 1 12:31:51 2016 + Fix accesses to the GOT for AARCH64 operating in 32-bit mode. PR ld/20868 bfd * elfnn-aarch64.c (elfNN_aarch64_tls_relax): Use 32-bit accesses to the GOT when operating in 32-bit mode. ld * testsuite/ld-aarch64/tls-relax-gd-ie-ilp32.d: New test. * testsuite/ld-aarch64/relocs-ilp32.ld: Linker script for the new test. * testsuite/ld-aarch64/aarch64-elf.exp: Run the new test. -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug ld/20868] ld relaxes TLS access erroneously for aarch64 in ilp32 mode
https://sourceware.org/bugzilla/show_bug.cgi?id=20868 Nick Clifton changed: What|Removed |Added Status|ASSIGNED|RESOLVED CC||nickc at redhat dot com Resolution|--- |FIXED --- Comment #6 from Nick Clifton --- Patch applied. -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug ld/20868] ld relaxes TLS access erroneously for aarch64 in ilp32 mode
https://sourceware.org/bugzilla/show_bug.cgi?id=20868
--- Comment #4 from Yury Norov ---
(In reply to Jiong Wang from comment #3)
> Hi Yury,
>
> Some quick thoughts:
>
> >
> > But in executalbe binary ld relaxes tls access with direct address
> > calculation:
> > 279 register unsigned long __result asm ("w0");
> > 280 asm volatile ("adrp %0, :tlsgd:foo; \n"
> > 281 400618: 9080adrpx0, 41
> > <__FRAME_END__+0xf828>
> > 282 40061c: f948ec00ldr x0, [x0,#4568]
> > 283 400620: d53bd041mrs x1, tpidr_el0
> > 284 400624: 8b20add x0, x1, x0
>
> The sequences is still loading tls offset from GOT table, then add it to the
> tp. It seems to me be a GD->IE bug on ILP32.
>
> Can you try to modify 0xf940 to 0xb940 in elfNN_aarch64_tls_relax
> when relaxing BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC, does it work for you?
>
> The "ldr x0, [x0,#4568]" looks suspicous to me. the x0 implies 8bytes
> scale, while ILP32 relocations are doing 4bytes shift.
To me too.
This code replaces TLS access with GOT using "ldr w0, [x0, ...]" manually, and
it works:
register unsigned long __result asm ("w0");
// asm volatile ("adrp %0, :tlsgd:foo; \n"
// "add %w0, %w0, #:tlsgd_lo12:foo; \n"
// "bl my_tls_get_addr;\n"
// "nop\n"
// : "=r" (__result)
// :
// : "x1", "x2", "x3", "x4", "x5", "x6", "x7",
// "x8", "x9", "x10", "x11", "x12", "x13",
// "x14", "x15", "x16", "x17", "x18", "x30",
// "memory", "cc");
asm volatile ("adrp %0, :gottprel:foo; \n"
"ldr %w0, [%0, #:gottprel_lo12:foo];\n"
"mrs x1, tpidr_el0;\n"
"add %w0, w1, %w0\n"
: "=r" (__result)
:
: "x1", "x2", "x3", "x4", "x5", "x6", "x7",
"x8", "x9", "x10", "x11", "x12", "x13",
"x14", "x15", "x16", "x17", "x18", "x30",
"memory", "cc");
bp = (unsigned int *) __result;
printf ("TLS_LD == %p\n", bp);
printf ("*TLS_LD == %d\n", *bp);
I can prepare the patch for binutils, but I need some time to setup environment
and get into the code. If you find it urgent, you'd better do it by yourself
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[Bug ld/20868] ld relaxes TLS access erroneously for aarch64 in ilp32 mode
https://sourceware.org/bugzilla/show_bug.cgi?id=20868 Andrew Pinski changed: What|Removed |Added CC||pinskia at gcc dot gnu.org -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug ld/20868] ld relaxes TLS access erroneously for aarch64 in ilp32 mode
https://sourceware.org/bugzilla/show_bug.cgi?id=20868
--- Comment #3 from Jiong Wang ---
Hi Yury,
Some quick thoughts:
>
> But in executalbe binary ld relaxes tls access with direct address
> calculation:
> 279 register unsigned long __result asm ("w0");
> 280 asm volatile ("adrp %0, :tlsgd:foo; \n"
> 281 400618: 9080adrpx0, 41 <__FRAME_END__+0xf828>
> 282 40061c: f948ec00ldr x0, [x0,#4568]
> 283 400620: d53bd041mrs x1, tpidr_el0
> 284 400624: 8b20add x0, x1, x0
The sequences is still loading tls offset from GOT table, then add it to the
tp. It seems to me be a GD->IE bug on ILP32.
Can you try to modify 0xf940 to 0xb940 in elfNN_aarch64_tls_relax when
relaxing BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC, does it work for you?
The "ldr x0, [x0,#4568]" looks suspicous to me. the x0 implies 8bytes
scale, while ILP32 relocations are doing 4bytes shift.
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[Bug ld/20868] ld relaxes TLS access erroneously for aarch64 in ilp32 mode
https://sourceware.org/bugzilla/show_bug.cgi?id=20868 --- Comment #2 from Jiong Wang --- (In reply to Jiong Wang from comment #1) > I investigate this. -> I will investigate this. -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug ld/20868] ld relaxes TLS access erroneously for aarch64 in ilp32 mode
https://sourceware.org/bugzilla/show_bug.cgi?id=20868 Jiong Wang changed: What|Removed |Added Status|UNCONFIRMED |ASSIGNED Last reconfirmed||2016-11-25 CC||jiwang at gcc dot gnu.org Assignee|unassigned at sourceware dot org |jiwang at gcc dot gnu.org Ever confirmed|0 |1 --- Comment #1 from Jiong Wang --- I investigate this. -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
