Re: [PATCH 02/12 gnumach] Add cpu_number and cpuboot

2023-01-31 Thread Samuel Thibault 
Almudena Garcia, le mar. 31 janv. 2023 22:43:39 +0100, a ecrit:
> I've just noticed that cpuboot.S is my code.

Ah, that one too?

Please, people, make sure to track which code you are re-using, to
properly account credit...

> Please make an amend to add this

Unfortunately git history cannot be modified on public trees :/

Really sorry about this...
Samuel

Re: [PATCH 02/12 gnumach] Add cpu_number and cpuboot

2023-01-31 Thread Almudena Garcia 
I've just noticed that cpuboot.S is my code. Please make an amend to add
this

El mar, 31 ene 2023 a las 20:38, Samuel Thibault ()
escribió:

> Applied, thanks!
>
> Damien Zammit, le mar. 31 janv. 2023 09:35:44 +, a ecrit:
> > I addressed most of the previous review.
> > MSRs are easier to set in asm so I have left it in.
> >
> > ---
> >  i386/i386/cpu_number.c |  33 +
> >  i386/i386/cpuboot.S| 164 +
> >  2 files changed, 197 insertions(+)
> >  create mode 100644 i386/i386/cpu_number.c
> >  create mode 100644 i386/i386/cpuboot.S
> >
> > diff --git a/i386/i386/cpu_number.c b/i386/i386/cpu_number.c
> > new file mode 100644
> > index ..65d74ddc
> > --- /dev/null
> > +++ b/i386/i386/cpu_number.c
> > @@ -0,0 +1,33 @@
> > +/*
> > + * Copyright (c) 2022 Free Software Foundation, Inc.
> > + *
> > + * This program is free software: you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation, either version 2 of the License, or
> > + * (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program.  If not, see  >.
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +#if NCPUS > 1
> > +int cpu_number(void)
> > +{
> > + int kernel_id;
> > + unsigned long flags;
> > +
> > + kernel_id = apic_get_cpu_kernel_id(apic_get_current_cpu());
> > +
> > + return kernel_id;
> > +}
> > +#endif
> > diff --git a/i386/i386/cpuboot.S b/i386/i386/cpuboot.S
> > new file mode 100644
> > index ..4a5823be
> > --- /dev/null
> > +++ b/i386/i386/cpuboot.S
> > @@ -0,0 +1,164 @@
> > +/*
> > + * Copyright (c) 2022 Free Software Foundation, Inc.
> > + *
> > + * This program is free software: you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation, either version 2 of the License, or
> > + * (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program.  If not, see  >.
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +#define AP_BOOT_ADDR 0x7000
> > +#define M(addr)  (addr - apboot + AP_BOOT_ADDR)
> > +#define CR0_CLEAR_FLAGS_CACHE_ENABLE (CR0_CD | CR0_NW)
> > +#define CR0_SET_FLAGS(CR0_CLEAR_FLAGS_CACHE_ENABLE | CR0_PE)
> > +#define CR0_CLEAR_FLAGS (CR0_PG | CR0_AM | CR0_WP | CR0_NE | CR0_TS |
> CR0_EM | CR0_MP)
> > +#define BOOT_CS  0x8
> > +#define BOOT_DS  0x10
> > +
> > +.text
> > +
> > +.align 16
> > +apboot_idt_ptr:
> > + .long 0
> > +.align 16
> > + .word 0
> > +apboot_gdt_descr:
> > + .word 3*8+7
> > + .long apboot_gdt - KERNELBASE
> > +.align 16
> > +apboot_gdt:
> > + /* NULL segment */
> > + .quad 0
> > + /* KERNEL_CS */
> > + .word 0x /* Segment limit first 0-15 bits*/
> > + .word (-KERNELBASE) & 0x /*Base first 0-15 bits*/
> > + .byte ((-KERNELBASE) >> 16) & 0xff /*Base 16-23 bits */
> > + .byte (ACC_P | ACC_CODE_R) /*Access byte */
> > + .byte 0xcf /* High 4 bits */
> > + .byte ((-KERNELBASE) >> 24) & 0xff /*Base 24-31 bits */
> > + /* KERNEL_DS */
> > + .word 0x /*Segment limit */
> > + .word (-KERNELBASE) & 0x /*Base first 0-15 bits*/
> > + .byte ((-KERNELBASE) >> 16) & 0xff
> > + .byte (ACC_P | ACC_DATA_W) /*Access byte*/
> > + .byte 0xcf /* High 4 bits */
> > + .byte ((-KERNELBASE) >> 24) & 0xff /*Base 24-31 bits */
> > +
> > +.globl apboot, apbootend
> > +.align 16
> > +.code16
> > +
> > +apboot:
> > +_apboot:
> > + cli
> > + xorl%eax, %eax
> > + movl%eax, %cr3
> > + mov %ax, %ds
> > + mov %ax, %es
> > + mov %ax, %fs
> > + mov %ax, %gs
> > + mov %ax, %ss
> > +
> > + lgdtM(gdt_descr_tmp)
> > +
> > + movl%cr0, %eax
> > + andl$~CR0_CLEAR_FLAGS, %eax
> > + orl $CR0_SET_FLAGS, %eax
> > + movl%eax, %cr0
> > +
> > + ljmp$BOOT_CS, $M(0f)
> > +0:
> > + .code32
> > + movw$BOOT_DS, %ax
> > + movw%ax, %ds
> > + movw%ax, %es
> > +

Re: Out of order building

2023-01-31 Thread Samuel Thibault 
Ryan Raymond, le lun. 30 janv. 2023 19:16:37 -0500, a ecrit:
> I think I found a resolvable issue. Still looking into it though.
> Apparently some things which depend on libstrore/libstore.so are built before
> it. The solution is to run make libstore and then continue. If this fixes it
> I'd like to make this the default behavior.
> What think?

Normally such dependencies are computed automatically. See library_deps
in Makeconf. If there is a bug there we have to fix it there, not
brown-tape around it.

Samuel

Re: [PATCH gnumach] Define rpc_vm_size_array_t and rpc_vm_offset_array_t

2023-01-31 Thread Samuel Thibault 
Applied, thanks!

Flavio Cruz, le mar. 31 janv. 2023 01:08:09 -0500, a ecrit:
> When generating stubs, Mig will will take the vm_size_array_t and define the
> input request struct using rpc_vm_size_t since the size is variable. This 
> will turn cause a mismatch
> between types (vm_size_t* vs rpc_vm_size_t*). We could also ask Mig to produce
> a prototype by using rpc_vm_size_t*, however we would need to change the 
> implementation
> of the RPC to use rpc_* types anyway since we want to avoid another allocation
> of the array.
> ---
>  i386/include/mach/i386/vm_types.h |  3 +++
>  include/mach/mach4.defs   |  8 +---
>  vm/memory_object_proxy.c  |  6 +++---
>  vm/memory_object_proxy.h  |  8 
>  vm/vm_map.c   | 13 +++--
>  5 files changed, 18 insertions(+), 20 deletions(-)
> 
> diff --git a/i386/include/mach/i386/vm_types.h 
> b/i386/include/mach/i386/vm_types.h
> index 663f920a..bd07ef26 100644
> --- a/i386/include/mach/i386/vm_types.h
> +++ b/i386/include/mach/i386/vm_types.h
> @@ -158,6 +158,9 @@ typedef long_integer_t rpc_long_integer_t;
>  #define convert_long_natural_to_user convert_vm_to_user
>  #define convert_long_natural_from_user convert_vm_from_user
>  
> +typedef  rpc_vm_size_t * rpc_vm_size_array_t;
> +typedef  rpc_vm_offset_t *   rpc_vm_offset_array_t;
> +
>  #endif   /* __ASSEMBLER__ */
>  
>  /*
> diff --git a/include/mach/mach4.defs b/include/mach/mach4.defs
> index 53cca7d3..d63d6f77 100644
> --- a/include/mach/mach4.defs
> +++ b/include/mach/mach4.defs
> @@ -108,14 +108,16 @@ skip/* pc_sampling reserved 4*/;
> protection MAX_PROTECTION and return it in *PORT.  */
>  type vm_offset_array_t = array[*:1024] of vm_offset_t;
>  type vm_size_array_t = array[*:1024] of vm_size_t;
> +type rpc_vm_size_array_t = array[*:1024] of rpc_vm_size_t;
> +type rpc_vm_offset_array_t = array[*:1024] of rpc_vm_offset_t;
>  routine memory_object_create_proxy(
>   task: ipc_space_t;
>   max_protection  : vm_prot_t;
>   object  : memory_object_array_t =
> array[*:1024] of mach_port_send_t;
> - offset  : vm_offset_array_t;
> - start   : vm_offset_array_t;
> - len : vm_size_array_t;
> + offset  : rpc_vm_offset_array_t;
> + start   : rpc_vm_offset_array_t;
> + len : rpc_vm_size_array_t;
>   out proxy   : mach_port_t);
>  
>  /* Gets a proxy to the region that ADDRESS belongs to, starting at the region
> diff --git a/vm/memory_object_proxy.c b/vm/memory_object_proxy.c
> index 46a57932..0f1e75e5 100644
> --- a/vm/memory_object_proxy.c
> +++ b/vm/memory_object_proxy.c
> @@ -133,9 +133,9 @@ memory_object_proxy_notify (mach_msg_header_t *msg)
>  kern_return_t
>  memory_object_create_proxy (ipc_space_t space, vm_prot_t max_protection,
>   ipc_port_t *object, natural_t object_count,
> - vm_offset_t *offset, natural_t offset_count,
> - vm_offset_t *start, natural_t start_count,
> - vm_size_t *len, natural_t len_count,
> + rpc_vm_offset_t *offset, natural_t offset_count,
> + rpc_vm_offset_t *start, natural_t start_count,
> + rpc_vm_size_t *len, natural_t len_count,
>   ipc_port_t *port)
>  {
>memory_object_proxy_t proxy;
> diff --git a/vm/memory_object_proxy.h b/vm/memory_object_proxy.h
> index 97f20b36..8b3f2025 100644
> --- a/vm/memory_object_proxy.h
> +++ b/vm/memory_object_proxy.h
> @@ -36,12 +36,4 @@ extern kern_return_t memory_object_proxy_lookup 
> (ipc_port_t port,
>   vm_offset_t *start,
>   vm_offset_t *len);
>  
> -extern kern_return_t
> -memory_object_create_proxy (ipc_space_t space, vm_prot_t max_protection,
> - ipc_port_t *object, natural_t object_count,
> - vm_offset_t *offset, natural_t offset_count,
> - vm_offset_t *start, natural_t start_count,
> - vm_size_t *len, natural_t len_count,
> - ipc_port_t *port);
> -
>  #endif /* _VM_MEMORY_OBJECT_PROXY_H_ */
> diff --git a/vm/vm_map.c b/vm/vm_map.c
> index bea84a4d..23c4c296 100644
> --- a/vm/vm_map.c
> +++ b/vm/vm_map.c
> @@ -4804,7 +4804,8 @@ vm_region_create_proxy (task_t task, vm_address_t 
> address,
>kern_return_t ret;
>vm_map_entry_t entry, tmp_entry;
>vm_object_t object;
> -  vm_offset_t offset, start;
> +  rpc_vm_offset_t rpc_offset, rpc_start;
> +  rpc_vm_size_t rpc_len = (rpc_vm_size_t) len;
>ipc_port_t pager;
>  
>if (task == TASK_NULL)
> @@ -4840,16 +4841,16 @@ vm_region_create_proxy (task_t task, vm_address_t

Re: [PATCH 11/12 gnumach] smp: Serialise AP bringup

2023-01-31 Thread Samuel Thibault 
Damien Zammit, le mar. 31 janv. 2023 09:39:35 +, a ecrit:
> @@ -262,11 +259,14 @@ cpu_setup()
>  void
>  cpu_ap_main()
>  {
> +unsigned apic_id = (((ApicLocalUnit*)phystokv(lapic_addr))->apic_id.r >> 
> 24) & 0xff;
> +int cpu = apic_get_cpu_kernel_id(apic_id);
> +
>  do {
>  asm volatile ("pause" : : : "memory");

I believe you actually want a full __sync_synchronize() barrier,
otherwise the booted AP may not be getting all variables flushes from
the BSP.

> @@ -309,16 +309,12 @@ start_other_cpus(void)
>   //Start cpu
>   printf("Starting AP %d\n", cpu);
>   cpu_start(cpu);
> - }
> - printf("BSP: Completed SMP init\n");
> - bspdone = 1;
> 
> - for (cpu = 1; cpu < ncpus; cpu++) {
> + bspdone++;
>   do {
>   asm volatile ("pause" : : : "memory");

And conversely here, I believe you actually want a full __sync_synchronize() 
barrier,
otherwise the BSP may not be getting all variables flushes from
the booted AP.

>   } while (machine_slot[cpu].running == FALSE);
>   }
> -
> -cpu_intr_restore(flags);
> + printf("BSP: Completed SMP init\n");
>  }
>  #endif   /* NCPUS > 1 */

> diff --git a/i386/intel/pmap.c b/i386/intel/pmap.c
> index 5cd68878..754334c9 100644
> --- a/i386/intel/pmap.c
> +++ b/i386/intel/pmap.c
> @@ -2920,6 +2920,7 @@ void pmap_update_interrupt(void)
>   int s;
> 
>   my_cpu = cpu_number();
> + printf("PMAP(%d)\n", my_cpu);
> 
>   /*
>*  Exit now if we're idle.  We'll pick up the update request

Avoid leftovers :)

Samuel

Re: [PATCH 11/12 gnumach] smp: Serialise AP bringup

2023-01-31 Thread Samuel Thibault 
I'd say squash this with patch 9, that'll answer Almudena's fear of
parallel startup :)

Also it'll avoid introducing code in patch 9 that gets fixed here in
patch 11.

Damien Zammit, le mar. 31 janv. 2023 09:39:35 +, a ecrit:
> ---
>  i386/i386/mp_desc.c | 26 +++---
>  i386/i386at/ioapic.c|  1 -
>  i386/i386at/model_dep.c |  1 -
>  i386/intel/pmap.c   |  1 +
>  kern/startup.c  |  5 -
>  5 files changed, 16 insertions(+), 18 deletions(-)
> 
> diff --git a/i386/i386/mp_desc.c b/i386/i386/mp_desc.c
> index 49ed9f94..97f7b92a 100644
> --- a/i386/i386/mp_desc.c
> +++ b/i386/i386/mp_desc.c
> @@ -204,11 +204,8 @@ interrupt_processor(int cpu)
>  }
> 
>  void
> -cpu_setup()
> +cpu_setup(int cpu)
>  {
> -unsigned apic_id = (((ApicLocalUnit*)phystokv(lapic_addr))->apic_id.r >> 
> 24) & 0xff;
> -uint16_t cpu = apic_get_cpu_kernel_id(apic_id);
> -
>  printf("AP=(%u) before\n", cpu);
> 
>  pmap_make_temporary_mapping();
> @@ -262,11 +259,14 @@ cpu_setup()
>  void
>  cpu_ap_main()
>  {
> +unsigned apic_id = (((ApicLocalUnit*)phystokv(lapic_addr))->apic_id.r >> 
> 24) & 0xff;
> +int cpu = apic_get_cpu_kernel_id(apic_id);
> +
>  do {
>  asm volatile ("pause" : : : "memory");
> -} while (!bspdone);
> +} while (bspdone != cpu);
> 
> -cpu_setup();
> +cpu_setup(cpu);
>  }
> 
>  kern_return_t
> @@ -289,9 +289,6 @@ void
>  start_other_cpus(void)
>  {
>   unsigned long flags;
> -
> - cpu_intr_save(&flags);
> -
>   int ncpus = smp_get_numcpus();
> 
>   //Copy cpu initialization assembly routine
> @@ -302,6 +299,9 @@ start_other_cpus(void)
>   lapic_enable(); /* Enable lapic only once */
>  #endif
>   unsigned cpu;
> +
> + splhigh();
> +
>   bspdone = 0;
>   for (cpu = 1; cpu < ncpus; cpu++) {
>   machine_slot[cpu].running = FALSE;
> @@ -309,16 +309,12 @@ start_other_cpus(void)
>   //Start cpu
>   printf("Starting AP %d\n", cpu);
>   cpu_start(cpu);
> - }
> - printf("BSP: Completed SMP init\n");
> - bspdone = 1;
> 
> - for (cpu = 1; cpu < ncpus; cpu++) {
> + bspdone++;
>   do {
>   asm volatile ("pause" : : : "memory");
>   } while (machine_slot[cpu].running == FALSE);
>   }
> -
> -cpu_intr_restore(flags);
> + printf("BSP: Completed SMP init\n");
>  }
>  #endif   /* NCPUS > 1 */
> diff --git a/i386/i386at/ioapic.c b/i386/i386at/ioapic.c
> index 1dd7af58..f7b0d1d3 100644
> --- a/i386/i386at/ioapic.c
> +++ b/i386/i386at/ioapic.c
> @@ -188,7 +188,6 @@ lapic_enable_timer(void)
> 
>  /* Enable interrupts for the first time */
>  printf("LAPIC timer configured on cpu%d\n", cpu_number());
> -asm("sti");
>  }
> 
>  void
> diff --git a/i386/i386at/model_dep.c b/i386/i386at/model_dep.c
> index cc18c864..7bf40df2 100644
> --- a/i386/i386at/model_dep.c
> +++ b/i386/i386at/model_dep.c
> @@ -624,7 +624,6 @@ startrtclock(void)
>  {
>  #ifndef APIC
>   clkstart();
> - asm ("sti");
>   unmask_irq(0);
>  #endif
>  }
> diff --git a/i386/intel/pmap.c b/i386/intel/pmap.c
> index 5cd68878..754334c9 100644
> --- a/i386/intel/pmap.c
> +++ b/i386/intel/pmap.c
> @@ -2920,6 +2920,7 @@ void pmap_update_interrupt(void)
>   int s;
> 
>   my_cpu = cpu_number();
> + printf("PMAP(%d)\n", my_cpu);
> 
>   /*
>*  Exit now if we're idle.  We'll pick up the update request
> diff --git a/kern/startup.c b/kern/startup.c
> index 2eb3a739..42f5ac6c 100644
> --- a/kern/startup.c
> +++ b/kern/startup.c
> @@ -308,8 +308,11 @@ void cpu_launch_first_thread(thread_t th)
> 
>   PMAP_ACTIVATE_USER(vm_map_pmap(th->task->map), th, mycpu);
> 
> +#if defined(APIC)
> + lapic_enable_timer();
> +#else
>   startrtclock(); /* needs an active thread */
> -
> +#endif
>   load_context(th);
>   /*NOTREACHED*/
>  }
> --
> 2.34.1
> 
> 
> 

-- 
Samuel
---
Pour une évaluation indépendante, transparente et rigoureuse !
Je soutiens la Commission d'Évaluation de l'Inria.

Re: [PATCH 04/12 gnumach] locore: Fix int stack check

2023-01-31 Thread Samuel Thibault 
Applied, thanks!

Damien Zammit, le mar. 31 janv. 2023 09:36:38 +, a ecrit:
> TODO: Return kernel_id via lookup table, not apic_id
> 
> ---
>  i386/i386/cpu_number.h |  7 +++
>  i386/i386/locore.S | 15 +--
>  2 files changed, 16 insertions(+), 6 deletions(-)
> 
> diff --git a/i386/i386/cpu_number.h b/i386/i386/cpu_number.h
> index 9aef6370..a6dd47d6 100644
> --- a/i386/i386/cpu_number.h
> +++ b/i386/i386/cpu_number.h
> @@ -35,6 +35,13 @@
>  /* More-specific code must define cpu_number() and CPU_NUMBER.  */
>  #ifdef __i386__
>  #define  CX(addr, reg)   addr(,reg,4)
> +
> +#define  CPU_NUMBER(reg) \
> + movl%cs:lapic, reg  ;\
> + movl%cs:APIC_ID(reg), reg   ;\
> + shrl$24, reg;\
> +
> +
>  #endif
>  #ifdef __x86_64__
>  #define  CX(addr, reg)   addr(,reg,8)
> diff --git a/i386/i386/locore.S b/i386/i386/locore.S
> index ff78e80d..5ac238f7 100644
> --- a/i386/i386/locore.S
> +++ b/i386/i386/locore.S
> @@ -541,13 +541,15 @@ _kret_iret:
>  trap_from_kernel:
>  #if  MACH_KDB || MACH_TTD
>   movl%esp,%ebx   /* save current stack */
> -
>   movl%esp,%edx   /* on an interrupt stack? */
> - and $(~(KERNEL_STACK_SIZE-1)),%edx
> - cmplEXT(int_stack_base),%edx
> +
> + CPU_NUMBER(%ecx)
> + and $(~(INTSTACK_SIZE-1)),%edx
> + cmplCX(EXT(int_stack_base),%ecx),%edx
>   je  1f  /* OK if so */
> 
> - CPU_NUMBER(%edx)/* get CPU number */
> + movl%ecx,%edx
> +
>   cmplCX(EXT(kernel_stack),%edx),%esp
>   /* already on kernel stack? */
>   ja  0f
> @@ -668,9 +670,10 @@ ENTRY(all_intrs)
>   pushl   %edx
>   cld /* clear direction flag */
> 
> + CPU_NUMBER(%ecx)
>   movl%esp,%edx   /* on an interrupt stack? */
> - and $(~(KERNEL_STACK_SIZE-1)),%edx
> - cmpl%ss:EXT(int_stack_base),%edx
> + and $(~(INTSTACK_SIZE-1)),%edx
> + cmpl%ss:CX(EXT(int_stack_base),%ecx),%edx
>   je  int_from_intstack   /* if not: */
> 
>   pushl   %ds /* save segment registers */
> --
> 2.34.1
> 
> 
> 

-- 
Samuel
---
Pour une évaluation indépendante, transparente et rigoureuse !
Je soutiens la Commission d'Évaluation de l'Inria.

Re: [PATCH gnumach] Define rpc_vm_size_array_t and rpc_vm_offset_array_t

2023-01-31 Thread Luca 

Hi Sergey,

Il 31/01/23 14:30, Sergey Bugaev ha scritto:

I understand they are related to the x64 bringup, and possibly to
running 32-bit userland on a 64-bit kernel (or to support for 32-bit
tasks communicating with 64-bit tasks?).


It's hust for running 32-bit userland on 64-bit kernel (USER32).
Mixing 32- and 64-bit tasks on the same system does not seem to be
supported at all, and in fact you must build the Mach with USER32
either defined or not, you cannot have it both ways. Unlike in XNU.


That's right, USER32 is just a simple way to isolate the code specific 
for 32-bit userland (mainly size conversions for pointers and vm_* 
types). I think it would be possible to handle both a 32-bit and a 
64-bit userspace at the same time, as in XNU, but we'd need also 
user-space support if we want to integrate 32-bit and 64-bit tasks, and 
this seems a bit more complicated to me (although I have to admit, so 
far I know better the kernel part).



But how are they different to
plain vm_size_t etc,


When running in full/native 64- (or 32-) bit mode, both rpc_vm_size_t
and vm_size_t will be of the same, well, size. But with USER32,
vm_size_t will be 64-bits wide, while rpc_vm_size_t will be 32-bits
wide. In other words, rpc_vm_size_t is "the userspace's idea of
vm_size_t".


yes, in the kernel we need to make such distinction, mainly to be able 
to use the current 32-bit userspace on a 64-bit kernel. The difference 
for the rpc_* types is only about the size and placement in memory, not 
the content (except for the cases where conversion would not be 
possible, but this would be a bug).



and when am I supposed to use one vs the other?
Does this only concern kernel land (i.e. GNU Mach) or the userland
too?


In userland, always use the regular variants. In MIG defs, use the
rpc_*variants. For the most part, MIG will handle the conversion
automatically (intran: vm_address_t
convert_vm_from_user(rpc_vm_address_t) and the like), so the
KernelServer routines can use the regular types already. That is,
except for particular cases like this one, where we have an array of
offsets/sizes which of course cannot be just converted in-place.


I think there is no need to use the rpc_* types in userspace, they can 
be ignored since the rpc_* variant should be always the same as the 
corresponding regular type. The kernel will handle the conversion, if 
needed, eventually with mig.


The array case is a bit special, as mig doesn't allow to handle the 
conversion in the same way as vm_offset_t and similar, and I think it's 
the reason for using the rpc_* types directly in the .defs files. I have 
the impression it would not be simple to add it, but fortunately this 
feature doesn't seem to be used a lot, at least in the kernel rpc. The 
only uses should be for memory objects (as in this patch) and syscall 
emulation (which seems unused in hurd and glibc)).


Note that another way to handle the size conversion between rpc_* and 
regular types would be to add some new VM types to 
include/mach/message.h; in this case, the shrink/expand would happen in 
copyinmsg()/copyoutmsg() instead of the mig-generated code (as for mach 
ports), but this approach would require to plan for a staged 
introduction of this change.


Luca

Re: [PATCH 12/12 gnumach] Debug printf when sending TLB IPI

2023-01-31 Thread Samuel Thibault 
Applied, thanks!

Damien Zammit, le mar. 31 janv. 2023 09:39:53 +, a ecrit:
> ---
>  i386/i386/smp.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/i386/i386/smp.c b/i386/i386/smp.c
> index acf69d21..c6a62958 100644
> --- a/i386/i386/smp.c
> +++ b/i386/i386/smp.c
> @@ -53,7 +53,7 @@ void smp_pmap_update(unsigned apic_id)
> 
>  cpu_intr_save(&flags);
> 
> -printf("Sending IPI(%u) to call TLB shootdown...", apic_id);
> +printf("IPI(%d>%u)\n", cpu_number(), apic_id);
>  apic_send_ipi(NO_SHORTHAND, FIXED, PHYSICAL, ASSERT, EDGE, 
> CALL_SINGLE_FUNCTION_BASE, apic_id);
> 
>  do {
> --
> 2.34.1
> 
> 
> 

-- 
Samuel
---
Pour une évaluation indépendante, transparente et rigoureuse !
Je soutiens la Commission d'Évaluation de l'Inria.

Re: [PATCH 10/12 gnumach] Fix makefrags

2023-01-31 Thread Samuel Thibault 
Applied, thanks!

Damien Zammit, le mar. 31 janv. 2023 09:39:09 +, a ecrit:
> ---
>  i386/Makefrag.am | 5 +++--
>  i386/Makefrag_x86.am | 3 +++
>  2 files changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/i386/Makefrag.am b/i386/Makefrag.am
> index 68460c49..5881f9f3 100644
> --- a/i386/Makefrag.am
> +++ b/i386/Makefrag.am
> @@ -30,6 +30,8 @@ if HOST_ix86
>  #
> 
>  libkernel_a_SOURCES += \
> + i386/i386at/acpi_parse_apic.h \
> + i386/i386at/acpi_parse_apic.c \
>   i386/i386at/autoconf.c \
>   i386/i386at/autoconf.h \
>   i386/i386at/biosmem.c \
> @@ -94,8 +96,7 @@ libkernel_a_SOURCES += \
>   i386/i386/idt_inittab.S \
>   i386/i386/locore.S \
>   i386/i386/spl.S \
> - i386/i386/smp.h
> - i386/i386/smp.c
> + i386/i386/cpuboot.S
> 
>  if PLATFORM_at
>  libkernel_a_SOURCES += \
> diff --git a/i386/Makefrag_x86.am b/i386/Makefrag_x86.am
> index 09beef0e..46c1d38b 100644
> --- a/i386/Makefrag_x86.am
> +++ b/i386/Makefrag_x86.am
> @@ -18,6 +18,7 @@ libkernel_a_SOURCES += \
>   i386/i386/ast_check.c \
>   i386/i386/ast_types.h \
>   i386/i386/cpu.h \
> + i386/i386/cpu_number.c \
>   i386/i386/cpu_number.h \
>   i386/i386/db_disasm.c \
>   i386/i386/db_interface.c \
> @@ -63,6 +64,8 @@ libkernel_a_SOURCES += \
>   i386/i386/sched_param.h \
>   i386/i386/seg.h \
>   i386/i386/setjmp.h \
> + i386/i386/smp.c \
> + i386/i386/smp.h \
>   i386/i386/spl.h \
>   i386/i386/strings.c \
>   i386/i386/task.h \
> --
> 2.34.1
> 
> 
> 

-- 
Samuel
---
Pour une évaluation indépendante, transparente et rigoureuse !
Je soutiens la Commission d'Évaluation de l'Inria.

Re: [PATCH 08/12 gnumach] smp: Deassert IPI 251 as part of sequence

2023-01-31 Thread Samuel Thibault 
Applied, thanks!

Damien Zammit, le mar. 31 janv. 2023 09:38:18 +, a ecrit:
> ---
>  i386/i386/smp.c | 6 +-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/i386/i386/smp.c b/i386/i386/smp.c
> index c351efaa..acf69d21 100644
> --- a/i386/i386/smp.c
> +++ b/i386/i386/smp.c
> @@ -60,7 +60,11 @@ void smp_pmap_update(unsigned apic_id)
>  pause_memory;
>  } while(lapic->icr_low.delivery_status == SEND_PENDING);
> 
> -printf("done\n");
> +apic_send_ipi(NO_SHORTHAND, FIXED, PHYSICAL, DE_ASSERT, EDGE, 
> CALL_SINGLE_FUNCTION_BASE, apic_id);
> +
> +do {
> +pause_memory;
> +} while(lapic->icr_low.delivery_status == SEND_PENDING);
> 
>  cpu_intr_restore(flags);
>  }
> --
> 2.34.1
> 
> 
> 

-- 
Samuel
---
Pour une évaluation indépendante, transparente et rigoureuse !
Je soutiens la Commission d'Évaluation de l'Inria.

Re: [PATCH 07/12 gnumach] Always use directed EOI and disable focus

2023-01-31 Thread Samuel Thibault 
Applied, thanks!

Damien Zammit, le mar. 31 janv. 2023 09:37:55 +, a ecrit:
> ---
>  i386/i386/apic.c | 4 +++-
>  i386/i386at/ioapic.c | 9 -
>  2 files changed, 3 insertions(+), 10 deletions(-)
> 
> diff --git a/i386/i386/apic.c b/i386/i386/apic.c
> index 891ce288..ff7ba3e2 100644
> --- a/i386/i386/apic.c
> +++ b/i386/i386/apic.c
> @@ -304,7 +304,9 @@ lapic_enable(void)
> 
>  /* Enable LAPIC to send or recieve IPI/SIPIs */
>  dummy = lapic->spurious_vector.r;
> -lapic->spurious_vector.r = dummy | LAPIC_ENABLE;
> +lapic->spurious_vector.r = IOAPIC_SPURIOUS_BASE
> +  | LAPIC_ENABLE_DIRECTED_EOI
> +  | LAPIC_ENABLE;
> 
>  lapic->error_status.r = 0;
> 
> diff --git a/i386/i386at/ioapic.c b/i386/i386at/ioapic.c
> index d4269ef0..003690ed 100644
> --- a/i386/i386at/ioapic.c
> +++ b/i386/i386at/ioapic.c
> @@ -333,15 +333,6 @@ ioapic_configure(void)
>  /* Start the IO APIC receiving interrupts */
>  lapic_enable();
> 
> -/* Enable IOAPIC processor focus */
> -lapic->spurious_vector.r |= LAPIC_FOCUS;
> -
> -/* Enable directed EOI if applicable */
> -if (has_irq_specific_eoi || lapic->version.r & LAPIC_HAS_DIRECTED_EOI) {
> -has_irq_specific_eoi = 1;
> -lapic->spurious_vector.r |= LAPIC_ENABLE_DIRECTED_EOI;
> -}
> -
>  /* Set one-shot timer */
>  lapic->divider_config.r = LAPIC_TIMER_DIVIDE_16;
>  lapic->lvt_timer.r = IOAPIC_INT_BASE;
> --
> 2.34.1
> 
> 
> 

-- 
Samuel
---
Pour une évaluation indépendante, transparente et rigoureuse !
Je soutiens la Commission d'Évaluation de l'Inria.

Re: [PATCH 06/12 gnumach] linux: Skip updating jiffies on AP timer

2023-01-31 Thread Samuel Thibault 
Applied, thanks!

Damien Zammit, le mar. 31 janv. 2023 09:37:28 +, a ecrit:
> ---
>  linux/dev/kernel/sched.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/linux/dev/kernel/sched.c b/linux/dev/kernel/sched.c
> index 2a9eeb3f..f9c52d1e 100644
> --- a/linux/dev/kernel/sched.c
> +++ b/linux/dev/kernel/sched.c
> @@ -616,6 +616,9 @@ int linux_timer_print = 0;
>  void
>  linux_timer_intr (void)
>  {
> +  if (cpu_number() != 0)
> +return;
> +
>(*(unsigned long *) &jiffies)++;
>mark_bh (TIMER_BH);
>if (tq_timer)
> --
> 2.34.1
> 
> 
> 

-- 
Samuel
---
Pour une évaluation indépendante, transparente et rigoureuse !
Je soutiens la Commission d'Évaluation de l'Inria.

Re: [PATCH 05/12 gnumach] interrupt: Send EOI before handling update interrupt

2023-01-31 Thread Samuel Thibault 
Applied, thanks!

Damien Zammit, le mar. 31 janv. 2023 09:37:03 +, a ecrit:
> ---
>  i386/i386at/interrupt.S | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/i386/i386at/interrupt.S b/i386/i386at/interrupt.S
> index 9f1883ac..1103b1c8 100644
> --- a/i386/i386at/interrupt.S
> +++ b/i386/i386at/interrupt.S
> @@ -122,8 +122,8 @@ _no_eoi:
>   ret
> 
>  _call_single:
> + callEXT(lapic_eoi)  /* lapic EOI before the handler to 
> allow extra update */
>   callEXT(pmap_update_interrupt) /* TODO: Allow other functions */
> - callEXT(lapic_eoi)  /* lapic EOI */
>   addl$24,%esp
>   ret
>  END(interrupt)
> --
> 2.34.1
> 
> 
> 

-- 
Samuel
---
Pour une évaluation indépendante, transparente et rigoureuse !
Je soutiens la Commission d'Évaluation de l'Inria.

Re: [PATCH 03/12 gnumach] Print warning on bad cpu numbering and assume BSP

2023-01-31 Thread Samuel Thibault 
Applied, thanks!

Damien Zammit, le mar. 31 janv. 2023 09:36:12 +, a ecrit:
> ---
>  i386/i386/apic.c   |  5 +
>  i386/i386/cpu_number.c | 16 +---
>  2 files changed, 18 insertions(+), 3 deletions(-)
> 
> diff --git a/i386/i386/apic.c b/i386/i386/apic.c
> index e53d4749..891ce288 100644
> --- a/i386/i386/apic.c
> +++ b/i386/i386/apic.c
> @@ -278,6 +278,11 @@ lapic_enable(void)
>  cpu_intr_save(&flags);
> 
>  apic_id = apic_get_current_cpu();
> +if (apic_id < 0)
> +  {
> +printf("apic_get_current_cpu() failed, assuming BSP\n");
> +apic_id = 0;
> +  }
> 
>  dummy = lapic->dest_format.r;
>  lapic->dest_format.r = 0x;   /* flat model */
> diff --git a/i386/i386/cpu_number.c b/i386/i386/cpu_number.c
> index 65d74ddc..c719d841 100644
> --- a/i386/i386/cpu_number.c
> +++ b/i386/i386/cpu_number.c
> @@ -19,14 +19,24 @@
>  #include 
>  #include 
>  #include 
> +#include 
> 
>  #if NCPUS > 1
>  int cpu_number(void)
>  {
> - int kernel_id;
> - unsigned long flags;
> + int kernel_id, apic_id;
> 
> - kernel_id = apic_get_cpu_kernel_id(apic_get_current_cpu());
> + apic_id = apic_get_current_cpu();
> + if (apic_id < 0) {
> + printf("apic_get_current_cpu() failed, assuming BSP\n");
> + apic_id = 0;
> + }
> +
> + kernel_id = apic_get_cpu_kernel_id(apic_id);
> + if (kernel_id < 0) {
> + printf("apic_get_cpu_kernel_id() failed, assuming BSP\n");
> + kernel_id = 0;
> + }
> 
>   return kernel_id;
>  }
> --
> 2.34.1
> 
> 
> 

-- 
Samuel
---
Pour une évaluation indépendante, transparente et rigoureuse !
Je soutiens la Commission d'Évaluation de l'Inria.

Re: [PATCH 02/12 gnumach] Add cpu_number and cpuboot

2023-01-31 Thread Samuel Thibault 
Applied, thanks!

Damien Zammit, le mar. 31 janv. 2023 09:35:44 +, a ecrit:
> I addressed most of the previous review.
> MSRs are easier to set in asm so I have left it in.
> 
> ---
>  i386/i386/cpu_number.c |  33 +
>  i386/i386/cpuboot.S| 164 +
>  2 files changed, 197 insertions(+)
>  create mode 100644 i386/i386/cpu_number.c
>  create mode 100644 i386/i386/cpuboot.S
> 
> diff --git a/i386/i386/cpu_number.c b/i386/i386/cpu_number.c
> new file mode 100644
> index ..65d74ddc
> --- /dev/null
> +++ b/i386/i386/cpu_number.c
> @@ -0,0 +1,33 @@
> +/*
> + * Copyright (c) 2022 Free Software Foundation, Inc.
> + *
> + * This program is free software: you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation, either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see .
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#if NCPUS > 1
> +int cpu_number(void)
> +{
> + int kernel_id;
> + unsigned long flags;
> +
> + kernel_id = apic_get_cpu_kernel_id(apic_get_current_cpu());
> +
> + return kernel_id;
> +}
> +#endif
> diff --git a/i386/i386/cpuboot.S b/i386/i386/cpuboot.S
> new file mode 100644
> index ..4a5823be
> --- /dev/null
> +++ b/i386/i386/cpuboot.S
> @@ -0,0 +1,164 @@
> +/*
> + * Copyright (c) 2022 Free Software Foundation, Inc.
> + *
> + * This program is free software: you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation, either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see .
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#define AP_BOOT_ADDR 0x7000
> +#define M(addr)  (addr - apboot + AP_BOOT_ADDR)
> +#define CR0_CLEAR_FLAGS_CACHE_ENABLE (CR0_CD | CR0_NW)
> +#define CR0_SET_FLAGS(CR0_CLEAR_FLAGS_CACHE_ENABLE | CR0_PE)
> +#define CR0_CLEAR_FLAGS (CR0_PG | CR0_AM | CR0_WP | CR0_NE | CR0_TS | CR0_EM 
> | CR0_MP)
> +#define BOOT_CS  0x8
> +#define BOOT_DS  0x10
> +
> +.text
> +
> +.align 16
> +apboot_idt_ptr:
> + .long 0
> +.align 16
> + .word 0
> +apboot_gdt_descr:
> + .word 3*8+7
> + .long apboot_gdt - KERNELBASE
> +.align 16
> +apboot_gdt:
> + /* NULL segment */
> + .quad 0
> + /* KERNEL_CS */
> + .word 0x /* Segment limit first 0-15 bits*/
> + .word (-KERNELBASE) & 0x /*Base first 0-15 bits*/
> + .byte ((-KERNELBASE) >> 16) & 0xff /*Base 16-23 bits */
> + .byte (ACC_P | ACC_CODE_R) /*Access byte */
> + .byte 0xcf /* High 4 bits */
> + .byte ((-KERNELBASE) >> 24) & 0xff /*Base 24-31 bits */
> + /* KERNEL_DS */
> + .word 0x /*Segment limit */
> + .word (-KERNELBASE) & 0x /*Base first 0-15 bits*/
> + .byte ((-KERNELBASE) >> 16) & 0xff
> + .byte (ACC_P | ACC_DATA_W) /*Access byte*/
> + .byte 0xcf /* High 4 bits */
> + .byte ((-KERNELBASE) >> 24) & 0xff /*Base 24-31 bits */
> +
> +.globl apboot, apbootend
> +.align 16
> +.code16
> +
> +apboot:
> +_apboot:
> + cli
> + xorl%eax, %eax
> + movl%eax, %cr3
> + mov %ax, %ds
> + mov %ax, %es
> + mov %ax, %fs
> + mov %ax, %gs
> + mov %ax, %ss
> +
> + lgdtM(gdt_descr_tmp)
> +
> + movl%cr0, %eax
> + andl$~CR0_CLEAR_FLAGS, %eax
> + orl $CR0_SET_FLAGS, %eax
> + movl%eax, %cr0
> +
> + ljmp$BOOT_CS, $M(0f)
> +0:
> + .code32
> + movw$BOOT_DS, %ax
> + movw%ax, %ds
> + movw%ax, %es
> + movw%ax, %ss
> +
> + lgdtl   apboot_gdt_descr - KERNELBASE
> + ljmpl   $KERNEL_CS, $1f
> +1:
> + xorl%eax, %eax
> + movw%ax, %ds
> + movw%ax, %es
> + movw%ax, %fs
> + movw%ax, %gs
> + movw$KERNEL_DS, %ax
> + movw%ax, %ds
> + movw%ax, %es
> + movw%ax, %fs
> + movw%ax, %gs
> + movw%ax, %ss
> +
> + /* Load null Interrupt descriptor ta

Re: [PATCH 01/12 gnumach] i386: Fix lapic and ioapic for smp

2023-01-31 Thread Samuel Thibault 
Applied, thanks!

Damien Zammit, le mar. 31 janv. 2023 09:35:21 +, a ecrit:
> Also-by: Almudena Garcia 
> ---
>  i386/i386/apic.c |  87 ++---
>  i386/i386/apic.h | 114 ---
>  i386/i386/smp.c  |  89 -
>  i386/i386/smp.h  |   7 +++
>  i386/i386at/ioapic.c |  97 ++--
>  5 files changed, 307 insertions(+), 87 deletions(-)
> 
> diff --git a/i386/i386/apic.c b/i386/i386/apic.c
> index d30084e2..e53d4749 100644
> --- a/i386/i386/apic.c
> +++ b/i386/i386/apic.c
> @@ -19,6 +19,8 @@
> Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111, USA. */
> 
>  #include 
> +#include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -112,7 +114,7 @@ acpi_get_irq_override(uint8_t pin)
>   * apic_get_cpu_apic_id: returns the apic_id of a cpu.
>   * Receives as input the kernel ID of a CPU.
>   */
> -uint16_t
> +int
>  apic_get_cpu_apic_id(int kernel_id)
>  {
>  if (kernel_id >= NCPUS)
> @@ -121,6 +123,24 @@ apic_get_cpu_apic_id(int kernel_id)
>  return apic_data.cpu_lapic_list[kernel_id];
>  }
> 
> +
> +/*
> + * apic_get_cpu_kernel_id: returns the kernel_id of a cpu.
> + * Receives as input the APIC ID of a CPU.
> + */
> +int
> +apic_get_cpu_kernel_id(uint16_t apic_id)
> +{
> +int i;
> +
> +for (i = 0; i < apic_data.ncpus; i++) {
> +if (apic_data.cpu_lapic_list[i] == apic_id)
> +return i;
> +}
> +
> +return -1;
> +}
> +
>  /* apic_get_lapic: returns a reference to the common memory address for 
> Local APIC. */
>  volatile ApicLocalUnit*
>  apic_get_lapic(void)
> @@ -158,17 +178,13 @@ apic_get_num_ioapics(void)
>  /*
>   * apic_get_current_cpu: returns the apic_id of current cpu.
>   */
> -uint16_t
> +int
>  apic_get_current_cpu(void)
>  {
> -uint16_t apic_id;
> -
>  if(lapic == NULL)
> -apic_id = 0;
> -else
> -apic_id = lapic->apic_id.r;
> +return -1;
> 
> -return apic_id;
> +return (lapic->apic_id.r >> 24) & 0xff;
>  }
> 
> 
> @@ -235,6 +251,61 @@ void apic_print_info(void)
>  }
>  }
> 
> +void apic_send_ipi(unsigned dest_shorthand, unsigned deliv_mode, unsigned 
> dest_mode, unsigned level, unsigned trig_mode, unsigned vector, unsigned 
> dest_id)
> +{
> +IcrLReg icrl_values;
> +IcrHReg icrh_values;
> +
> +icrl_values.destination_shorthand = dest_shorthand;
> +icrl_values.delivery_mode = deliv_mode;
> +icrl_values.destination_mode = dest_mode;
> +icrl_values.level = level;
> +icrl_values.trigger_mode = trig_mode;
> +icrl_values.vector = vector;
> +icrh_values.destination_field = dest_id;
> +
> +lapic->icr_high = icrh_values;
> +lapic->icr_low = icrl_values;
> +}
> +
> +void
> +lapic_enable(void)
> +{
> +unsigned long flags;
> +int apic_id;
> +volatile uint32_t dummy;
> +
> +cpu_intr_save(&flags);
> +
> +apic_id = apic_get_current_cpu();
> +
> +dummy = lapic->dest_format.r;
> +lapic->dest_format.r = 0x;   /* flat model */
> +dummy = lapic->logical_dest.r;
> +lapic->logical_dest.r = lapic->apic_id.r;/* target self */
> +dummy = lapic->lvt_lint0.r;
> +lapic->lvt_lint0.r = dummy | LAPIC_DISABLE;
> +dummy = lapic->lvt_lint1.r;
> +lapic->lvt_lint1.r = dummy | LAPIC_DISABLE;
> +dummy = lapic->lvt_performance_monitor.r;
> +lapic->lvt_performance_monitor.r = dummy | LAPIC_DISABLE;
> +if (apic_id != 0)
> +  {
> +dummy = lapic->lvt_timer.r;
> +lapic->lvt_timer.r = dummy | LAPIC_DISABLE;
> +  }
> +dummy = lapic->task_pri.r;
> +lapic->task_pri.r = 0;
> +
> +/* Enable LAPIC to send or recieve IPI/SIPIs */
> +dummy = lapic->spurious_vector.r;
> +lapic->spurious_vector.r = dummy | LAPIC_ENABLE;
> +
> +lapic->error_status.r = 0;
> +
> +cpu_intr_restore(flags);
> +}
> +
>  void
>  lapic_eoi(void)
>  {
> diff --git a/i386/i386/apic.h b/i386/i386/apic.h
> index 0bb1bd73..ac083d26 100644
> --- a/i386/i386/apic.h
> +++ b/i386/i386/apic.h
> @@ -61,10 +61,99 @@ union ioapic_route_entry_union {
>  struct ioapic_route_entry both;
>  };
> 
> +
> +/* Grateful to trasterlabs for this snippet */
> +
> +typedef union u_icr_low
> +{
> +uint32_t value[4];
> +struct
> +{
> +uint32_t r;// FEE0 0300H - 4 bytes
> +unsigned :32;  // FEE0 0304H
> +unsigned :32;  // FEE0 0308H
> +unsigned :32;  // FEE0 030CH
> +};
> +struct
> +{
> +unsigned vector: 8; /* Vector of interrupt. Lowest 8 bits of routine 
> address */
> +unsigned delivery_mode : 3;
> +unsigned destination_mode: 1;
> +unsigned delivery_status: 1;
> +unsigned :1;
> +unsigned level: 1;
> +unsigned trigger_mode: 1;
> +unsigned :2;
> +unsigned destination_shorthand: 2;
> +unsigned :12;
> +};
> +} IcrLReg;
> +
> +typ

Re: [PATCH 09/12 gnumach] i386: Refactor int stacks for SMP - shared temp pmap

2023-01-31 Thread Almudena Garcia 
void
 start_other_cpus(void)
 {
-   int cpu;
-   for (cpu = 0; cpu < NCPUS; cpu++)
-   if (cpu != cpu_number())
-   cpu_start(cpu);
-}
+   unsigned long flags;
+
+   cpu_intr_save(&flags);
+
+   int ncpus = smp_get_numcpus();

+   //Copy cpu initialization assembly routine
+   memcpy((void*)phystokv(AP_BOOT_ADDR), (void*) &apboot,
+  (uint32_t)&apbootend - (uint32_t)&apboot);
+
+#ifndef APIC
+   lapic_enable(); /* Enable lapic only once */
+#endif
+   unsigned cpu;
+   bspdone = 0;
+   for (cpu = 1; cpu < ncpus; cpu++) {
+   machine_slot[cpu].running = FALSE;
+
+   //Start cpu
+   printf("Starting AP %d\n", cpu);
+   cpu_start(cpu);
+   }
+   printf("BSP: Completed SMP init\n");
+   bspdone = 1;
+
+   for (cpu = 1; cpu < ncpus; cpu++) {
+   do {
+   asm volatile ("pause" : : : "memory");
+   } while (machine_slot[cpu].running == FALSE);
+   }
+
+cpu_intr_restore(flags);
+}

Raise all startup IPI at same time could be dangerous: all cpus try to
access to same assembly routine in the same address, added to other
problems.
I prefer don't startup a new AP until the current AP is enabled.


+/* Turn paging on.
+ * TODO: Why does setting the WP bit here cause a crash?
+ */
+set_cr0(get_cr0() | CR0_PG /* | CR0_WP */);
+set_cr0(get_cr0() & ~(CR0_CD | CR0_NW));
+if (CPU_HAS_FEATURE(CPU_FEATURE_PGE))
+set_cr4(get_cr4() | CR4_PGE);

I prefer to put this code in a separated function, calling this after
cpu_setup() is finished.
+unsigned apic_id = (((ApicLocalUnit*)phystokv(lapic_addr))->apic_id.r
>> 24) & 0xff;

Be careful, because this type of access to lapic only works before pagging
is enabled, only works with segmentation.
Once pagging is enabled, you must be able to access to local_apic (and
apic_id) directly through its pointer. Even, after this, probably you can
get the apic_id calling to the proper function which I implemented in apic.c

El mar, 31 ene 2023 a las 10:39, Damien Zammit ()
escribió:

> Also-by: Almudena Garcia 
> ---
>  i386/i386/cpu_number.h   |  15 +-
>  i386/i386/cswitch.S  |   6 +-
>  i386/i386/i386asm.sym|   3 +
>  i386/i386/locore.S   |   4 +-
>  i386/i386/mp_desc.c  | 227 ++-
>  i386/i386/mp_desc.h  |   7 +-
>  i386/i386at/boothdr.S|  18 ++-
>  i386/i386at/ioapic.c |   4 +-
>  i386/i386at/model_dep.c  | 101 +++---
>  i386/i386at/model_dep.h  |   3 +-
>  i386/intel/pmap.c| 103 --
>  i386/intel/pmap.h|   6 +
>  linux/dev/arch/i386/kernel/irq.c |  13 +-
>  linux/dev/init/main.c|   2 +
>  14 files changed, 322 insertions(+), 190 deletions(-)
>
> diff --git a/i386/i386/cpu_number.h b/i386/i386/cpu_number.h
> index a6dd47d6..46232459 100644
> --- a/i386/i386/cpu_number.h
> +++ b/i386/i386/cpu_number.h
> @@ -32,6 +32,8 @@
>
>  #ifNCPUS > 1
>
> +#include "apic.h"
> +
>  /* More-specific code must define cpu_number() and CPU_NUMBER.  */
>  #ifdef __i386__
>  #defineCX(addr, reg)   addr(,reg,4)
> @@ -45,11 +47,14 @@
>  #endif
>  #ifdef __x86_64__
>  #defineCX(addr, reg)   addr(,reg,8)
> +#warning Missing CPU_NUMBER() for 64 bit
> +#define CPU_NUMBER(reg)
>  #endif
>
> -/* XXX For now */
> -#defineCPU_NUMBER(reg) movl $0,reg
> -#define cpu_number() 0
> +#ifndef __ASSEMBLER__
> +#include "kern/cpu_number.h"
> +int cpu_number(void);
> +#endif
>
>  #else  /* NCPUS == 1 */
>
> @@ -58,8 +63,4 @@
>
>  #endif /* NCPUS == 1 */
>
> -#ifndef __ASSEMBLER__
> -#include "kern/cpu_number.h"
> -#endif
> -
>  #endif /* _I386_CPU_NUMBER_H_ */
> diff --git a/i386/i386/cswitch.S b/i386/i386/cswitch.S
> index 718c8aac..ae941bdd 100644
> --- a/i386/i386/cswitch.S
> +++ b/i386/i386/cswitch.S
> @@ -110,7 +110,7 @@ ENTRY(Thread_continue)
>   */
>  ENTRY(switch_to_shutdown_context)
> CPU_NUMBER(%edx)
> -   movlEXT(active_stacks)(,%edx,4),%ecx/* get old kernel
> stack */
> +   movlCX(EXT(active_stacks),%edx),%ecx/* get old kernel
> stack */
> movl%ebx,KSS_EBX(%ecx)  /* save registers */
> movl%ebp,KSS_EBP(%ecx)
> movl%edi,KSS_EDI(%ecx)
> @@ -124,8 +124,8 @@ ENTRY(switch_to_shutdown_context)
> movl4(%esp),%ebx/* get routine to run next
> */
> movl8(%esp),%esi/* get its argument */
>
> -   movlEXT(interrupt_stack)(,%edx,4),%ecx  /* point to its
> interrupt stack */
> -   lea INTSTACK_SIZE(%ecx),%esp/* switch to it (top) */
> +   movlCX(EXT(int_stack_base),%edx),%ecx   /* point to its
> interrupt stack */
> +   lea -4+INTSTACK_SIZE(%ecx),%esp /* switch to it (top) *

Re: [PATCH gnumach] Define rpc_vm_size_array_t and rpc_vm_offset_array_t

2023-01-31 Thread Sergey Bugaev 
Replying to myself after looking at the definition:

On Tue, Jan 31, 2023 at 12:06 PM Sergey Bugaev  wrote:
>
> I understand they are related to the x64 bringup, and possibly to
> running 32-bit userland on a 64-bit kernel (or to support for 32-bit
> tasks communicating with 64-bit tasks?).

It's hust for running 32-bit userland on 64-bit kernel (USER32).
Mixing 32- and 64-bit tasks on the same system does not seem to be
supported at all, and in fact you must build the Mach with USER32
either defined or not, you cannot have it both ways. Unlike in XNU.

> But how are they different to
> plain vm_size_t etc,

When running in full/native 64- (or 32-) bit mode, both rpc_vm_size_t
and vm_size_t will be of the same, well, size. But with USER32,
vm_size_t will be 64-bits wide, while rpc_vm_size_t will be 32-bits
wide. In other words, rpc_vm_size_t is "the userspace's idea of
vm_size_t".

> and when am I supposed to use one vs the other?
> Does this only concern kernel land (i.e. GNU Mach) or the userland
> too?

In userland, always use the regular variants. In MIG defs, use the
rpc_*variants. For the most part, MIG will handle the conversion
automatically (intran: vm_address_t
convert_vm_from_user(rpc_vm_address_t) and the like), so the
KernelServer routines can use the regular types already. That is,
except for particular cases like this one, where we have an array of
offsets/sizes which of course cannot be just converted in-place.

Did I get it right?

Sergey

Re: [PATCH 09/12 gnumach] i386: Refactor int stacks for SMP - shared temp pmap

2023-01-31 Thread Almudena Garcia 
Please. Don't enable pagging yet. It requires some preliminary steps. Added
to this, I prefer configure pagging in a separate function

El mar., 31 ene. 2023 10:39, Damien Zammit  escribió:

> Also-by: Almudena Garcia 
> ---
>  i386/i386/cpu_number.h   |  15 +-
>  i386/i386/cswitch.S  |   6 +-
>  i386/i386/i386asm.sym|   3 +
>  i386/i386/locore.S   |   4 +-
>  i386/i386/mp_desc.c  | 227 ++-
>  i386/i386/mp_desc.h  |   7 +-
>  i386/i386at/boothdr.S|  18 ++-
>  i386/i386at/ioapic.c |   4 +-
>  i386/i386at/model_dep.c  | 101 +++---
>  i386/i386at/model_dep.h  |   3 +-
>  i386/intel/pmap.c| 103 --
>  i386/intel/pmap.h|   6 +
>  linux/dev/arch/i386/kernel/irq.c |  13 +-
>  linux/dev/init/main.c|   2 +
>  14 files changed, 322 insertions(+), 190 deletions(-)
>
> diff --git a/i386/i386/cpu_number.h b/i386/i386/cpu_number.h
> index a6dd47d6..46232459 100644
> --- a/i386/i386/cpu_number.h
> +++ b/i386/i386/cpu_number.h
> @@ -32,6 +32,8 @@
>
>  #ifNCPUS > 1
>
> +#include "apic.h"
> +
>  /* More-specific code must define cpu_number() and CPU_NUMBER.  */
>  #ifdef __i386__
>  #defineCX(addr, reg)   addr(,reg,4)
> @@ -45,11 +47,14 @@
>  #endif
>  #ifdef __x86_64__
>  #defineCX(addr, reg)   addr(,reg,8)
> +#warning Missing CPU_NUMBER() for 64 bit
> +#define CPU_NUMBER(reg)
>  #endif
>
> -/* XXX For now */
> -#defineCPU_NUMBER(reg) movl $0,reg
> -#define cpu_number() 0
> +#ifndef __ASSEMBLER__
> +#include "kern/cpu_number.h"
> +int cpu_number(void);
> +#endif
>
>  #else  /* NCPUS == 1 */
>
> @@ -58,8 +63,4 @@
>
>  #endif /* NCPUS == 1 */
>
> -#ifndef __ASSEMBLER__
> -#include "kern/cpu_number.h"
> -#endif
> -
>  #endif /* _I386_CPU_NUMBER_H_ */
> diff --git a/i386/i386/cswitch.S b/i386/i386/cswitch.S
> index 718c8aac..ae941bdd 100644
> --- a/i386/i386/cswitch.S
> +++ b/i386/i386/cswitch.S
> @@ -110,7 +110,7 @@ ENTRY(Thread_continue)
>   */
>  ENTRY(switch_to_shutdown_context)
> CPU_NUMBER(%edx)
> -   movlEXT(active_stacks)(,%edx,4),%ecx/* get old kernel
> stack */
> +   movlCX(EXT(active_stacks),%edx),%ecx/* get old kernel
> stack */
> movl%ebx,KSS_EBX(%ecx)  /* save registers */
> movl%ebp,KSS_EBP(%ecx)
> movl%edi,KSS_EDI(%ecx)
> @@ -124,8 +124,8 @@ ENTRY(switch_to_shutdown_context)
> movl4(%esp),%ebx/* get routine to run next
> */
> movl8(%esp),%esi/* get its argument */
>
> -   movlEXT(interrupt_stack)(,%edx,4),%ecx  /* point to its
> interrupt stack */
> -   lea INTSTACK_SIZE(%ecx),%esp/* switch to it (top) */
> +   movlCX(EXT(int_stack_base),%edx),%ecx   /* point to its
> interrupt stack */
> +   lea -4+INTSTACK_SIZE(%ecx),%esp /* switch to it (top) */
>
> pushl   %eax/* push thread */
> callEXT(thread_dispatch)/* reschedule thread */
> diff --git a/i386/i386/i386asm.sym b/i386/i386/i386asm.sym
> index 85658b30..8317db6c 100644
> --- a/i386/i386/i386asm.sym
> +++ b/i386/i386/i386asm.sym
> @@ -45,10 +45,13 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>
>  expr   CALL_SINGLE_FUNCTION_BASE
>
> +offset ApicLocalUnit   lu  apic_id APIC_ID
> +
>  offset thread  th  pcb
>  offset thread  th  task
>  offset thread  th  recover
> diff --git a/i386/i386/locore.S b/i386/i386/locore.S
> index 5ac238f7..55add6e4 100644
> --- a/i386/i386/locore.S
> +++ b/i386/i386/locore.S
> @@ -689,6 +689,7 @@ ENTRY(all_intrs)
> CPU_NUMBER(%edx)
>
> movlCX(EXT(int_stack_top),%edx),%ecx
> +
> xchgl   %ecx,%esp   /* switch to interrupt stack */
>
>  #ifSTAT_TIME
> @@ -733,7 +734,8 @@ LEXT(return_to_iret)/* ( label
> for kdb_kintr and hardclock) */
> iret/* return to caller */
>
>  int_from_intstack:
> -   cmplEXT(int_stack_base),%esp/* seemingly looping? */
> +   CPU_NUMBER(%edx)
> +   cmplCX(EXT(int_stack_base),%edx),%esp /* seemingly looping? */
> jb  stack_overflowed/* if not: */
> callEXT(interrupt)  /* call interrupt routine */
>  _return_to_iret_i: /* ( label for kdb_kintr) */
> diff --git a/i386/i386/mp_desc.c b/i386/i386/mp_desc.c
> index bcf2fbe7..49ed9f94 100644
> --- a/i386/i386/mp_desc.c
> +++ b/i386/i386/mp_desc.c
> @@ -24,25 +24,36 @@
>   * the rights to redistribute these changes.
>   */
>
> -#ifNCPUS > 1
> -
> -#include 
> -
>  #include 
>  #include 
>  #include 
> +#include 
> +#include 
> +#include 
>  #include 
>  #include 
>  #include 
>
>  #include 
>

[PATCH 12/12 gnumach] Debug printf when sending TLB IPI

2023-01-31 Thread Damien Zammit 
---
 i386/i386/smp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/i386/i386/smp.c b/i386/i386/smp.c
index acf69d21..c6a62958 100644
--- a/i386/i386/smp.c
+++ b/i386/i386/smp.c
@@ -53,7 +53,7 @@ void smp_pmap_update(unsigned apic_id)

 cpu_intr_save(&flags);

-printf("Sending IPI(%u) to call TLB shootdown...", apic_id);
+printf("IPI(%d>%u)\n", cpu_number(), apic_id);
 apic_send_ipi(NO_SHORTHAND, FIXED, PHYSICAL, ASSERT, EDGE, 
CALL_SINGLE_FUNCTION_BASE, apic_id);

 do {
--
2.34.1

[PATCH 11/12 gnumach] smp: Serialise AP bringup

2023-01-31 Thread Damien Zammit 
---
 i386/i386/mp_desc.c | 26 +++---
 i386/i386at/ioapic.c|  1 -
 i386/i386at/model_dep.c |  1 -
 i386/intel/pmap.c   |  1 +
 kern/startup.c  |  5 -
 5 files changed, 16 insertions(+), 18 deletions(-)

diff --git a/i386/i386/mp_desc.c b/i386/i386/mp_desc.c
index 49ed9f94..97f7b92a 100644
--- a/i386/i386/mp_desc.c
+++ b/i386/i386/mp_desc.c
@@ -204,11 +204,8 @@ interrupt_processor(int cpu)
 }

 void
-cpu_setup()
+cpu_setup(int cpu)
 {
-unsigned apic_id = (((ApicLocalUnit*)phystokv(lapic_addr))->apic_id.r >> 
24) & 0xff;
-uint16_t cpu = apic_get_cpu_kernel_id(apic_id);
-
 printf("AP=(%u) before\n", cpu);

 pmap_make_temporary_mapping();
@@ -262,11 +259,14 @@ cpu_setup()
 void
 cpu_ap_main()
 {
+unsigned apic_id = (((ApicLocalUnit*)phystokv(lapic_addr))->apic_id.r >> 
24) & 0xff;
+int cpu = apic_get_cpu_kernel_id(apic_id);
+
 do {
 asm volatile ("pause" : : : "memory");
-} while (!bspdone);
+} while (bspdone != cpu);

-cpu_setup();
+cpu_setup(cpu);
 }

 kern_return_t
@@ -289,9 +289,6 @@ void
 start_other_cpus(void)
 {
unsigned long flags;
-
-   cpu_intr_save(&flags);
-
int ncpus = smp_get_numcpus();

//Copy cpu initialization assembly routine
@@ -302,6 +299,9 @@ start_other_cpus(void)
lapic_enable(); /* Enable lapic only once */
 #endif
unsigned cpu;
+
+   splhigh();
+
bspdone = 0;
for (cpu = 1; cpu < ncpus; cpu++) {
machine_slot[cpu].running = FALSE;
@@ -309,16 +309,12 @@ start_other_cpus(void)
//Start cpu
printf("Starting AP %d\n", cpu);
cpu_start(cpu);
-   }
-   printf("BSP: Completed SMP init\n");
-   bspdone = 1;

-   for (cpu = 1; cpu < ncpus; cpu++) {
+   bspdone++;
do {
asm volatile ("pause" : : : "memory");
} while (machine_slot[cpu].running == FALSE);
}
-
-cpu_intr_restore(flags);
+   printf("BSP: Completed SMP init\n");
 }
 #endif /* NCPUS > 1 */
diff --git a/i386/i386at/ioapic.c b/i386/i386at/ioapic.c
index 1dd7af58..f7b0d1d3 100644
--- a/i386/i386at/ioapic.c
+++ b/i386/i386at/ioapic.c
@@ -188,7 +188,6 @@ lapic_enable_timer(void)

 /* Enable interrupts for the first time */
 printf("LAPIC timer configured on cpu%d\n", cpu_number());
-asm("sti");
 }

 void
diff --git a/i386/i386at/model_dep.c b/i386/i386at/model_dep.c
index cc18c864..7bf40df2 100644
--- a/i386/i386at/model_dep.c
+++ b/i386/i386at/model_dep.c
@@ -624,7 +624,6 @@ startrtclock(void)
 {
 #ifndef APIC
clkstart();
-   asm ("sti");
unmask_irq(0);
 #endif
 }
diff --git a/i386/intel/pmap.c b/i386/intel/pmap.c
index 5cd68878..754334c9 100644
--- a/i386/intel/pmap.c
+++ b/i386/intel/pmap.c
@@ -2920,6 +2920,7 @@ void pmap_update_interrupt(void)
int s;

my_cpu = cpu_number();
+   printf("PMAP(%d)\n", my_cpu);

/*
 *  Exit now if we're idle.  We'll pick up the update request
diff --git a/kern/startup.c b/kern/startup.c
index 2eb3a739..42f5ac6c 100644
--- a/kern/startup.c
+++ b/kern/startup.c
@@ -308,8 +308,11 @@ void cpu_launch_first_thread(thread_t th)

PMAP_ACTIVATE_USER(vm_map_pmap(th->task->map), th, mycpu);

+#if defined(APIC)
+   lapic_enable_timer();
+#else
startrtclock(); /* needs an active thread */
-
+#endif
load_context(th);
/*NOTREACHED*/
 }
--
2.34.1

[PATCH 10/12 gnumach] Fix makefrags

2023-01-31 Thread Damien Zammit 
---
 i386/Makefrag.am | 5 +++--
 i386/Makefrag_x86.am | 3 +++
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/i386/Makefrag.am b/i386/Makefrag.am
index 68460c49..5881f9f3 100644
--- a/i386/Makefrag.am
+++ b/i386/Makefrag.am
@@ -30,6 +30,8 @@ if HOST_ix86
 #

 libkernel_a_SOURCES += \
+   i386/i386at/acpi_parse_apic.h \
+   i386/i386at/acpi_parse_apic.c \
i386/i386at/autoconf.c \
i386/i386at/autoconf.h \
i386/i386at/biosmem.c \
@@ -94,8 +96,7 @@ libkernel_a_SOURCES += \
i386/i386/idt_inittab.S \
i386/i386/locore.S \
i386/i386/spl.S \
-   i386/i386/smp.h
-   i386/i386/smp.c
+   i386/i386/cpuboot.S

 if PLATFORM_at
 libkernel_a_SOURCES += \
diff --git a/i386/Makefrag_x86.am b/i386/Makefrag_x86.am
index 09beef0e..46c1d38b 100644
--- a/i386/Makefrag_x86.am
+++ b/i386/Makefrag_x86.am
@@ -18,6 +18,7 @@ libkernel_a_SOURCES += \
i386/i386/ast_check.c \
i386/i386/ast_types.h \
i386/i386/cpu.h \
+   i386/i386/cpu_number.c \
i386/i386/cpu_number.h \
i386/i386/db_disasm.c \
i386/i386/db_interface.c \
@@ -63,6 +64,8 @@ libkernel_a_SOURCES += \
i386/i386/sched_param.h \
i386/i386/seg.h \
i386/i386/setjmp.h \
+   i386/i386/smp.c \
+   i386/i386/smp.h \
i386/i386/spl.h \
i386/i386/strings.c \
i386/i386/task.h \
--
2.34.1

[PATCH 09/12 gnumach] i386: Refactor int stacks for SMP - shared temp pmap

2023-01-31 Thread Damien Zammit 
Also-by: Almudena Garcia 
---
 i386/i386/cpu_number.h   |  15 +-
 i386/i386/cswitch.S  |   6 +-
 i386/i386/i386asm.sym|   3 +
 i386/i386/locore.S   |   4 +-
 i386/i386/mp_desc.c  | 227 ++-
 i386/i386/mp_desc.h  |   7 +-
 i386/i386at/boothdr.S|  18 ++-
 i386/i386at/ioapic.c |   4 +-
 i386/i386at/model_dep.c  | 101 +++---
 i386/i386at/model_dep.h  |   3 +-
 i386/intel/pmap.c| 103 --
 i386/intel/pmap.h|   6 +
 linux/dev/arch/i386/kernel/irq.c |  13 +-
 linux/dev/init/main.c|   2 +
 14 files changed, 322 insertions(+), 190 deletions(-)

diff --git a/i386/i386/cpu_number.h b/i386/i386/cpu_number.h
index a6dd47d6..46232459 100644
--- a/i386/i386/cpu_number.h
+++ b/i386/i386/cpu_number.h
@@ -32,6 +32,8 @@

 #ifNCPUS > 1

+#include "apic.h"
+
 /* More-specific code must define cpu_number() and CPU_NUMBER.  */
 #ifdef __i386__
 #defineCX(addr, reg)   addr(,reg,4)
@@ -45,11 +47,14 @@
 #endif
 #ifdef __x86_64__
 #defineCX(addr, reg)   addr(,reg,8)
+#warning Missing CPU_NUMBER() for 64 bit
+#define CPU_NUMBER(reg)
 #endif

-/* XXX For now */
-#defineCPU_NUMBER(reg) movl $0,reg
-#define cpu_number() 0
+#ifndef __ASSEMBLER__
+#include "kern/cpu_number.h"
+int cpu_number(void);
+#endif

 #else  /* NCPUS == 1 */

@@ -58,8 +63,4 @@

 #endif /* NCPUS == 1 */

-#ifndef __ASSEMBLER__
-#include "kern/cpu_number.h"
-#endif
-
 #endif /* _I386_CPU_NUMBER_H_ */
diff --git a/i386/i386/cswitch.S b/i386/i386/cswitch.S
index 718c8aac..ae941bdd 100644
--- a/i386/i386/cswitch.S
+++ b/i386/i386/cswitch.S
@@ -110,7 +110,7 @@ ENTRY(Thread_continue)
  */
 ENTRY(switch_to_shutdown_context)
CPU_NUMBER(%edx)
-   movlEXT(active_stacks)(,%edx,4),%ecx/* get old kernel stack 
*/
+   movlCX(EXT(active_stacks),%edx),%ecx/* get old kernel stack 
*/
movl%ebx,KSS_EBX(%ecx)  /* save registers */
movl%ebp,KSS_EBP(%ecx)
movl%edi,KSS_EDI(%ecx)
@@ -124,8 +124,8 @@ ENTRY(switch_to_shutdown_context)
movl4(%esp),%ebx/* get routine to run next */
movl8(%esp),%esi/* get its argument */

-   movlEXT(interrupt_stack)(,%edx,4),%ecx  /* point to its 
interrupt stack */
-   lea INTSTACK_SIZE(%ecx),%esp/* switch to it (top) */
+   movlCX(EXT(int_stack_base),%edx),%ecx   /* point to its 
interrupt stack */
+   lea -4+INTSTACK_SIZE(%ecx),%esp /* switch to it (top) */

pushl   %eax/* push thread */
callEXT(thread_dispatch)/* reschedule thread */
diff --git a/i386/i386/i386asm.sym b/i386/i386/i386asm.sym
index 85658b30..8317db6c 100644
--- a/i386/i386/i386asm.sym
+++ b/i386/i386/i386asm.sym
@@ -45,10 +45,13 @@
 #include 
 #include 
 #include 
+#include 
 #include 

 expr   CALL_SINGLE_FUNCTION_BASE

+offset ApicLocalUnit   lu  apic_id APIC_ID
+
 offset thread  th  pcb
 offset thread  th  task
 offset thread  th  recover
diff --git a/i386/i386/locore.S b/i386/i386/locore.S
index 5ac238f7..55add6e4 100644
--- a/i386/i386/locore.S
+++ b/i386/i386/locore.S
@@ -689,6 +689,7 @@ ENTRY(all_intrs)
CPU_NUMBER(%edx)

movlCX(EXT(int_stack_top),%edx),%ecx
+
xchgl   %ecx,%esp   /* switch to interrupt stack */

 #ifSTAT_TIME
@@ -733,7 +734,8 @@ LEXT(return_to_iret)/* ( label for 
kdb_kintr and hardclock) */
iret/* return to caller */

 int_from_intstack:
-   cmplEXT(int_stack_base),%esp/* seemingly looping? */
+   CPU_NUMBER(%edx)
+   cmplCX(EXT(int_stack_base),%edx),%esp /* seemingly looping? */
jb  stack_overflowed/* if not: */
callEXT(interrupt)  /* call interrupt routine */
 _return_to_iret_i: /* ( label for kdb_kintr) */
diff --git a/i386/i386/mp_desc.c b/i386/i386/mp_desc.c
index bcf2fbe7..49ed9f94 100644
--- a/i386/i386/mp_desc.c
+++ b/i386/i386/mp_desc.c
@@ -24,25 +24,36 @@
  * the rights to redistribute these changes.
  */

-#ifNCPUS > 1
-
-#include 
-
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
 #include 
 #include 
 #include 

 #include 
 #include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 

+#include 
+#include 
+
 /*
  * The i386 needs an interrupt stack to keep the PCB stack from being
  * overrun by interrupts.  All interrupt stacks MUST lie at lower addresses
@@ -52,20 +63,35 @@
 /*
  * Addresses of bottom and top of interrupt stacks.
  */
-vm_offset_tinterrupt_stack[NCPUS];
 vm_offset_ti

[PATCH 08/12 gnumach] smp: Deassert IPI 251 as part of sequence

2023-01-31 Thread Damien Zammit 
---
 i386/i386/smp.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/i386/i386/smp.c b/i386/i386/smp.c
index c351efaa..acf69d21 100644
--- a/i386/i386/smp.c
+++ b/i386/i386/smp.c
@@ -60,7 +60,11 @@ void smp_pmap_update(unsigned apic_id)
 pause_memory;
 } while(lapic->icr_low.delivery_status == SEND_PENDING);

-printf("done\n");
+apic_send_ipi(NO_SHORTHAND, FIXED, PHYSICAL, DE_ASSERT, EDGE, 
CALL_SINGLE_FUNCTION_BASE, apic_id);
+
+do {
+pause_memory;
+} while(lapic->icr_low.delivery_status == SEND_PENDING);

 cpu_intr_restore(flags);
 }
--
2.34.1

[PATCH 07/12 gnumach] Always use directed EOI and disable focus

2023-01-31 Thread Damien Zammit 
---
 i386/i386/apic.c | 4 +++-
 i386/i386at/ioapic.c | 9 -
 2 files changed, 3 insertions(+), 10 deletions(-)

diff --git a/i386/i386/apic.c b/i386/i386/apic.c
index 891ce288..ff7ba3e2 100644
--- a/i386/i386/apic.c
+++ b/i386/i386/apic.c
@@ -304,7 +304,9 @@ lapic_enable(void)

 /* Enable LAPIC to send or recieve IPI/SIPIs */
 dummy = lapic->spurious_vector.r;
-lapic->spurious_vector.r = dummy | LAPIC_ENABLE;
+lapic->spurious_vector.r = IOAPIC_SPURIOUS_BASE
+| LAPIC_ENABLE_DIRECTED_EOI
+| LAPIC_ENABLE;

 lapic->error_status.r = 0;

diff --git a/i386/i386at/ioapic.c b/i386/i386at/ioapic.c
index d4269ef0..003690ed 100644
--- a/i386/i386at/ioapic.c
+++ b/i386/i386at/ioapic.c
@@ -333,15 +333,6 @@ ioapic_configure(void)
 /* Start the IO APIC receiving interrupts */
 lapic_enable();

-/* Enable IOAPIC processor focus */
-lapic->spurious_vector.r |= LAPIC_FOCUS;
-
-/* Enable directed EOI if applicable */
-if (has_irq_specific_eoi || lapic->version.r & LAPIC_HAS_DIRECTED_EOI) {
-has_irq_specific_eoi = 1;
-lapic->spurious_vector.r |= LAPIC_ENABLE_DIRECTED_EOI;
-}
-
 /* Set one-shot timer */
 lapic->divider_config.r = LAPIC_TIMER_DIVIDE_16;
 lapic->lvt_timer.r = IOAPIC_INT_BASE;
--
2.34.1

[PATCH 06/12 gnumach] linux: Skip updating jiffies on AP timer

2023-01-31 Thread Damien Zammit 
---
 linux/dev/kernel/sched.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/linux/dev/kernel/sched.c b/linux/dev/kernel/sched.c
index 2a9eeb3f..f9c52d1e 100644
--- a/linux/dev/kernel/sched.c
+++ b/linux/dev/kernel/sched.c
@@ -616,6 +616,9 @@ int linux_timer_print = 0;
 void
 linux_timer_intr (void)
 {
+  if (cpu_number() != 0)
+return;
+
   (*(unsigned long *) &jiffies)++;
   mark_bh (TIMER_BH);
   if (tq_timer)
--
2.34.1

[PATCH 05/12 gnumach] interrupt: Send EOI before handling update interrupt

2023-01-31 Thread Damien Zammit 
---
 i386/i386at/interrupt.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/i386/i386at/interrupt.S b/i386/i386at/interrupt.S
index 9f1883ac..1103b1c8 100644
--- a/i386/i386at/interrupt.S
+++ b/i386/i386at/interrupt.S
@@ -122,8 +122,8 @@ _no_eoi:
ret

 _call_single:
+   callEXT(lapic_eoi)  /* lapic EOI before the handler to 
allow extra update */
callEXT(pmap_update_interrupt) /* TODO: Allow other functions */
-   callEXT(lapic_eoi)  /* lapic EOI */
addl$24,%esp
ret
 END(interrupt)
--
2.34.1

[PATCH 04/12 gnumach] locore: Fix int stack check

2023-01-31 Thread Damien Zammit 
TODO: Return kernel_id via lookup table, not apic_id

---
 i386/i386/cpu_number.h |  7 +++
 i386/i386/locore.S | 15 +--
 2 files changed, 16 insertions(+), 6 deletions(-)

diff --git a/i386/i386/cpu_number.h b/i386/i386/cpu_number.h
index 9aef6370..a6dd47d6 100644
--- a/i386/i386/cpu_number.h
+++ b/i386/i386/cpu_number.h
@@ -35,6 +35,13 @@
 /* More-specific code must define cpu_number() and CPU_NUMBER.  */
 #ifdef __i386__
 #defineCX(addr, reg)   addr(,reg,4)
+
+#defineCPU_NUMBER(reg) \
+   movl%cs:lapic, reg  ;\
+   movl%cs:APIC_ID(reg), reg   ;\
+   shrl$24, reg;\
+
+
 #endif
 #ifdef __x86_64__
 #defineCX(addr, reg)   addr(,reg,8)
diff --git a/i386/i386/locore.S b/i386/i386/locore.S
index ff78e80d..5ac238f7 100644
--- a/i386/i386/locore.S
+++ b/i386/i386/locore.S
@@ -541,13 +541,15 @@ _kret_iret:
 trap_from_kernel:
 #ifMACH_KDB || MACH_TTD
movl%esp,%ebx   /* save current stack */
-
movl%esp,%edx   /* on an interrupt stack? */
-   and $(~(KERNEL_STACK_SIZE-1)),%edx
-   cmplEXT(int_stack_base),%edx
+
+   CPU_NUMBER(%ecx)
+   and $(~(INTSTACK_SIZE-1)),%edx
+   cmplCX(EXT(int_stack_base),%ecx),%edx
je  1f  /* OK if so */

-   CPU_NUMBER(%edx)/* get CPU number */
+   movl%ecx,%edx
+
cmplCX(EXT(kernel_stack),%edx),%esp
/* already on kernel stack? */
ja  0f
@@ -668,9 +670,10 @@ ENTRY(all_intrs)
pushl   %edx
cld /* clear direction flag */

+   CPU_NUMBER(%ecx)
movl%esp,%edx   /* on an interrupt stack? */
-   and $(~(KERNEL_STACK_SIZE-1)),%edx
-   cmpl%ss:EXT(int_stack_base),%edx
+   and $(~(INTSTACK_SIZE-1)),%edx
+   cmpl%ss:CX(EXT(int_stack_base),%ecx),%edx
je  int_from_intstack   /* if not: */

pushl   %ds /* save segment registers */
--
2.34.1

[PATCH 03/12 gnumach] Print warning on bad cpu numbering and assume BSP

2023-01-31 Thread Damien Zammit 
---
 i386/i386/apic.c   |  5 +
 i386/i386/cpu_number.c | 16 +---
 2 files changed, 18 insertions(+), 3 deletions(-)

diff --git a/i386/i386/apic.c b/i386/i386/apic.c
index e53d4749..891ce288 100644
--- a/i386/i386/apic.c
+++ b/i386/i386/apic.c
@@ -278,6 +278,11 @@ lapic_enable(void)
 cpu_intr_save(&flags);

 apic_id = apic_get_current_cpu();
+if (apic_id < 0)
+  {
+printf("apic_get_current_cpu() failed, assuming BSP\n");
+apic_id = 0;
+  }

 dummy = lapic->dest_format.r;
 lapic->dest_format.r = 0x; /* flat model */
diff --git a/i386/i386/cpu_number.c b/i386/i386/cpu_number.c
index 65d74ddc..c719d841 100644
--- a/i386/i386/cpu_number.c
+++ b/i386/i386/cpu_number.c
@@ -19,14 +19,24 @@
 #include 
 #include 
 #include 
+#include 

 #if NCPUS > 1
 int cpu_number(void)
 {
-   int kernel_id;
-   unsigned long flags;
+   int kernel_id, apic_id;

-   kernel_id = apic_get_cpu_kernel_id(apic_get_current_cpu());
+   apic_id = apic_get_current_cpu();
+   if (apic_id < 0) {
+   printf("apic_get_current_cpu() failed, assuming BSP\n");
+   apic_id = 0;
+   }
+
+   kernel_id = apic_get_cpu_kernel_id(apic_id);
+   if (kernel_id < 0) {
+   printf("apic_get_cpu_kernel_id() failed, assuming BSP\n");
+   kernel_id = 0;
+   }

return kernel_id;
 }
--
2.34.1

[PATCH 02/12 gnumach] Add cpu_number and cpuboot

2023-01-31 Thread Damien Zammit 
I addressed most of the previous review.
MSRs are easier to set in asm so I have left it in.

---
 i386/i386/cpu_number.c |  33 +
 i386/i386/cpuboot.S| 164 +
 2 files changed, 197 insertions(+)
 create mode 100644 i386/i386/cpu_number.c
 create mode 100644 i386/i386/cpuboot.S

diff --git a/i386/i386/cpu_number.c b/i386/i386/cpu_number.c
new file mode 100644
index ..65d74ddc
--- /dev/null
+++ b/i386/i386/cpu_number.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2022 Free Software Foundation, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#if NCPUS > 1
+int cpu_number(void)
+{
+   int kernel_id;
+   unsigned long flags;
+
+   kernel_id = apic_get_cpu_kernel_id(apic_get_current_cpu());
+
+   return kernel_id;
+}
+#endif
diff --git a/i386/i386/cpuboot.S b/i386/i386/cpuboot.S
new file mode 100644
index ..4a5823be
--- /dev/null
+++ b/i386/i386/cpuboot.S
@@ -0,0 +1,164 @@
+/*
+ * Copyright (c) 2022 Free Software Foundation, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define AP_BOOT_ADDR   0x7000
+#define M(addr)(addr - apboot + AP_BOOT_ADDR)
+#define CR0_CLEAR_FLAGS_CACHE_ENABLE   (CR0_CD | CR0_NW)
+#define CR0_SET_FLAGS  (CR0_CLEAR_FLAGS_CACHE_ENABLE | CR0_PE)
+#define CR0_CLEAR_FLAGS (CR0_PG | CR0_AM | CR0_WP | CR0_NE | CR0_TS | CR0_EM | 
CR0_MP)
+#define BOOT_CS0x8
+#define BOOT_DS0x10
+
+.text
+
+.align 16
+apboot_idt_ptr:
+   .long 0
+.align 16
+   .word 0
+apboot_gdt_descr:
+   .word 3*8+7
+   .long apboot_gdt - KERNELBASE
+.align 16
+apboot_gdt:
+   /* NULL segment */
+   .quad 0
+   /* KERNEL_CS */
+   .word 0x /* Segment limit first 0-15 bits*/
+   .word (-KERNELBASE) & 0x /*Base first 0-15 bits*/
+   .byte ((-KERNELBASE) >> 16) & 0xff /*Base 16-23 bits */
+   .byte (ACC_P | ACC_CODE_R) /*Access byte */
+   .byte 0xcf /* High 4 bits */
+   .byte ((-KERNELBASE) >> 24) & 0xff /*Base 24-31 bits */
+   /* KERNEL_DS */
+   .word 0x /*Segment limit */
+   .word (-KERNELBASE) & 0x /*Base first 0-15 bits*/
+   .byte ((-KERNELBASE) >> 16) & 0xff
+   .byte (ACC_P | ACC_DATA_W) /*Access byte*/
+   .byte 0xcf /* High 4 bits */
+   .byte ((-KERNELBASE) >> 24) & 0xff /*Base 24-31 bits */
+
+.globl apboot, apbootend
+.align 16
+.code16
+
+apboot:
+_apboot:
+   cli
+   xorl%eax, %eax
+   movl%eax, %cr3
+   mov %ax, %ds
+   mov %ax, %es
+   mov %ax, %fs
+   mov %ax, %gs
+   mov %ax, %ss
+
+   lgdtM(gdt_descr_tmp)
+
+   movl%cr0, %eax
+   andl$~CR0_CLEAR_FLAGS, %eax
+   orl $CR0_SET_FLAGS, %eax
+   movl%eax, %cr0
+
+   ljmp$BOOT_CS, $M(0f)
+0:
+   .code32
+   movw$BOOT_DS, %ax
+   movw%ax, %ds
+   movw%ax, %es
+   movw%ax, %ss
+
+   lgdtl   apboot_gdt_descr - KERNELBASE
+   ljmpl   $KERNEL_CS, $1f
+1:
+   xorl%eax, %eax
+   movw%ax, %ds
+   movw%ax, %es
+   movw%ax, %fs
+   movw%ax, %gs
+   movw$KERNEL_DS, %ax
+   movw%ax, %ds
+   movw%ax, %es
+   movw%ax, %fs
+   movw%ax, %gs
+   movw%ax, %ss
+
+   /* Load null Interrupt descriptor table */
+   mov apboot_idt_ptr, %ebx
+   lidt(%ebx)
+
+   /* Enable local apic */
+   xorl%eax, %eax
+   xorl%edx, %edx
+   movl$APIC_MSR, %ecx
+   rdmsr
+   orl $APIC_MSR_ENABLE, %eax
+   andl$(~APIC_MSR_BSP), %eax
+   m

[PATCH 01/12 gnumach] i386: Fix lapic and ioapic for smp

2023-01-31 Thread Damien Zammit 
Also-by: Almudena Garcia 
---
 i386/i386/apic.c |  87 ++---
 i386/i386/apic.h | 114 ---
 i386/i386/smp.c  |  89 -
 i386/i386/smp.h  |   7 +++
 i386/i386at/ioapic.c |  97 ++--
 5 files changed, 307 insertions(+), 87 deletions(-)

diff --git a/i386/i386/apic.c b/i386/i386/apic.c
index d30084e2..e53d4749 100644
--- a/i386/i386/apic.c
+++ b/i386/i386/apic.c
@@ -19,6 +19,8 @@
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111, USA. */

 #include 
+#include 
+#include 
 #include 
 #include 
 #include 
@@ -112,7 +114,7 @@ acpi_get_irq_override(uint8_t pin)
  * apic_get_cpu_apic_id: returns the apic_id of a cpu.
  * Receives as input the kernel ID of a CPU.
  */
-uint16_t
+int
 apic_get_cpu_apic_id(int kernel_id)
 {
 if (kernel_id >= NCPUS)
@@ -121,6 +123,24 @@ apic_get_cpu_apic_id(int kernel_id)
 return apic_data.cpu_lapic_list[kernel_id];
 }

+
+/*
+ * apic_get_cpu_kernel_id: returns the kernel_id of a cpu.
+ * Receives as input the APIC ID of a CPU.
+ */
+int
+apic_get_cpu_kernel_id(uint16_t apic_id)
+{
+int i;
+
+for (i = 0; i < apic_data.ncpus; i++) {
+if (apic_data.cpu_lapic_list[i] == apic_id)
+return i;
+}
+
+return -1;
+}
+
 /* apic_get_lapic: returns a reference to the common memory address for Local 
APIC. */
 volatile ApicLocalUnit*
 apic_get_lapic(void)
@@ -158,17 +178,13 @@ apic_get_num_ioapics(void)
 /*
  * apic_get_current_cpu: returns the apic_id of current cpu.
  */
-uint16_t
+int
 apic_get_current_cpu(void)
 {
-uint16_t apic_id;
-
 if(lapic == NULL)
-apic_id = 0;
-else
-apic_id = lapic->apic_id.r;
+return -1;

-return apic_id;
+return (lapic->apic_id.r >> 24) & 0xff;
 }


@@ -235,6 +251,61 @@ void apic_print_info(void)
 }
 }

+void apic_send_ipi(unsigned dest_shorthand, unsigned deliv_mode, unsigned 
dest_mode, unsigned level, unsigned trig_mode, unsigned vector, unsigned 
dest_id)
+{
+IcrLReg icrl_values;
+IcrHReg icrh_values;
+
+icrl_values.destination_shorthand = dest_shorthand;
+icrl_values.delivery_mode = deliv_mode;
+icrl_values.destination_mode = dest_mode;
+icrl_values.level = level;
+icrl_values.trigger_mode = trig_mode;
+icrl_values.vector = vector;
+icrh_values.destination_field = dest_id;
+
+lapic->icr_high = icrh_values;
+lapic->icr_low = icrl_values;
+}
+
+void
+lapic_enable(void)
+{
+unsigned long flags;
+int apic_id;
+volatile uint32_t dummy;
+
+cpu_intr_save(&flags);
+
+apic_id = apic_get_current_cpu();
+
+dummy = lapic->dest_format.r;
+lapic->dest_format.r = 0x; /* flat model */
+dummy = lapic->logical_dest.r;
+lapic->logical_dest.r = lapic->apic_id.r;  /* target self */
+dummy = lapic->lvt_lint0.r;
+lapic->lvt_lint0.r = dummy | LAPIC_DISABLE;
+dummy = lapic->lvt_lint1.r;
+lapic->lvt_lint1.r = dummy | LAPIC_DISABLE;
+dummy = lapic->lvt_performance_monitor.r;
+lapic->lvt_performance_monitor.r = dummy | LAPIC_DISABLE;
+if (apic_id != 0)
+  {
+dummy = lapic->lvt_timer.r;
+lapic->lvt_timer.r = dummy | LAPIC_DISABLE;
+  }
+dummy = lapic->task_pri.r;
+lapic->task_pri.r = 0;
+
+/* Enable LAPIC to send or recieve IPI/SIPIs */
+dummy = lapic->spurious_vector.r;
+lapic->spurious_vector.r = dummy | LAPIC_ENABLE;
+
+lapic->error_status.r = 0;
+
+cpu_intr_restore(flags);
+}
+
 void
 lapic_eoi(void)
 {
diff --git a/i386/i386/apic.h b/i386/i386/apic.h
index 0bb1bd73..ac083d26 100644
--- a/i386/i386/apic.h
+++ b/i386/i386/apic.h
@@ -61,10 +61,99 @@ union ioapic_route_entry_union {
 struct ioapic_route_entry both;
 };

+
+/* Grateful to trasterlabs for this snippet */
+
+typedef union u_icr_low
+{
+uint32_t value[4];
+struct
+{
+uint32_t r;// FEE0 0300H - 4 bytes
+unsigned :32;  // FEE0 0304H
+unsigned :32;  // FEE0 0308H
+unsigned :32;  // FEE0 030CH
+};
+struct
+{
+unsigned vector: 8; /* Vector of interrupt. Lowest 8 bits of routine 
address */
+unsigned delivery_mode : 3;
+unsigned destination_mode: 1;
+unsigned delivery_status: 1;
+unsigned :1;
+unsigned level: 1;
+unsigned trigger_mode: 1;
+unsigned :2;
+unsigned destination_shorthand: 2;
+unsigned :12;
+};
+} IcrLReg;
+
+typedef union u_icr_high
+{
+uint32_t value[4];
+struct
+{
+uint32_t r; // FEE0 0310H - 4 bytes
+unsigned :32;  // FEE0 0314H
+unsigned :32;  // FEE0 0318H
+unsigned :32;  // FEE0 031CH
+};
+struct
+{
+unsigned :24; // FEE0 0310H - 4 bytes
+unsigned destination_field :8; /* APIC ID (in physical mode) or MDA 
(in logical) of destination processor */
+};
+} IcrHReg;
+
+
+typedef

[PATCH 00/12 gnumach] Progress on SMP with N cpus

2023-01-31 Thread Damien Zammit 
This gets us closer to a working SMP kernel without breaking our non-SMP mode.

What was tested?

- kdb, apic, ncpus=8 with -smp 1 (boots slow)
- kdb, apic, ncpus=8 with -smp 2 (hangs)
- kdb, apic, ncpus=8 with -smp 4 (hangs)
- kdb, apic, ncpus=8 with -smp 6 (hangs)
- (no options)   with -smp 1 (boots as normal)

Damien

Re: [PATCH gnumach] Define rpc_vm_size_array_t and rpc_vm_offset_array_t

2023-01-31 Thread Sergey Bugaev 
On Tue, Jan 31, 2023 at 9:08 AM Flavio Cruz  wrote:
>
> When generating stubs, Mig will will take the vm_size_array_t and define the
> input request struct using rpc_vm_size_t since the size is variable. This 
> will turn cause a mismatch
> between types (vm_size_t* vs rpc_vm_size_t*). We could also ask Mig to produce
> a prototype by using rpc_vm_size_t*, however we would need to change the 
> implementation
> of the RPC to use rpc_* types anyway since we want to avoid another allocation
> of the array.

For someone as uninitiated as myself, could you please explain the
deal with these rpc_* types? (Or point me to some docs, if they
exist...)

I understand they are related to the x64 bringup, and possibly to
running 32-bit userland on a 64-bit kernel (or to support for 32-bit
tasks communicating with 64-bit tasks?). But how are they different to
plain vm_size_t etc, and when am I supposed to use one vs the other?
Does this only concern kernel land (i.e. GNU Mach) or the userland
too?

Thanks,
Sergey