[bug #21661] Make expands command-line variable defnitions after/during every command invocation

[Robert Bogomip]

Follow-up Comment #6, bug #21661 (project make):

Aha, that explains everything. You are right of course, it's not a regression
(as I found out after digging out 3.79.1 and 3.80), so appologgies for any
aspersions cast.

Using something like "~" for the variable name on the cammand line is a
decent work around for this effect. Thankyou.


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[bug #21661] Make expands command-line variable defnitions after/during every command invocation

[Paul D. Smith]

Follow-up Comment #5, bug #21661 (project make):

Ah, now it's clear what the confusion is.  This happens because make puts
command line variable settings into the environment to be exported to the
subshell.  And, of course, before make can invoke a subshell it has to expand
all the variables that are to be exported.

See
http://www.gnu.org/software/make/manual/html_node/Variables_002fRecursion.html#Variables_002fRecursion

You can avoid this by adding an explicit "unexport var" to your makefile.

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[bug #21661] Make expands command-line variable defnitions after/during every command invocation

[Robert Bogomip]

Follow-up Comment #4, bug #21661 (project make):

> If you put "var=value" in your makefile, then the left hand side of the
variable will be re-expanded every time the variable "var" is referenced.

Fine, but I have _not_ _referenced_ var _anywhere._ Why then is it being
expanded?

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[bug #21661] Make expands command-line variable defnitions after/during every command invocation

[Paul D. Smith]

Update of bug #21661 (project make):

  Status:None => Not A Bug  
 Open/Closed:Open => Closed 

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Follow-up Comment #3:

Dave is correct: this is exactly how make should behave; it's not a
regression (because all versions of make have always behaved this way); it's
not even a bug.  Setting a variable on the command line using "var=value" is
conceptually exactly the same as having that same assignment appear at the end
of the last makefile make reads in (because the value on the command line
takes precedence over values set in the makefile).

If you put "var=value" in your makefile, then the left hand side of the
variable will be re-expanded every time the variable "var" is referenced.

As Dave suggests, you should review the difference between simple variables
and recursive variables, and/or the difference between immediate and deferred
expansion.  You can read about these topics in the "How make Reads a Makefile"
section of the manual, here:
http://www.gnu.org/software/make/manual/html_node/Reading-Makefiles.html#Reading-Makefiles

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[bug #21661] Make expands command-line variable defnitions after/during every command invocation

[Robert Bogomip]

Follow-up Comment #2, bug #21661 (project make):

I set $var on the command-line. Note that it is not mentioned _anywhere_
inside the Makefile, and yet it (or its expression) seems to be being expanded
whenever the Makefile runs a command --- _any_ and _all_ commands.

Expected behaviour? (Regression methinks.)

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[bug #21661] Make expands command-line variable defnitions after/during every command invocation

[Dave Korn]

Follow-up Comment #1, bug #21661 (project make):

As far as I can see, this is the expected and as-intended behaviour.  Try

make 'var:=$(warning hello)'

instead, and refresh your memory on the difference between immediate and
deferred expansion.


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[bug #21661] Make expands command-line variable defnitions after/during every command invocation

[Robert Bogomip]

URL:
  

 Summary: Make expands command-line variable defnitions
after/during every command invocation
 Project: make
Submitted by: bobbogo
Submitted on: Wednesday 28/11/07 at 16:43
Severity: 3 - Normal
  Item Group: Bug
  Status: None
 Privacy: Public
 Assigned to: None
 Open/Closed: Open
 Discussion Lock: Any
   Component Version: 3.81
Operating System: Any
   Fixed Release: None

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Details:

(Eh, what? I don't really know how to rationalise this.) It seems that
something like "var=def" specified on the command line will be evaluated after
each rule is run. Consider:


$ cat Makefile
tgts := 1 2 3 4 5
.PHONY: all ${tgts}
all: ${tgts}
all ${tgts}:
echo 'Commands for [EMAIL PROTECTED]'


This runs fine:


$ make
echo 'Commands for [1]'
Commands for [1]
echo 'Commands for [2]'
Commands for [2]
echo 'Commands for [3]'
Commands for [3]
echo 'Commands for [4]'
Commands for [4]
echo 'Commands for [5]'
Commands for [5]
echo 'Commands for [all]'


However, try adding a command-line definition


$ make 'var=$(warning hello)'
echo 'Commands for [1]'
make: hello
Commands for [1]
echo 'Commands for [2]'
make: hello
Commands for [2]
echo 'Commands for [3]'
make: hello
Commands for [3]
echo 'Commands for [4]'
make: hello
Commands for [4]
echo 'Commands for [5]'
make: hello
Commands for [5]
echo 'Commands for [all]'
make: hello
Commands for [all]


Make seems to be expanding the expression "var=$(warning hello)". This is
very annoying --- it precludes doing something like 'fixme=$(error urk)' on
the command-line.

Present in make-3.81-10.fc8.x86_64 on Fedora 8, the system make on MacOS
10.5.1, and the current cygwin make (all 3.81).




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