Re: RFR: 8284949: riscv: Add Zero support for the 32-bit RISC-V architecture [v2]
On Tue, 19 Apr 2022 11:22:37 GMT, Thomas Stuefe wrote: > LGTM > > Cheers, Thomas > > P.S. I assume you did not run the whole gamut of jtreg tests, right? Seems to > me there are a number of tests which would need to get adapted for riscv32. Thanks for the review, Thomas. Currently, we only test jtreg tier1 tests under test/hotspot and test/jdk. I assume it would be enough for adding riscv32 zero support? There are some tests adaptions to be done for riscv32 like [1] [2]. I guess it might be better to fix them in another PR. [1] https://github.com/openjdk/jdk/blob/72726c41829b33fd2baf5b3604cab49d39489dd2/test/lib/jdk/test/lib/Platform.java#L200-L202 [2] https://github.com/openjdk/jdk/blob/72726c41829b33fd2baf5b3604cab49d39489dd2/test/lib-test/jdk/test/lib/TestMutuallyExclusivePlatformPredicates.java#L46-L49 - PR: https://git.openjdk.java.net/jdk/pull/8284
Re: RFR: 8284949: riscv: Add Zero support for the 32-bit RISC-V architecture [v2]
On Tue, 19 Apr 2022 08:47:18 GMT, Feilong Jiang wrote: >> This patch adds Zero support for the 32-bit RISC-V architecture. >> >> Additional tests: >> >> - [x] Linux zero RISCV32 cross-compilation >> - [x] Resulting binaries run on QEMU User mode without problems > > Feilong Jiang has updated the pull request incrementally with one additional > commit since the last revision: > > adjust SYS_futex define for RISCV32 Marked as reviewed by ihse (Reviewer). - PR: https://git.openjdk.java.net/jdk/pull/8284
Re: RFR: 8284949: riscv: Add Zero support for the 32-bit RISC-V architecture [v2]
On Tue, 19 Apr 2022 08:47:18 GMT, Feilong Jiang wrote: >> This patch adds Zero support for the 32-bit RISC-V architecture. >> >> Additional tests: >> >> - [x] Linux zero RISCV32 cross-compilation >> - [x] Resulting binaries run on QEMU User mode without problems > > Feilong Jiang has updated the pull request incrementally with one additional > commit since the last revision: > > adjust SYS_futex define for RISCV32 LGTM Cheers, Thomas P.S. I assume you did not run the whole gamut of jtreg tests, right? Seems to me there are a number of tests which would need to get adapted for riscv32. - Marked as reviewed by stuefe (Reviewer). PR: https://git.openjdk.java.net/jdk/pull/8284
Re: RFR: 8284949: riscv: Add Zero support for the 32-bit RISC-V architecture [v2]
> This patch adds Zero support for the 32-bit RISC-V architecture. > > Additional tests: > > - [x] Linux zero RISCV32 cross-compilation > - [x] Resulting binaries run on QEMU User mode without problems Feilong Jiang has updated the pull request incrementally with one additional commit since the last revision: adjust SYS_futex define for RISCV32 - Changes: - all: https://git.openjdk.java.net/jdk/pull/8284/files - new: https://git.openjdk.java.net/jdk/pull/8284/files/a26633b2..dae310f9 Webrevs: - full: https://webrevs.openjdk.java.net/?repo=jdk=8284=01 - incr: https://webrevs.openjdk.java.net/?repo=jdk=8284=00-01 Stats: 2 lines in 1 file changed: 0 ins; 0 del; 2 mod Patch: https://git.openjdk.java.net/jdk/pull/8284.diff Fetch: git fetch https://git.openjdk.java.net/jdk pull/8284/head:pull/8284 PR: https://git.openjdk.java.net/jdk/pull/8284
Re: RFR: 8284949: riscv: Add Zero support for the 32-bit RISC-V architecture [v2]
On Mon, 18 Apr 2022 15:27:07 GMT, Yadong Wang wrote: >> Feilong Jiang has updated the pull request incrementally with one additional >> commit since the last revision: >> >> adjust SYS_futex define for RISCV32 > > src/hotspot/os/linux/waitBarrier_linux.cpp line 44: > >> 42: #ifndef SYS_futex >> 43: #if defined(RISCV32) && defined(SYS_futex_time64) >> 44: #define SYS_futex SYS_futex_time64 > > Should it be better to check SYS_futex and SYS_futex_time64 when RISCV32 > defined? Fixed. - PR: https://git.openjdk.java.net/jdk/pull/8284
