Re: [casper] KATCP maximum segment size for transmition and struct.pack/unpack format
Hi Jason, Thanks for the reply. The problem that I have when trying to implement this library on the PIC32 is that on the compiler that I use there is no file. Also there are some functions defined inside this .h files that are missing. Do you know where can I get these special .h files that were used with this lightweight processors? Best regards. On Mon, Jan 26, 2015 at 11:35 AM, Jason Manley wrote: > There is a C-based KATCP library that has been used successfully on > lightweight (8-bit) processors in the past. It might make your life a > little easier, as the parsing and everything's already taken care of. Try > this: https://github.com/ska-sa/katcp_devel > > Jason Manley > CBF Manager > SKA-SA > > Cell: +27 82 662 7726 > Work: +27 21 506 7300 > > On 26 Jan 2015, at 15:50, Pablo Vasquez wrote: > > > Hi, > > > > I'm trying to get a 32 bits PIC controller to work with a ROACH. I'm > establishing communication through a standard TCP connection and getting > data from a socket opened between the PIC and the ROACH. About this I have > two questions: > > > > 1.- What is the package size, also know as maximum segment size, that > the ROACH/KATCP uses for transmission over the LAN port? > > I need to know this so I can work with the same segment size on both > platforms and get proper data flow synchronization. > > > > > > 2.- Do you know where can I find more info about the way struct.pack > works? > > I need to "unpack" the data coming in the string from the ROACH, but > since I have no python libraries on the PIC I need to handle the unpacking > myself. Looking directly at the data I seem to recognize some patterns > (i.e. "/0" at the end of each integer per channel) but this patterns are > not behaving the same through the whole string. > > > > Any hints will help. > > > > Best regards. > > > > -- > > Pablo Vasquez > > Ingeniero Eléctrico > > DAS Universidad de Chile > > (+562)29771119 > > -- Pablo Vasquez Ingeniero Eléctrico DAS Universidad de Chile (+562)29771119
Re: [casper] sync ADCs in ROACH2
PS: if you're trying to interleave two ADCs, I would imagine regardless of getting the samples in sync, for best results you would need to implement a way to calibrate <<1 sample offsets anyway, which might mandate some signal injection system anyway... Though I've never tried to do this, so really I'm just thinking out loud :)
Re: [casper] sync ADCs in ROACH2
Hi Franco, The sync inputs are usually used to synchronise multiple boards. If you feed an lvttl signal into the sync input of the adc5g, it will emerge from the sync output of the yellow block. Usually people drive this signal with a pulse per second signal from a GPS, and use the resulting simulink signal to synchronise their logic. Trying to sync 2 ADCs perfectly is a bit tricky though. Unless the adc5g interface has changed since I last used it (which is possible), every time you reprogram your board, the latency of the ADC samples arriving to simulink is liable to change and might not be the same for both ADC cards. I *think* that the sync signal follows the ADC data through the interface's FIFOs, which means you can compensate for some of this variable latency using this sync. However, I don't think you'll be able to get the alignment of ADC streams better than 16 ADC clocks (one FPGA clock). Usually this isn't a problem - a correlator can usually fix these small offsets in software after taking data, and they don't change once you start running your system. Personally, if you need perfect real-time alignment, I would consider injecting some test signal into both adcs and correlating their digital streams to measure their relative phase differences. Perhaps someone else has a better / different answer. I know people have worried about precision ADC synchronisation for other ADCs before, but I don't know what solutions have been proposed or implemented in the past. Cheers, Jack On Thu, 29 Jan 2015 10:19 pm Franco wrote: > Hi CASPER community, > I'm working with ROACH 2 and I need to synchronize the two ADC so that > both take samples at the same instant of time. Does anybody know how can I > achieve this synchronization? > > I've noticed that that the Simulink block model for these ADCs (adc5g), > doesn't have the option of using them in interleave mode in the block > parameters, contrary to ROACH1 ADC blocks (adc_083000x2). > > I've also noticed that the ADC boards have a SYNC input, but I don't know > how to use it. > > Thanks, > Franco > > -- > Franco Curotto > Estudiante de Ingeniería Civil Eléctrica > Facultad de Ciencias Físicas y Matemáticas > Universidad de Chile >
