Re: [casper] How to use the qdr_transpose and qdr_ct blocks?
Hi Chenwei, I had a look at your model - the error will go away if you select the enable CPU interface option in your qdr yellow blocks. Regardless of your error, enabling the cpu interface is necessary because it is used for calibrating the qdr on roach2 (this was not the case on roach1) using the script in the mlib_devel repo. Note that currently calibrating the qdr requires software writes to occur in the top half of the memory without being interfered with by the fabric (aka simulink) qdr interface. QDR calibration will fail if you attempt to calibrate whilst the fabric is writing to the top half of the qdr memory space, so when using more than 20 bits of the address line, you'll need a way to halt the simulink interface during calibration. Tomorrow I'll try and modify the qdr controller so that it can override the simulink interface during calibration, since currently this is an unnecessary user hassle. Cheers, Jack On 8 June 2015 at 10:38, Chenwei Cai caichenwei1...@gmail.com wrote: Hi Jack, I have encountered the same problem with Xilinx 14.7. See the log, ERROR:PhysDesignRules:1763 - Issue with pin connections and/or configuration on block:qdr1_controller/qdr1_controller/qdrc_infrastructure_inst/IODELAY_sa20 :IODELAYE1_IODELAYE1. For DELAY_SRC IO or O programming the ODATAIN input pins of IODELAYE1 must be connected. ERROR:Bitgen:25 - DRC detected 1 errors and 63 warnings. Please see the previously displayed individual error or warning messages for more details. === Flow run time summary: (01:08:07 seconds total) System update00:00:00 Design Rules Check...00:00:00 Xilinx System Generator..00:52:02 Base system copy.00:00:00 IP creation..00:00:00 EDK files creation...00:00:05 IP elaboration...00:00:00 Software creation00:00:00 EDK/ISE backend..00:15:58 === Maybe I truly need your help on this. And here is my model, https://www.dropbox.com/s/oiawxtux7syt0jv/fft_corner_turner_v4_nuevo.slx?dl=0 . There is one self-defined block, filt_sample, within the model, which can be obtained an added through this url, https://www.dropbox.com/sh/qckqor5hw8if0rv/AAB_SGyCoBsgDHk-8YfpPKlma?dl=0 . Thanks for your help! On Sat, Jun 6, 2015 at 3:43 AM, Jack Hickish jackhick...@gmail.com wrote: no rush - let me know how the compile goes! cheers jack On 5 June 2015 at 23:24, Chenwei Cai caichenwei1...@gmail.com wrote: Sure Jack, but I have to send that to you on Monday, because that is not in my personal computer. I have installed Xilinx 14.7 on that computer and the model is being compiled now. El sábado, 6 de junio de 2015, Jack Hickish jackhick...@gmail.com escribió: in fact, can you send me your design and i'll check it works on 14.7. Some of the warnings you have are a bit concerning but i think they might just be related to some bit slicing you're doing in your model. Thanks, Jack On 5 June 2015 at 13:06, Jack Hickish jackhick...@gmail.com wrote: Hi Chenwei, I'll fix the verilog anyway to get rid of that erro, but I think you'll find that if you use 14.7 the error will go away. In any case, 14.7 is the last version of ISE that Xilinx will release, so it's the one we're going to target in our libraries - it might be a good idea to upgrade your toolflow for this reason alone. Cheers, Jack On Fri, 5 Jun 2015 at 12:57 Chenwei Cai caichenwei1...@gmail.com wrote: Hi Jack, I am using Xilinx 14.5. On Fri, Jun 5, 2015 at 4:55 PM, Jack Hickish jackhick...@gmail.com wrote: Hi Chenwei, What version of the Xilinx tools are you using? I think this is easy to fix, but I'm surprised I didn't see this error when I compiled my test models. Cheers, Jack On Fri, 5 Jun 2015 at 12:02 Chenwei Cai caichenwei1...@gmail.com wrote: Thanks Jack, The qdr_transpose seems to work appropriately now. And I am now using the qdr_transpose block to construct my model which will be executed with ROACH II, as you can check out in the following url: https://www.dropbox.com/s/1wcz0lhmjgcuwua/Screenshot%20from%202015-06-05%2015%3A35%3A44.png?dl=0. The library I am using is the one Jack merged last week ( http://www.mail-archive.com/casper@lists.berkeley.edu/msg05947.html ). The compile goes smoothly, only to find an error at the last of compile. See the log below, which records the last part of compile. Running DRC. WARNING:PhysDesignRules:367 - The signal fft_corner_turner_v4_nuevo_asiaa_adc5g/fft_corner_turner_v4_nuevo_asiaa_adc5 g/fifo_din_buf181 is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal fft_corner_turner_v4_nuevo_asiaa_adc5g/fft_corner_turner_v4_nuevo_asiaa_adc5 g/fifo_din_buf183 is incomplete. The signal does
Re: [casper] How to use the qdr_transpose and qdr_ct blocks?
Hi Jack, Yes, it works now! I have obtained the .bof file from the new compilation. Thanks so much for your suggestions and help. I will try to calibrate qdr with the script you provided in my next step. Best Regards Chenwei CAI Email: caichenwei1...@pku.edu.cn On Tue, Jun 9, 2015 at 4:24 AM, Jack Hickish jackhick...@gmail.com wrote: Hi Chenwei, I had a look at your model - the error will go away if you select the enable CPU interface option in your qdr yellow blocks. Regardless of your error, enabling the cpu interface is necessary because it is used for calibrating the qdr on roach2 (this was not the case on roach1) using the script in the mlib_devel repo. Note that currently calibrating the qdr requires software writes to occur in the top half of the memory without being interfered with by the fabric (aka simulink) qdr interface. QDR calibration will fail if you attempt to calibrate whilst the fabric is writing to the top half of the qdr memory space, so when using more than 20 bits of the address line, you'll need a way to halt the simulink interface during calibration. Tomorrow I'll try and modify the qdr controller so that it can override the simulink interface during calibration, since currently this is an unnecessary user hassle. Cheers, Jack On 8 June 2015 at 10:38, Chenwei Cai caichenwei1...@gmail.com wrote: Hi Jack, I have encountered the same problem with Xilinx 14.7. See the log, ERROR:PhysDesignRules:1763 - Issue with pin connections and/or configuration on block:qdr1_controller/qdr1_controller/qdrc_infrastructure_inst/IODELAY_sa20 :IODELAYE1_IODELAYE1. For DELAY_SRC IO or O programming the ODATAIN input pins of IODELAYE1 must be connected. ERROR:Bitgen:25 - DRC detected 1 errors and 63 warnings. Please see the previously displayed individual error or warning messages for more details. === Flow run time summary: (01:08:07 seconds total) System update00:00:00 Design Rules Check...00:00:00 Xilinx System Generator..00:52:02 Base system copy.00:00:00 IP creation..00:00:00 EDK files creation...00:00:05 IP elaboration...00:00:00 Software creation00:00:00 EDK/ISE backend..00:15:58 === Maybe I truly need your help on this. And here is my model, https://www.dropbox.com/s/oiawxtux7syt0jv/fft_corner_turner_v4_nuevo.slx?dl=0 . There is one self-defined block, filt_sample, within the model, which can be obtained an added through this url, https://www.dropbox.com/sh/qckqor5hw8if0rv/AAB_SGyCoBsgDHk-8YfpPKlma?dl=0 . Thanks for your help! On Sat, Jun 6, 2015 at 3:43 AM, Jack Hickish jackhick...@gmail.com wrote: no rush - let me know how the compile goes! cheers jack On 5 June 2015 at 23:24, Chenwei Cai caichenwei1...@gmail.com wrote: Sure Jack, but I have to send that to you on Monday, because that is not in my personal computer. I have installed Xilinx 14.7 on that computer and the model is being compiled now. El sábado, 6 de junio de 2015, Jack Hickish jackhick...@gmail.com escribió: in fact, can you send me your design and i'll check it works on 14.7. Some of the warnings you have are a bit concerning but i think they might just be related to some bit slicing you're doing in your model. Thanks, Jack On 5 June 2015 at 13:06, Jack Hickish jackhick...@gmail.com wrote: Hi Chenwei, I'll fix the verilog anyway to get rid of that erro, but I think you'll find that if you use 14.7 the error will go away. In any case, 14.7 is the last version of ISE that Xilinx will release, so it's the one we're going to target in our libraries - it might be a good idea to upgrade your toolflow for this reason alone. Cheers, Jack On Fri, 5 Jun 2015 at 12:57 Chenwei Cai caichenwei1...@gmail.com wrote: Hi Jack, I am using Xilinx 14.5. On Fri, Jun 5, 2015 at 4:55 PM, Jack Hickish jackhick...@gmail.com wrote: Hi Chenwei, What version of the Xilinx tools are you using? I think this is easy to fix, but I'm surprised I didn't see this error when I compiled my test models. Cheers, Jack On Fri, 5 Jun 2015 at 12:02 Chenwei Cai caichenwei1...@gmail.com wrote: Thanks Jack, The qdr_transpose seems to work appropriately now. And I am now using the qdr_transpose block to construct my model which will be executed with ROACH II, as you can check out in the following url: https://www.dropbox.com/s/1wcz0lhmjgcuwua/Screenshot%20from%202015-06-05%2015%3A35%3A44.png?dl=0. The library I am using is the one Jack merged last week ( http://www.mail-archive.com/casper@lists.berkeley.edu/msg05947.html ). The compile goes smoothly, only to find an error at the last of compile. See the log below, which records the last part of compile. Running DRC. WARNING:PhysDesignRules:367 -
Re: [casper] How to use the qdr_transpose and qdr_ct blocks?
Hi Chenwei et al. Commit 082b13caee in the casper-astro-soak-test branch now allows calibration of QDRs even when the fabric is writing to the whole QDR memory space. It does this my allowing the software interface to disable simulink writes whilst calibration is taking place. To use this functionality, you'll need to use both the updated pcore and calibration software in this commit. Cheers, Jack On Tue, 9 Jun 2015 at 10:00 Chenwei Cai caichenwei1...@gmail.com wrote: Hi Jack, Yes, it works now! I have obtained the .bof file from the new compilation. Thanks so much for your suggestions and help. I will try to calibrate qdr with the script you provided in my next step. Best Regards Chenwei CAI Email: caichenwei1...@pku.edu.cn On Tue, Jun 9, 2015 at 4:24 AM, Jack Hickish jackhick...@gmail.com wrote: Hi Chenwei, I had a look at your model - the error will go away if you select the enable CPU interface option in your qdr yellow blocks. Regardless of your error, enabling the cpu interface is necessary because it is used for calibrating the qdr on roach2 (this was not the case on roach1) using the script in the mlib_devel repo. Note that currently calibrating the qdr requires software writes to occur in the top half of the memory without being interfered with by the fabric (aka simulink) qdr interface. QDR calibration will fail if you attempt to calibrate whilst the fabric is writing to the top half of the qdr memory space, so when using more than 20 bits of the address line, you'll need a way to halt the simulink interface during calibration. Tomorrow I'll try and modify the qdr controller so that it can override the simulink interface during calibration, since currently this is an unnecessary user hassle. Cheers, Jack On 8 June 2015 at 10:38, Chenwei Cai caichenwei1...@gmail.com wrote: Hi Jack, I have encountered the same problem with Xilinx 14.7. See the log, ERROR:PhysDesignRules:1763 - Issue with pin connections and/or configuration on block:qdr1_controller/qdr1_controller/qdrc_infrastructure_inst/IODELAY_sa20 :IODELAYE1_IODELAYE1. For DELAY_SRC IO or O programming the ODATAIN input pins of IODELAYE1 must be connected. ERROR:Bitgen:25 - DRC detected 1 errors and 63 warnings. Please see the previously displayed individual error or warning messages for more details. === Flow run time summary: (01:08:07 seconds total) System update00:00:00 Design Rules Check...00:00:00 Xilinx System Generator..00:52:02 Base system copy.00:00:00 IP creation..00:00:00 EDK files creation...00:00:05 IP elaboration...00:00:00 Software creation00:00:00 EDK/ISE backend..00:15:58 === Maybe I truly need your help on this. And here is my model, https://www.dropbox.com/s/oiawxtux7syt0jv/fft_corner_turner_v4_nuevo.slx?dl=0 . There is one self-defined block, filt_sample, within the model, which can be obtained an added through this url, https://www.dropbox.com/sh/qckqor5hw8if0rv/AAB_SGyCoBsgDHk-8YfpPKlma?dl=0 . Thanks for your help! On Sat, Jun 6, 2015 at 3:43 AM, Jack Hickish jackhick...@gmail.com wrote: no rush - let me know how the compile goes! cheers jack On 5 June 2015 at 23:24, Chenwei Cai caichenwei1...@gmail.com wrote: Sure Jack, but I have to send that to you on Monday, because that is not in my personal computer. I have installed Xilinx 14.7 on that computer and the model is being compiled now. El sábado, 6 de junio de 2015, Jack Hickish jackhick...@gmail.com escribió: in fact, can you send me your design and i'll check it works on 14.7. Some of the warnings you have are a bit concerning but i think they might just be related to some bit slicing you're doing in your model. Thanks, Jack On 5 June 2015 at 13:06, Jack Hickish jackhick...@gmail.com wrote: Hi Chenwei, I'll fix the verilog anyway to get rid of that erro, but I think you'll find that if you use 14.7 the error will go away. In any case, 14.7 is the last version of ISE that Xilinx will release, so it's the one we're going to target in our libraries - it might be a good idea to upgrade your toolflow for this reason alone. Cheers, Jack On Fri, 5 Jun 2015 at 12:57 Chenwei Cai caichenwei1...@gmail.com wrote: Hi Jack, I am using Xilinx 14.5. On Fri, Jun 5, 2015 at 4:55 PM, Jack Hickish jackhick...@gmail.com wrote: Hi Chenwei, What version of the Xilinx tools are you using? I think this is easy to fix, but I'm surprised I didn't see this error when I compiled my test models. Cheers, Jack On Fri, 5 Jun 2015 at 12:02 Chenwei Cai caichenwei1...@gmail.com wrote: Thanks Jack, The qdr_transpose seems to work appropriately now. And I am now using the qdr_transpose block to construct my model which
