Re: [casper] To disable the PAR timing check:

[isaacjpl]

Hi CASPER team,

Thanks to everybody for the suggestions. Finally the problem has been
solved. This a typical error when you have timing error:


“ERROR: 1 constraint not met.
PAR could not meet all timing constraints. A bitstream will not be
generated.”

It can be generated for different delays in the design, and it is possible
to solved adding strategically other delays ….but it not was the case.

Thanks to one member of JPL called Ryan or for my Super Ryan checking the
system.twr report saw a very big problem in the design “high value for the
fanout of about 256” it was the real problem.


Slack:  -0.516ns (requirement - (data path - clock path
skew + uncertainty))
  Requirement:  4.000ns
  Data Path Delay:  4.481ns (Levels of Logic = 1)
  Clock Path Skew:  -0.035ns (-0.123 - -0.088)
  Source Clock: adc0_clk rising at 0.000ns
  Destination Clock:adc0_clk rising at 4.000ns
  Clock Uncertainty:0.000ns


   Logical Resource(s)
-  ---
SLICE_X89Y76.YQ  Tcko  0.370  
   
./latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp

SLICE_X44Y98.G4  net (fanout=265)  2.453
- 
---
Total  4.481ns (0.908ns logic,
3.573ns route)
   (20.3% logic, 79.7%
route)

Now this signal does not feed a lot of gates directly, if not thought
different buffers to obtain  a suitable fanout.

So if you have timing errors, have a look to the fanout.

Thanks very much to the CASPER community for the help and especially to Ryan.

Isaac

[casper] To disable the PAR timing check:

[isaacjpl]

Hi CASPER team,

I am working with the iBOB FPGA at 250 MHz and two iADCs at 1000 GHz in a
correlator project.
In the compilation I have a timing error


ERROR: 1 constraint not met.

PAR could not meet all timing constraints. A bitstream will not be generated.

To disable the PAR timing check:

1 Disable the Treat timing closure failure as error option from the
Project Options dialog in XPS.

OR

2 Type following at the XPS prompt:
XPS% xset enable_par_timing_error 0

I have read lot of documents and everybody said that is better solve the
problem adding delays  and no disable the PAR timing check, but a like
check this behavior.
To do this I go to the Xilinx Platform Studio and open the file
system.xmp. Then I go to Project  Project Options Hierarchy and Flow
and unselected the “Treat timing closure failure as an error” and finally
I save the project.
Then execute again the bee_xps command in Matlab for the new compilation
but I obtain the same error. Then go to check the state of the option of 
“Treat timing closure failure as an error” and it appear selected again.
It’s like the bee_xps select automatically this option and I do not how
unselected.
Do you have any insights of this?
Thanks a lot,
Isaac