Re: [casper] Simple clk divider
Thanks Glen - I can see that will work. On Wed, Nov 13, 2013 at 2:41 PM, G Jones wrote: > Usually people just slice the bit you want off a counter. To select > the bit using a software register, just use the software register as > the select for a mux. Or use the software register as a bit mask and > AND it with the counter, then use the output of a relational == 0 as > your divided counter. > > On Wed, Nov 13, 2013 at 5:38 PM, Ross Williamson > wrote: >> Hi All, >> >> I suspect this is really simple but I just cannot get this to work in >> simulink. I would like to divide the sys_clk by a factor set by a >> software register. To do this in VHDL is very simple - You setup a >> counter and invert the output when it reaches half of the required clk >> divide - the counter is then reset. >> >> The problem is trying to draw the simulink equivalent. The counter and >> relational are fairly simple but you need to be able to assign an >> initial value to the not gate but I cannot seem to be able to do this. >> >> What is the obvious thing that I'm missing here? >> >> Ross >> >> -- >> Ross Williamson >> Research Scientist - Sub-mm Group >> California Institute of Technology >> 626-395-2647 (office) >> 312-504-3051 (Cell) >> -- Ross Williamson Research Scientist - Sub-mm Group California Institute of Technology 626-395-2647 (office) 312-504-3051 (Cell)
Re: [casper] Simple clk divider
Usually people just slice the bit you want off a counter. To select the bit using a software register, just use the software register as the select for a mux. Or use the software register as a bit mask and AND it with the counter, then use the output of a relational == 0 as your divided counter. On Wed, Nov 13, 2013 at 5:38 PM, Ross Williamson wrote: > Hi All, > > I suspect this is really simple but I just cannot get this to work in > simulink. I would like to divide the sys_clk by a factor set by a > software register. To do this in VHDL is very simple - You setup a > counter and invert the output when it reaches half of the required clk > divide - the counter is then reset. > > The problem is trying to draw the simulink equivalent. The counter and > relational are fairly simple but you need to be able to assign an > initial value to the not gate but I cannot seem to be able to do this. > > What is the obvious thing that I'm missing here? > > Ross > > -- > Ross Williamson > Research Scientist - Sub-mm Group > California Institute of Technology > 626-395-2647 (office) > 312-504-3051 (Cell) >
[casper] Simple clk divider
Hi All, I suspect this is really simple but I just cannot get this to work in simulink. I would like to divide the sys_clk by a factor set by a software register. To do this in VHDL is very simple - You setup a counter and invert the output when it reaches half of the required clk divide - the counter is then reset. The problem is trying to draw the simulink equivalent. The counter and relational are fairly simple but you need to be able to assign an initial value to the not gate but I cannot seem to be able to do this. What is the obvious thing that I'm missing here? Ross -- Ross Williamson Research Scientist - Sub-mm Group California Institute of Technology 626-395-2647 (office) 312-504-3051 (Cell)
