Re: [casper] system.twx missing
I found the error. A Xilinx Accumulator block was configured with a number of bit less than the input width (just a typo), the update diagram do not report a warning/error message and the compilation went ahead till the timing check. The system.twx file in this case was missing. Thanks to all, Cheers, Andrea 2013/10/2 Andrea Mattana : > mmm yes I think that's the problem, I have read the system generator > reference manual at the delay block page and should be definitely a > problem to have big delay coupled with big data bus width. > > Thanks, > I will try i a different way and will report the improvements (hopefully). > Andrea > > 2013/10/2 Andrea Mattana : >> Thanks Jack, >> >> can be a z^-2048 delay?? >> >> >> Andrea >> >> 2013/10/2 Jack Hickish : >>> Hey Andrea, >>> >>> I think (http://www.xilinx.com/support/answers/23165.html) the ngc >>> file is all you're going to get, unless you run the compile again with >>> the XIL_TIMING_ALLOW_IMPOSSIBLE variable set to 1. >>> >>> Your error is some specific component that has impossible timing >>> constraints -- it's not just general routing difficulties. I don't >>> think it can be ADC related unless you've changed the ADC parameters >>> since your last compile. I think it has to be some block you've >>> changed the parameters of or added since your last successful compile >>> -- embedded multipliers with low latency and really large input >>> bitwidths are one example of a common block which I've seen throw this >>> error. I'm sure there are plenty of others... >>> >>> Cheers, >>> Jack >>> >>> On 2 October 2013 15:34, Andrea Mattana wrote: I'm sure, the directory is correct, because I do that very often, but in this case the system.twx is really missing. The only file readable from the timingan is a ngc file but I don't know how to investigate timing with that. Can be an issue related to the ADC or some resources ended? This is the last succesfully compilation, I have added few blocks after that: Design Summary: Number of errors: 0 Number of warnings: 2216 Slice Logic Utilization: Number of Slice Registers:34,241 out of 58,880 58% Number used as Flip Flops: 34,239 Number used as Latch-thrus: 2 Number of Slice LUTs: 28,529 out of 58,880 48% Number used as logic: 23,304 out of 58,880 39% Number using O6 output only: 17,536 Number using O5 output only: 4,428 Number using O5 and O6:1,340 Number used as Memory: 4,890 out of 24,320 20% Number used as Dual Port RAM:304 Number using O6 output only: 188 Number using O5 and O6:116 Number used as Shift Register: 4,586 Number using O6 output only: 4,586 Number used as exclusive route-thru: 335 Number of route-thrus: 4,992 Number using O6 output only: 4,747 Number using O5 output only: 241 Number using O5 and O6: 4 Slice Logic Distribution: Number of occupied Slices:12,032 out of 14,720 81% Number of LUT Flip Flop pairs used: 40,207 Number with an unused Flip Flop: 5,966 out of 40,207 14% Number with an unused LUT: 11,678 out of 40,207 29% Number of fully used LUT-FF pairs: 22,563 out of 40,207 56% Number of unique control sets: 584 Number of slice register sites lost to control set restrictions: 1,187 out of 58,8802% A LUT Flip Flop pair for this architecture represents one LUT paired with one Flip Flop within a slice. A control set is a unique combination of clock, reset, set, and enable signals for a registered element. The Slice Logic Distribution report is not meaningful if the design is over-mapped for a non-slice resource or if Placement fails. OVERMAPPING of BRAM resources should be ignored if the design is over-mapped for a non-BRAM resource or if placement fails. IO Utilization: Number of bonded IOBs: 151 out of 640 23% Number of LOCed IOBs: 151 out of 151 100% IOB Flip Flops:114 Number of bonded IPADs: 36 out of 50 72% Number of bonded OPADs: 32 out of 32 100% Specific Feature Utilization: Number of BlockRAM/FIFO: 219 out of 244 89% Number using BlockRAM only:219 Total primitives used: Number of 36
Re: [casper] system.twx missing
mmm yes I think that's the problem, I have read the system generator reference manual at the delay block page and should be definitely a problem to have big delay coupled with big data bus width. Thanks, I will try i a different way and will report the improvements (hopefully). Andrea 2013/10/2 Andrea Mattana : > Thanks Jack, > > can be a z^-2048 delay?? > > > Andrea > > 2013/10/2 Jack Hickish : >> Hey Andrea, >> >> I think (http://www.xilinx.com/support/answers/23165.html) the ngc >> file is all you're going to get, unless you run the compile again with >> the XIL_TIMING_ALLOW_IMPOSSIBLE variable set to 1. >> >> Your error is some specific component that has impossible timing >> constraints -- it's not just general routing difficulties. I don't >> think it can be ADC related unless you've changed the ADC parameters >> since your last compile. I think it has to be some block you've >> changed the parameters of or added since your last successful compile >> -- embedded multipliers with low latency and really large input >> bitwidths are one example of a common block which I've seen throw this >> error. I'm sure there are plenty of others... >> >> Cheers, >> Jack >> >> On 2 October 2013 15:34, Andrea Mattana wrote: >>> I'm sure, the directory is correct, because I do that very often, but >>> in this case the system.twx is really missing. The only file readable >>> from the timingan is a ngc file but I don't know how to investigate >>> timing with that. >>> >>> Can be an issue related to the ADC or some resources ended? This is >>> the last succesfully compilation, I have added few blocks after that: >>> >>> Design Summary: >>> Number of errors: 0 >>> Number of warnings: 2216 >>> Slice Logic Utilization: >>> Number of Slice Registers:34,241 out of 58,880 58% >>> Number used as Flip Flops: 34,239 >>> Number used as Latch-thrus: 2 >>> Number of Slice LUTs: 28,529 out of 58,880 48% >>> Number used as logic: 23,304 out of 58,880 39% >>> Number using O6 output only: 17,536 >>> Number using O5 output only: 4,428 >>> Number using O5 and O6:1,340 >>> Number used as Memory: 4,890 out of 24,320 20% >>> Number used as Dual Port RAM:304 >>> Number using O6 output only: 188 >>> Number using O5 and O6:116 >>> Number used as Shift Register: 4,586 >>> Number using O6 output only: 4,586 >>> Number used as exclusive route-thru: 335 >>> Number of route-thrus: 4,992 >>> Number using O6 output only: 4,747 >>> Number using O5 output only: 241 >>> Number using O5 and O6: 4 >>> >>> Slice Logic Distribution: >>> Number of occupied Slices:12,032 out of 14,720 81% >>> Number of LUT Flip Flop pairs used: 40,207 >>> Number with an unused Flip Flop: 5,966 out of 40,207 14% >>> Number with an unused LUT: 11,678 out of 40,207 29% >>> Number of fully used LUT-FF pairs: 22,563 out of 40,207 56% >>> Number of unique control sets: 584 >>> Number of slice register sites lost >>> to control set restrictions: 1,187 out of 58,8802% >>> >>> A LUT Flip Flop pair for this architecture represents one LUT paired with >>> one Flip Flop within a slice. A control set is a unique combination of >>> clock, reset, set, and enable signals for a registered element. >>> The Slice Logic Distribution report is not meaningful if the design is >>> over-mapped for a non-slice resource or if Placement fails. >>> OVERMAPPING of BRAM resources should be ignored if the design is >>> over-mapped for a non-BRAM resource or if placement fails. >>> >>> IO Utilization: >>> Number of bonded IOBs: 151 out of 640 23% >>> Number of LOCed IOBs: 151 out of 151 100% >>> IOB Flip Flops:114 >>> Number of bonded IPADs: 36 out of 50 72% >>> Number of bonded OPADs: 32 out of 32 100% >>> >>> Specific Feature Utilization: >>> Number of BlockRAM/FIFO: 219 out of 244 89% >>> Number using BlockRAM only:219 >>> Total primitives used: >>> Number of 36k BlockRAM used: 175 >>> Number of 18k BlockRAM used: 77 >>> Total Memory used (KB): 7,686 out of 8,784 87% >>> Number of BUFG/BUFGCTRLs: 12 out of 32 37% >>> Number used as BUFGs: 12 >>> Number of IDELAYCTRLs: 6 out of 22 27% >>> Number of BUFDSs: 2 out of 8 25%
Re: [casper] system.twx missing
Thanks Jack, can be a z^-2048 delay?? Andrea 2013/10/2 Jack Hickish : > Hey Andrea, > > I think (http://www.xilinx.com/support/answers/23165.html) the ngc > file is all you're going to get, unless you run the compile again with > the XIL_TIMING_ALLOW_IMPOSSIBLE variable set to 1. > > Your error is some specific component that has impossible timing > constraints -- it's not just general routing difficulties. I don't > think it can be ADC related unless you've changed the ADC parameters > since your last compile. I think it has to be some block you've > changed the parameters of or added since your last successful compile > -- embedded multipliers with low latency and really large input > bitwidths are one example of a common block which I've seen throw this > error. I'm sure there are plenty of others... > > Cheers, > Jack > > On 2 October 2013 15:34, Andrea Mattana wrote: >> I'm sure, the directory is correct, because I do that very often, but >> in this case the system.twx is really missing. The only file readable >> from the timingan is a ngc file but I don't know how to investigate >> timing with that. >> >> Can be an issue related to the ADC or some resources ended? This is >> the last succesfully compilation, I have added few blocks after that: >> >> Design Summary: >> Number of errors: 0 >> Number of warnings: 2216 >> Slice Logic Utilization: >> Number of Slice Registers:34,241 out of 58,880 58% >> Number used as Flip Flops: 34,239 >> Number used as Latch-thrus: 2 >> Number of Slice LUTs: 28,529 out of 58,880 48% >> Number used as logic: 23,304 out of 58,880 39% >> Number using O6 output only: 17,536 >> Number using O5 output only: 4,428 >> Number using O5 and O6:1,340 >> Number used as Memory: 4,890 out of 24,320 20% >> Number used as Dual Port RAM:304 >> Number using O6 output only: 188 >> Number using O5 and O6:116 >> Number used as Shift Register: 4,586 >> Number using O6 output only: 4,586 >> Number used as exclusive route-thru: 335 >> Number of route-thrus: 4,992 >> Number using O6 output only: 4,747 >> Number using O5 output only: 241 >> Number using O5 and O6: 4 >> >> Slice Logic Distribution: >> Number of occupied Slices:12,032 out of 14,720 81% >> Number of LUT Flip Flop pairs used: 40,207 >> Number with an unused Flip Flop: 5,966 out of 40,207 14% >> Number with an unused LUT: 11,678 out of 40,207 29% >> Number of fully used LUT-FF pairs: 22,563 out of 40,207 56% >> Number of unique control sets: 584 >> Number of slice register sites lost >> to control set restrictions: 1,187 out of 58,8802% >> >> A LUT Flip Flop pair for this architecture represents one LUT paired with >> one Flip Flop within a slice. A control set is a unique combination of >> clock, reset, set, and enable signals for a registered element. >> The Slice Logic Distribution report is not meaningful if the design is >> over-mapped for a non-slice resource or if Placement fails. >> OVERMAPPING of BRAM resources should be ignored if the design is >> over-mapped for a non-BRAM resource or if placement fails. >> >> IO Utilization: >> Number of bonded IOBs: 151 out of 640 23% >> Number of LOCed IOBs: 151 out of 151 100% >> IOB Flip Flops:114 >> Number of bonded IPADs: 36 out of 50 72% >> Number of bonded OPADs: 32 out of 32 100% >> >> Specific Feature Utilization: >> Number of BlockRAM/FIFO: 219 out of 244 89% >> Number using BlockRAM only:219 >> Total primitives used: >> Number of 36k BlockRAM used: 175 >> Number of 18k BlockRAM used: 77 >> Total Memory used (KB): 7,686 out of 8,784 87% >> Number of BUFG/BUFGCTRLs: 12 out of 32 37% >> Number used as BUFGs: 12 >> Number of IDELAYCTRLs: 6 out of 22 27% >> Number of BUFDSs: 2 out of 8 25% >> Number of CRC64s: 2 out of 16 12% >> Number of DCM_ADVs:4 out of 12 33% >> Number of DSP48Es: 233 out of 640 36% >> Number of GTP_DUALs: 8 out of 8 100% >> Number of PLL_ADVs:2 out of 6 33% >> >> Average Fanout of Non-Clock Nets:
Re: [casper] system.twx missing
Hey Andrea, I think (http://www.xilinx.com/support/answers/23165.html) the ngc file is all you're going to get, unless you run the compile again with the XIL_TIMING_ALLOW_IMPOSSIBLE variable set to 1. Your error is some specific component that has impossible timing constraints -- it's not just general routing difficulties. I don't think it can be ADC related unless you've changed the ADC parameters since your last compile. I think it has to be some block you've changed the parameters of or added since your last successful compile -- embedded multipliers with low latency and really large input bitwidths are one example of a common block which I've seen throw this error. I'm sure there are plenty of others... Cheers, Jack On 2 October 2013 15:34, Andrea Mattana wrote: > I'm sure, the directory is correct, because I do that very often, but > in this case the system.twx is really missing. The only file readable > from the timingan is a ngc file but I don't know how to investigate > timing with that. > > Can be an issue related to the ADC or some resources ended? This is > the last succesfully compilation, I have added few blocks after that: > > Design Summary: > Number of errors: 0 > Number of warnings: 2216 > Slice Logic Utilization: > Number of Slice Registers:34,241 out of 58,880 58% > Number used as Flip Flops: 34,239 > Number used as Latch-thrus: 2 > Number of Slice LUTs: 28,529 out of 58,880 48% > Number used as logic: 23,304 out of 58,880 39% > Number using O6 output only: 17,536 > Number using O5 output only: 4,428 > Number using O5 and O6:1,340 > Number used as Memory: 4,890 out of 24,320 20% > Number used as Dual Port RAM:304 > Number using O6 output only: 188 > Number using O5 and O6:116 > Number used as Shift Register: 4,586 > Number using O6 output only: 4,586 > Number used as exclusive route-thru: 335 > Number of route-thrus: 4,992 > Number using O6 output only: 4,747 > Number using O5 output only: 241 > Number using O5 and O6: 4 > > Slice Logic Distribution: > Number of occupied Slices:12,032 out of 14,720 81% > Number of LUT Flip Flop pairs used: 40,207 > Number with an unused Flip Flop: 5,966 out of 40,207 14% > Number with an unused LUT: 11,678 out of 40,207 29% > Number of fully used LUT-FF pairs: 22,563 out of 40,207 56% > Number of unique control sets: 584 > Number of slice register sites lost > to control set restrictions: 1,187 out of 58,8802% > > A LUT Flip Flop pair for this architecture represents one LUT paired with > one Flip Flop within a slice. A control set is a unique combination of > clock, reset, set, and enable signals for a registered element. > The Slice Logic Distribution report is not meaningful if the design is > over-mapped for a non-slice resource or if Placement fails. > OVERMAPPING of BRAM resources should be ignored if the design is > over-mapped for a non-BRAM resource or if placement fails. > > IO Utilization: > Number of bonded IOBs: 151 out of 640 23% > Number of LOCed IOBs: 151 out of 151 100% > IOB Flip Flops:114 > Number of bonded IPADs: 36 out of 50 72% > Number of bonded OPADs: 32 out of 32 100% > > Specific Feature Utilization: > Number of BlockRAM/FIFO: 219 out of 244 89% > Number using BlockRAM only:219 > Total primitives used: > Number of 36k BlockRAM used: 175 > Number of 18k BlockRAM used: 77 > Total Memory used (KB): 7,686 out of 8,784 87% > Number of BUFG/BUFGCTRLs: 12 out of 32 37% > Number used as BUFGs: 12 > Number of IDELAYCTRLs: 6 out of 22 27% > Number of BUFDSs: 2 out of 8 25% > Number of CRC64s: 2 out of 16 12% > Number of DCM_ADVs:4 out of 12 33% > Number of DSP48Es: 233 out of 640 36% > Number of GTP_DUALs: 8 out of 8 100% > Number of PLL_ADVs:2 out of 6 33% > > Average Fanout of Non-Clock Nets:2.16 > > Peak Memory Usage: 1931 MB > Total REAL time to MAP completion: 13 mins 41 secs > Total CPU time to MAP completion: 13 mins 33 secs > > Mapping completed.
Re: [casper] system.twx missing
I'm sure, the directory is correct, because I do that very often, but in this case the system.twx is really missing. The only file readable from the timingan is a ngc file but I don't know how to investigate timing with that. Can be an issue related to the ADC or some resources ended? This is the last succesfully compilation, I have added few blocks after that: Design Summary: Number of errors: 0 Number of warnings: 2216 Slice Logic Utilization: Number of Slice Registers:34,241 out of 58,880 58% Number used as Flip Flops: 34,239 Number used as Latch-thrus: 2 Number of Slice LUTs: 28,529 out of 58,880 48% Number used as logic: 23,304 out of 58,880 39% Number using O6 output only: 17,536 Number using O5 output only: 4,428 Number using O5 and O6:1,340 Number used as Memory: 4,890 out of 24,320 20% Number used as Dual Port RAM:304 Number using O6 output only: 188 Number using O5 and O6:116 Number used as Shift Register: 4,586 Number using O6 output only: 4,586 Number used as exclusive route-thru: 335 Number of route-thrus: 4,992 Number using O6 output only: 4,747 Number using O5 output only: 241 Number using O5 and O6: 4 Slice Logic Distribution: Number of occupied Slices:12,032 out of 14,720 81% Number of LUT Flip Flop pairs used: 40,207 Number with an unused Flip Flop: 5,966 out of 40,207 14% Number with an unused LUT: 11,678 out of 40,207 29% Number of fully used LUT-FF pairs: 22,563 out of 40,207 56% Number of unique control sets: 584 Number of slice register sites lost to control set restrictions: 1,187 out of 58,8802% A LUT Flip Flop pair for this architecture represents one LUT paired with one Flip Flop within a slice. A control set is a unique combination of clock, reset, set, and enable signals for a registered element. The Slice Logic Distribution report is not meaningful if the design is over-mapped for a non-slice resource or if Placement fails. OVERMAPPING of BRAM resources should be ignored if the design is over-mapped for a non-BRAM resource or if placement fails. IO Utilization: Number of bonded IOBs: 151 out of 640 23% Number of LOCed IOBs: 151 out of 151 100% IOB Flip Flops:114 Number of bonded IPADs: 36 out of 50 72% Number of bonded OPADs: 32 out of 32 100% Specific Feature Utilization: Number of BlockRAM/FIFO: 219 out of 244 89% Number using BlockRAM only:219 Total primitives used: Number of 36k BlockRAM used: 175 Number of 18k BlockRAM used: 77 Total Memory used (KB): 7,686 out of 8,784 87% Number of BUFG/BUFGCTRLs: 12 out of 32 37% Number used as BUFGs: 12 Number of IDELAYCTRLs: 6 out of 22 27% Number of BUFDSs: 2 out of 8 25% Number of CRC64s: 2 out of 16 12% Number of DCM_ADVs:4 out of 12 33% Number of DSP48Es: 233 out of 640 36% Number of GTP_DUALs: 8 out of 8 100% Number of PLL_ADVs:2 out of 6 33% Average Fanout of Non-Clock Nets:2.16 Peak Memory Usage: 1931 MB Total REAL time to MAP completion: 13 mins 41 secs Total CPU time to MAP completion: 13 mins 33 secs Mapping completed. See MAP report file "system_map.mrp" for details. #--# # Starting program par # par -ise ../__xps/ise/system.ise -xe n -w -ol high system_map.ncd system.ncd system.pcf #--# Release 11.4 - par L.68 (lin64) Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. PMSPEC -- Overriding Xilinx file with local file Loading device for application Rf_Device from file '5vsx95t.nph' in environment /opt/Xilinx/11.1/ISE:/opt/Xilinx/11.1/EDK. "system" is an NCD, version 3.2, device xc5vsx95t, package ff1136, speed -1 Constraints file: system.pcf. "system" is an NCD, version 3.2, device xc5vsx95t, package ff1136, speed -1 WARNING:ConstraintSystem:65 - Constraint [system.pcf(10135)] overrides constraint [system.pcf(10132)]. Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) Initializing voltage
Re: [casper] system.twx missing
> Hi all, > > I'm compiling a model file for ROACH1 but I have to solve some timing > constraints which are not met. Unfortunately, the system.twx file to > be opened with the timing analyzer which should be found in > XPS_R..BASE/implementations/ is missing. Hmm. If it got as far as the snapshot below, the .twx file should have been created. Are you looking in the directory created by the compile and not the one in the library? That is: ...//XPS_ROACH_base/implementation/system.twx and not .../mlib_devel/xps_base/XPS_ROACH_base/implementation John > > Do you have an idea? > > Cheers, > Andrea > > > > Running delay-based LUT packing... > Updating timing models... > ERROR:Pack:1653 - At least one timing constraint is impossible to meet > because >component delays alone exceed the constraint. A timing constraint > summary >below shows the failing constraints (preceded with an Asterisk (*)). > Please >use the Timing Analyzer (GUI) or TRCE (command line) with the Mapped > NCD and >PCF files to identify which constraints and paths are failing because > of the >component delays alone. If the failing path(s) is mapped to Xilinx > components >as expected, consider relaxing the constraint. If it is not mapped to >components as expected, re-evaluate your HDL and how synthesis is > optimizing >the path. To allow the tools to bypass this error, set the environment >variable XIL_TIMING_ALLOW_IMPOSSIBLE to 1. > > >For more information about the Timing Analyzer, consult the Xilinx > Timing >Analyzer Reference manual; for more information on TRCE, consult the > Xilinx >Command Line Tools User Guide "TRACE" chapter. > INFO:Timing:3386 - Intersecting Constraints found and resolved. For more >information, see the TSI report. Please consult the Xilinx Command > Line >Tools User Guide for information on generating a TSI report. > INFO:Timing:3284 - This timing report was generated using estimated delay >information. For accurate numbers, please refer to the post Place and > Route >timing report. > Number of Timing Constraints that were not applied: 3 > > Asterisk (*) preceding a constraint indicates it was not met. >This may be due to a setup or hold violation. > > -- > Constraint|Check| Worst Case > | Best Case | Timing | Timing > | |Slack > | Achievable | Errors |Score > -- > * PERIOD analysis for net "mad_corr_beam_x6 | SETUP | > -3.440ns| 9.690ns| 113| 272325 > 4_adc_fab_phase_gen/mad_corr_beam_x64_adc | HOLD| > -0.179ns||6891| 366231 > _fab_phase_gen/CLK0_BUF" derived from PE | | > ||| > RIOD analysis for net "mad_corr_beam_x64_ | | > ||| > adc/fab_clk1" derived from NET "mad_corr_ | | > ||| > beam_x64_adc/mad_corr_beam_x64_adc/x64_ad | | > ||| > c_infrastructure_inst/adc_clk_ibufds" PER | | > ||| > IOD = 4.1667 ns HIGH 50% multiplied by 1. | | > ||| > 50 to 6.250 nS and duty cycle corrected t | | > ||| > o HIGH 3.125 nS duty cycle corrected to | | > ||| >6.250 nS HIGH 3.125 nS | | > ||| > -- > * TS_mgt_clk_0 = PERIOD TIMEGRP "mgt_clk_0" | SETUP | > 3.803ns| 2.597ns| 0| 0 >156.25 MHz HIGH 50% | HOLD| > -1.513ns|| 218| 146110 > -- > * TS_mgt_clk_mult_2_b = PERIOD TIMEGRP "mgt | SETUP | > 5.500ns| 0.900ns| 0| 0 > _clk_mult_2_b" 156.25 MHz HIGH 50%| HOLD| > -0.204ns|| 18|3672 > -- > NET "mad_corr_beam_x64_adc/mad_corr_beam_ | MINLOWPULSE | > 0.566ns| 3.600ns| 0| 0 > x64_adc/x64_adc_infrastructure_inst/adc_c | | > ||| > lk_ibufds" PERIOD = 4.1667 ns HIGH 50%| | > ||| > -- > PERIOD analysis for net "mad_corr_beam_x6 | SETUP | > 5.132ns| 1.118ns| 0| 0 > 4_adc/fab_clk1" derived from NET "mad
Re: [casper] system.twx missing
The timing was so bad that it didn't get beyond the mapping stage. Follow the instructions in the error message: "Please use the Timing Analyzer (GUI) or TRCE (command line) with the Mapped NCD" so run the $XILINX/settings64.sh and then timingan and use the "open design" option to open the system_map.ncd (or something like that, I'm going from memory) in the implementation directory. Glenn On Wed, Oct 2, 2013 at 7:39 AM, Andrea Mattana wrote: > Hi all, > > I'm compiling a model file for ROACH1 but I have to solve some timing > constraints which are not met. Unfortunately, the system.twx file to > be opened with the timing analyzer which should be found in > XPS_R..BASE/implementations/ is missing. > > Do you have an idea? > > Cheers, > Andrea > > > > Running delay-based LUT packing... > Updating timing models... > ERROR:Pack:1653 - At least one timing constraint is impossible to meet because >component delays alone exceed the constraint. A timing constraint summary >below shows the failing constraints (preceded with an Asterisk (*)). Please >use the Timing Analyzer (GUI) or TRCE (command line) with the Mapped NCD > and >PCF files to identify which constraints and paths are failing because of > the >component delays alone. If the failing path(s) is mapped to Xilinx > components >as expected, consider relaxing the constraint. If it is not mapped to >components as expected, re-evaluate your HDL and how synthesis is > optimizing >the path. To allow the tools to bypass this error, set the environment >variable XIL_TIMING_ALLOW_IMPOSSIBLE to 1. > > >For more information about the Timing Analyzer, consult the Xilinx Timing >Analyzer Reference manual; for more information on TRCE, consult the Xilinx >Command Line Tools User Guide "TRACE" chapter. > INFO:Timing:3386 - Intersecting Constraints found and resolved. For more >information, see the TSI report. Please consult the Xilinx Command Line >Tools User Guide for information on generating a TSI report. > INFO:Timing:3284 - This timing report was generated using estimated delay >information. For accurate numbers, please refer to the post Place and > Route >timing report. > Number of Timing Constraints that were not applied: 3 > > Asterisk (*) preceding a constraint indicates it was not met. >This may be due to a setup or hold violation. > > -- > Constraint|Check| Worst Case > | Best Case | Timing | Timing > | |Slack > | Achievable | Errors |Score > -- > * PERIOD analysis for net "mad_corr_beam_x6 | SETUP | > -3.440ns| 9.690ns| 113| 272325 > 4_adc_fab_phase_gen/mad_corr_beam_x64_adc | HOLD| > -0.179ns||6891| 366231 > _fab_phase_gen/CLK0_BUF" derived from PE | | > ||| > RIOD analysis for net "mad_corr_beam_x64_ | | > ||| > adc/fab_clk1" derived from NET "mad_corr_ | | > ||| > beam_x64_adc/mad_corr_beam_x64_adc/x64_ad | | > ||| > c_infrastructure_inst/adc_clk_ibufds" PER | | > ||| > IOD = 4.1667 ns HIGH 50% multiplied by 1. | | > ||| > 50 to 6.250 nS and duty cycle corrected t | | > ||| > o HIGH 3.125 nS duty cycle corrected to | | > ||| >6.250 nS HIGH 3.125 nS | | > ||| > -- > * TS_mgt_clk_0 = PERIOD TIMEGRP "mgt_clk_0" | SETUP | > 3.803ns| 2.597ns| 0| 0 >156.25 MHz HIGH 50% | HOLD| > -1.513ns|| 218| 146110 > -- > * TS_mgt_clk_mult_2_b = PERIOD TIMEGRP "mgt | SETUP | > 5.500ns| 0.900ns| 0| 0 > _clk_mult_2_b" 156.25 MHz HIGH 50%| HOLD| > -0.204ns|| 18|3672 > -- > NET "mad_corr_beam_x64_adc/mad_corr_beam_ | MINLOWPULSE | > 0.566ns| 3.600ns| 0| 0 > x64_adc/x64_adc_infrastructure_inst/adc_c | | > ||| > lk_ibufds" PERIOD = 4.1667 ns HIGH 50%| | > ||| > -- > PERIO
[casper] system.twx missing
Hi all, I'm compiling a model file for ROACH1 but I have to solve some timing constraints which are not met. Unfortunately, the system.twx file to be opened with the timing analyzer which should be found in XPS_R..BASE/implementations/ is missing. Do you have an idea? Cheers, Andrea Running delay-based LUT packing... Updating timing models... ERROR:Pack:1653 - At least one timing constraint is impossible to meet because component delays alone exceed the constraint. A timing constraint summary below shows the failing constraints (preceded with an Asterisk (*)). Please use the Timing Analyzer (GUI) or TRCE (command line) with the Mapped NCD and PCF files to identify which constraints and paths are failing because of the component delays alone. If the failing path(s) is mapped to Xilinx components as expected, consider relaxing the constraint. If it is not mapped to components as expected, re-evaluate your HDL and how synthesis is optimizing the path. To allow the tools to bypass this error, set the environment variable XIL_TIMING_ALLOW_IMPOSSIBLE to 1. For more information about the Timing Analyzer, consult the Xilinx Timing Analyzer Reference manual; for more information on TRCE, consult the Xilinx Command Line Tools User Guide "TRACE" chapter. INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report. INFO:Timing:3284 - This timing report was generated using estimated delay information. For accurate numbers, please refer to the post Place and Route timing report. Number of Timing Constraints that were not applied: 3 Asterisk (*) preceding a constraint indicates it was not met. This may be due to a setup or hold violation. -- Constraint|Check| Worst Case | Best Case | Timing | Timing | |Slack | Achievable | Errors |Score -- * PERIOD analysis for net "mad_corr_beam_x6 | SETUP | -3.440ns| 9.690ns| 113| 272325 4_adc_fab_phase_gen/mad_corr_beam_x64_adc | HOLD| -0.179ns||6891| 366231 _fab_phase_gen/CLK0_BUF" derived from PE | | ||| RIOD analysis for net "mad_corr_beam_x64_ | | ||| adc/fab_clk1" derived from NET "mad_corr_ | | ||| beam_x64_adc/mad_corr_beam_x64_adc/x64_ad | | ||| c_infrastructure_inst/adc_clk_ibufds" PER | | ||| IOD = 4.1667 ns HIGH 50% multiplied by 1. | | ||| 50 to 6.250 nS and duty cycle corrected t | | ||| o HIGH 3.125 nS duty cycle corrected to | | ||| 6.250 nS HIGH 3.125 nS | | ||| -- * TS_mgt_clk_0 = PERIOD TIMEGRP "mgt_clk_0" | SETUP | 3.803ns| 2.597ns| 0| 0 156.25 MHz HIGH 50% | HOLD| -1.513ns|| 218| 146110 -- * TS_mgt_clk_mult_2_b = PERIOD TIMEGRP "mgt | SETUP | 5.500ns| 0.900ns| 0| 0 _clk_mult_2_b" 156.25 MHz HIGH 50%| HOLD| -0.204ns|| 18|3672 -- NET "mad_corr_beam_x64_adc/mad_corr_beam_ | MINLOWPULSE | 0.566ns| 3.600ns| 0| 0 x64_adc/x64_adc_infrastructure_inst/adc_c | | ||| lk_ibufds" PERIOD = 4.1667 ns HIGH 50%| | ||| -- PERIOD analysis for net "mad_corr_beam_x6 | SETUP | 5.132ns| 1.118ns| 0| 0 4_adc/fab_clk1" derived from NET "mad_co | HOLD| 0.195ns|| 0| 0 rr_beam_x64_adc/mad_corr_beam_x64_adc/x64 | MINLOWPULSE | 2.249ns| 4.000ns| 0| 0 _adc_infrastructure_inst/adc_clk_ibufds" | | ||| PERIOD = 4.1667 ns HIGH 50% multiplied b | | ||| y 1.50 to 6.250 nS and duty cycle correct | | ||| ed to HIGH 3.125 nS | | ||
