[cctalk] Re: Signetics N8220B ??
Maybe 8x2 content addressable memory? See https://bitsavers.informatik.uni-stuttgart.de/components/signetics/_dataBooks/1972_Signetics_Full_Line.pdf, page 4-3 -- Holger Von: Holm Tiffe via cctalk Gesendet: Montag, 28. August 2023 15:24 An: cctalk@classiccmp.org Cc: Holm Tiffe Betreff: [cctalk] Signetics N8220B ?? Hi guys, I have 8 "new" Chips from Signetics, they are labeled: S7536 N8220B and on the backside between the pins "8220". Does anyone know what they do? My search with google and in the 1976 Signetics Date Manual (from Bitsavers) wasn't helpful... Thanx in advance, Holm -- Technik Service u. Handel Tiffe, www.tsht.de, Holm Tiffe, Goethestrasse 15, 09569 Oederan, USt-Id: DE253710583 i...@tsht.de Tel +49 37292 709778 Mobil: 0172 8790 741
[cctalk] Re: FOSBIC Compiler
Von: Chuck Guzis via cctalk > On 7/7/23 00:43, Veit, Holger via cctalk wrote: >> Hi all, >> maybe someone here is interested in the FOSBIC (FORTRAN Simulated BASIC >> Interpretive Compiler) system. >> >> Background: This was developed, oder rather ported from UWBIC (University of >> Washington, Prog. W.H. Sharpe) in the mid 70s, by Prof Weber et al. at the >> German University of Gießen, for the purpose of teaching BASIC on their >> CDC3300 batch system. >> It is written in FORTRAN IV, and knows most of Dartmouth BASIC, including >> MAT statements and basic sequential/ISAM file handling. >> >> I have ported that, with the help to GNU gfortran, to modern Windows >> (mingw/cygwin) and Linux, so anyone may play with it. It is still a batch >> system, i.e. on has to provide the BASIC program as a file (formerly it had >> to be a card deck), and feed it into the program through stdin, as >> in "./fosbic < hello.bas | ./asa" >> The code with many examples is available at >> https://github.com/hveit01/FOSBIC, and has also found its way to >> bitsavers.org/pdf/uni-giessen. > >Does a test/validation suite exist for this thing? > >Just wondering--how does one tell if a good version has been produced? Where should a validation suite come from with such old code? There are numerous examples, partly from the accompanying text books, partly generated by myself by reverse engineering the source code, where I even found a number of bugs in the published code, as well as some quirks such as PRINT also being accepted as PRONT, due to incomplete decoding of keywords. The examples do work, but there is no warranty that it will be bug free under all circumstances. Take it or leave it as is. Holger
[cctalk] FOSBIC Compiler
Hi all, maybe someone here is interested in the FOSBIC (FORTRAN Simulated BASIC Interpretive Compiler) system. Background: This was developed, oder rather ported from UWBIC (University of Washington, Prog. W.H. Sharpe) in the mid 70s, by Prof Weber et al. at the German University of Gießen, for the purpose of teaching BASIC on their CDC3300 batch system. It is written in FORTRAN IV, and knows most of Dartmouth BASIC, including MAT statements and basic sequential/ISAM file handling. I have ported that, with the help to GNU gfortran, to modern Windows (mingw/cygwin) and Linux, so anyone may play with it. It is still a batch system, i.e. on has to provide the BASIC program as a file (formerly it had to be a card deck), and feed it into the program through stdin, as in "./fosbic < hello.bas | ./asa" The code with many examples is available at https://github.com/hveit01/FOSBIC, and has also found its way to bitsavers.org/pdf/uni-giessen. -- Regards Holger
[cctalk] Did Intel's Insite User Program Library survive?
Hi all, The PDF at https://www.bitsavers.org/pdf/intel/insite/1983_Insite_Users_Program_Library_Catalog.pdf lists various old user submitted software which could have been ordered from Intel those days. Is there anything of that archived and downloadable somewhere? Regards Holger
Re: For those with 6809 experience
Am 01.03.2020 um 00:42 schrieb Jim Brain via cctalk: Looking at the datasheet for the 6809 (specifically, the 6809E that needs incoming quadrature clock), I read that !HALT can be asserted 200nS (for 1MHz part) before falling Q and the CPU will finish the existing instruction and then go into a HALT state as long as the HALT line is low during the falling edge of Q. That's the store from the datasheet, but when I am testing it, I see that, even if I pull HALT low at the very beginning of the last cycle of an instruction, the 6809 will not acknowledge the HALT until executing the next instruction. My logic is watching for IO address $ff61. When found, it drops Q so, to start the HALT condition, I need only: lda $ff61 Not that the trigger is being performed by the code, so the current instruction (the lda) should complete and then the CPU should go into HiZ. What I see is: lda $ff61 lda $ff60 <- the next instruction executed, and THEN the CPU goes into HiZ. I can deal with this (Yes, I should just look at BS=BA=1, which tell when to safely use the bus, but I don't have access to those signals for this project), but I thought I'd see if this was known by all, or if there is something I am missing. Jim What are you trying to accomplish? I guess you are using $FF61 as a trigger to start a DMA transfer, or alike. I've seen something like this in code already, so it might have been be known in developer circles for long. The plain simple fix apparently was to add one or two NOPs after the initiating address reference. The hardware price could be an additional flipflop and another comparator. Detecting $FF61 wil arm the FF and a following NOP on databus will initiate the operation. If no NOP follows, the FF is reset.However, the latter situation should not occur when all instances of LDA $FF61 are properly followed by NOP. -- Holger
Re: Tap, tap, tap, is this working???
Am 14.12.2019 um 18:58 schrieb crufta cat via cctech: Signed up this new account exclusively for CCtech and CCchat. Hopefully its working. Why do this? I had to shut off the other subscription for spam reasons. Allison How did you manage to subscribe? I have been trying to change my subscription address for more than a year, and both web site as well as mail request have been completely ignored so far. Holger
Newcastle Connection Sources?
Hi, for some research on ancient Unix, I am interesting in finding the source code (tape, etc.) of the so-called "Newcastle connection", aka "UNIXes of the World Unite!" . See, for instance, https://pdfs.semanticscholar.org/13f8/6c18fa780031d76b80f359d6670f9f3debdc.pdf or ftp://ftp.informatik.uni-stuttgart.de/pub/cm/pcs/NewcastleConnectionR1.0_1983.pdf for details. There are a few more papers which I know as well. Does someone have the source tape or pointers to it? THX in advance -- Holger
Re: XT/370 microcode
You might look up Nick Tredennick's book "Microprocessor Logic Design: The Flowchart Method" which is sold at Amazon for an obscene price - but maybe some university library has a copy. It's focus is on a methodology for designing microcode, and it uses the design of the single chip 370 to explain it. I suppose it was a PhD thesis. The main point is that the 370 is NOT an 68000 with a different microcode; instead it is said that it implements the bus interface of the 68K in order to interface easily with existing peripherals (rather than reinventing the wheel). The internal data paths and register sets may be similar between the 68K and the 370 (actually it is quite possible that at Motorola they were aware of IBM mainframe architectures...) but that's all likely. The control unit design described in the book was completely redesigned for the purpose of describing the proposed methodology. Holger Am 12.03.2018 um 12:13 schrieb Dave Wade via cctalk: I don't suppose any one left in IBM has any knowledge of this. Perhaps no one ever did and it was all done by Motorola. Wikipedia says there were/are 2x68000 CPU's.. .. I would ask on IBM Main... http://www.cpushack.com/2013/03/22/cpu-of-the-day-ibm-micro-370/ seems to have some names.. Dave -Original Message- From: cctalk On Behalf Of Lars Brinkhoff via cctalk Sent: 12 March 2018 07:02 To: cctalk@classiccmp.org Subject: XT/370 microcode Does someone have good connections with people inside IBM? I'd like to ask about 68000 microcode for the XT/370 product.
Re: Ideas for a simple, but somewhat extendable computer bus
Am 19.11.2017 um 16:08 schrieb emanuel stiebler via cctalk: On 2017-11-18 23:48, Jim Brain wrote: > Looking at the schematic for the ECB, I cannot find any description of > the signals BAI, BAO, IEI, and IEO. Can anyone shed some light on the > function of these signals? Here again: https://en.wikipedia.org/wiki/Europe_Card_Bus I have some ECB documentation "somewhere", but I'm moving so it is in one of the 100s boxes somewhere :( But the guys on the retrobrewcomputers can help you for sure. And yes, I like ECB, it was small & simple, you still can get boards for it, and the DIN conectors I still use ... ECB is, like many similar approaches, basically Intel world, i.e. 8085, 8088, Z80 (ok, that's Zilog). It is rather tricky to adapt to the 6xxx (6502/68xx) world; and given the former Kontron et al socienty, it was basically used for a Z80 line of CPU and peripheral boards, not much else. To add another idea, why not run the IBM-XT bus on the DIN41612 connector? This is to avoid the card edge connectors. Use A+C with the classic 62 pins of the XT connector (2 are unused), and add the B pins in case to extend to the AT bus. While the XT bus is also Intel world, it has been already successfully used for 68xx (6809) multiprocessing. Read http://www.bradrodriguez.com/papers/ (section "Multiprocessing for the Impoverished..."). -- Holger
