[cctalk] Re: Microcom S-64 8085 system
Wouter de Waal via cctalk wrote: > Hi all > > I re-discovered some eurocards I found in a box at a swapmeet long ago. > > It looks like a complete 8085 system. Lots of RAM, 2K EPROM, I/O, FDC. > > The strange thing is that the EPROM is mapped at F800, the code in there > looks like 8085 code, and looks like it wants to live at F800. And there's > RAM at . > > The DIN41612 A/C 64 pin bus has provision for 16 bits data. > > Pics here http://retro.co.za/8085/Microcom/ > > Anyone maybe have more information on this? I'm curious. > > W Besides of relocating the entire ROM temporarly to 0x0 there are other possibilities, for example placing NOP's (0x0) on the data bus until the bus addresses reaching 0xf800 for the first time. This way a few extra gates and a flipflop is all what you need. On Z80 Systems I've mostly used a mechanism that enables writes to the RAM at 0x0, but the reads came from the ROM until an flipflop was set by an out instruction (and reset by Reset). Regards, Holm -- Technik Service u. Handel Tiffe, www.tsht.de, Holm Tiffe, Goethestrasse 15, 09569 Oederan, USt-Id: DE253710583 i...@tsht.de Tel +49 37292 709778 Mobil: 0172 8790 741
[cctalk] Re: Microcom S-64 8085 system
Hi Tony and all It might have run CP/M (which will run on an 8080, and therefore on an 8085). That needs RAM at location [1]. I know of CP/M, I even used CP/M (on my Apple) but I did not know it needs RAM at . That's kind of strange, since everything that ran CP/M (OK, everything -80) has vectors at 0. I guess there was a reason behind it. I see the CPU board has a jumper "F000/F800" so I guess it does something to map that address to 0 after reset. W
[cctalk] Re: Microcom S-64 8085 system
On Sun, Oct 1, 2023 at 8:38 AM Wouter de Waal via cctalk wrote: > > Hi all > > I re-discovered some eurocards I found in a box at a swapmeet long ago. > > It looks like a complete 8085 system. Lots of RAM, 2K EPROM, I/O, FDC. > > The strange thing is that the EPROM is mapped at F800, the code in there > looks like 8085 code, and looks like it wants to live at F800. And there's > RAM at . It might have run CP/M (which will run on an 8080, and therefore on an 8085). That needs RAM at location [1]. If the EPROM is mapped to F800 only (some machines mapped it to as well after a reset, this image was disabled after the processor jumped to F800 or wherever) then there might be a bit of logic to force a jump instruction onto the data bus after a reset to get the processor to run the code in the EPROM. [1] For the pedants, there were 'relocated versions of CP/M that could run on machines like an unmodified TRS-80 model 1 with ROM at location 0. These versions needed special relocated versions of all the application software and were generally pretty useless. -tony
