Re: FW: More 8085a oddities

[steven canning via cctalk]

Sorry Adrian I feel like I'm coming in at the end of the movie here . My
code pig ( software guy ) learned the hard way that you ALWAYS need to
start 8085 code with an " F3 "  (HEX ) DI disable interrupts command so
that you can have all your ducks lined up before you get an Interrupt (
whether real or imagined ) otherwise you can jump to some weird a$$ address
that will do something unwanted . Just a thought .

Best regards , Steven

On Sun, Mar 5, 2017 at 10:25 AM, Adrian Graham via cctalk <
cctalk@classiccmp.org> wrote:

> Hi folks,
>
> I didn't see the message at the bottom of this one arrive since I think I
> sent it JUST as the list software was being changed over.
>
> Gah, having just looked again I realise I've sent it from not the address
> I've subbed with. PEBCAK there :)
>
> Since then I discovered the -5V rail for the 4116s had dropped to -4.2V
> which was out of spec for both types of RAM on this box so on Chuck's
> suggestion I swapped the 560ohm resistor/zener combo that was powering this
> rail for a 79L05 regulator and the DRAMs now have all 3 voltages steady.
>
> No change in behaviour though. I'm baffled as to why the upper address bus
> doesn't blip once RESET goes high. HOLD is permanently pulled low so it's
> not that.
>
> Any suggestions?
>
> Cheers!
>
> --
> Adrian/Witchy
> Binary Dinosaurs creator/curator
> Www.binarydinosaurs.co.uk - the UK's biggest private home computer
> collection?
>
> -- Forwarded Message
> From: Adrian Graham 
> Date: Sun, 26 Feb 2017 23:34:50 +
> To: "Discussion: On-Topic and Off-Topic Posts" 
> Conversation: More  8085a oddities
> Subject: More  8085a oddities
>
> Hi folks,
>
> After a few days break I came back to my 8085a-powered phone system this
> weekend and it's decided to go on strike. By that I mean the processor
> locks
> up after only a few cycles so doesn't get as far as attempting to read
> anything, when it freezes the S0/S1/WR status lines are all high which
> shouldn't be possible since S0/S1 high should be 'Fetch' according to the
> manual, not WRITE.
>
> Vcc, RESET and clock are good and I can't see any other external signal
> which might hold the CPU. The PSU is good and putting out +5/+12/-12 as it
> should. CPU checks out in another 8085 system I forgot I had.
>
> Interestingly my analyser shows the upper half of the address bus doesn't
> change while the lower half manages a single transition, as does the ALE
> signal. From the CPU both halves of the address bus go directly to a
> 74LS373
> each which both check out OK on a breadboard circuit I made up earlier.
>
> ROMs are all OK and the lines themselves back to the LS373 and CPU check
> out
> with little resistance.
>
> I'm stumped and can't help but think this is something stupid which I'm
> overlooking. Maybe more sleep will help.
>
> Cheers!
>
> --
> Adrian/Witchy
> Binary Dinosaurs creator/curator
> Www.binarydinosaurs.co.uk - the UK's biggest private home computer
> collection?
>
> -- End of Forwarded Message
>
>
>

FW: More 8085a oddities

[Adrian Graham via cctalk]

Hi folks,

I didn't see the message at the bottom of this one arrive since I think I
sent it JUST as the list software was being changed over.

Gah, having just looked again I realise I've sent it from not the address
I've subbed with. PEBCAK there :)

Since then I discovered the -5V rail for the 4116s had dropped to -4.2V
which was out of spec for both types of RAM on this box so on Chuck's
suggestion I swapped the 560ohm resistor/zener combo that was powering this
rail for a 79L05 regulator and the DRAMs now have all 3 voltages steady.

No change in behaviour though. I'm baffled as to why the upper address bus
doesn't blip once RESET goes high. HOLD is permanently pulled low so it's
not that.

Any suggestions?

Cheers!

-- 
Adrian/Witchy
Binary Dinosaurs creator/curator
Www.binarydinosaurs.co.uk - the UK's biggest private home computer
collection?

-- Forwarded Message
From: Adrian Graham 
Date: Sun, 26 Feb 2017 23:34:50 +
To: "Discussion: On-Topic and Off-Topic Posts" 
Conversation: More  8085a oddities
Subject: More  8085a oddities

Hi folks,

After a few days break I came back to my 8085a-powered phone system this
weekend and it's decided to go on strike. By that I mean the processor locks
up after only a few cycles so doesn't get as far as attempting to read
anything, when it freezes the S0/S1/WR status lines are all high which
shouldn't be possible since S0/S1 high should be 'Fetch' according to the
manual, not WRITE.

Vcc, RESET and clock are good and I can't see any other external signal
which might hold the CPU. The PSU is good and putting out +5/+12/-12 as it
should. CPU checks out in another 8085 system I forgot I had.

Interestingly my analyser shows the upper half of the address bus doesn't
change while the lower half manages a single transition, as does the ALE
signal. From the CPU both halves of the address bus go directly to a 74LS373
each which both check out OK on a breadboard circuit I made up earlier.

ROMs are all OK and the lines themselves back to the LS373 and CPU check out
with little resistance.

I'm stumped and can't help but think this is something stupid which I'm
overlooking. Maybe more sleep will help.

Cheers!

--  
Adrian/Witchy
Binary Dinosaurs creator/curator
Www.binarydinosaurs.co.uk - the UK's biggest private home computer
collection?

-- End of Forwarded Message