Re: PDP11 I/O page memory map
> On Mar 2, 2018, at 9:11 AM, Paul Koning via cctalk > wrote: > > >> On Mar 2, 2018, at 8:37 AM, Noel Chiappa via cctalk >> wrote: >> >>> From: Jerry Weiss >> >>> Typically execution of the RESET instruction in a user program is >>> treated as a NOP >> >> Yeah, that's not documented in most PDP-11 CPU manuals, either. It's one of >> the things that makes the PDP-11 impossible to virtualize; only HALT and SPL >> trap, IIRC. M[TF]P[ID] doesn't, I think, and neither does WAIT or RT[IT], >> IIRC. > > RTI/RTT are used in the debugger, so they need to work in user mode. They > refuse to raise your privilege level, though. But an RTI in user mode that > returns to user mode is perfectly ok so it is valid. > > The move from/to previous are also valid, by deliberate design. This works > because the previous mode is explicitly encoded in the PSW, and just like the > current mode, cannot be raised by user mode RTI. It is why the kernel > usually sets current == previous == user when constructing the PSW for a > process. > > What does the Architecture handbook say about WAIT and RESET in non-kernel > modes? I don't have mine at hand unfortunately. > > paul > > In the Digital Microcomputer Processor Handbook 1979-80 edition page 280 describes the user mode restrictions on HALT, RESET. and MTPS, but nothing about WAIT. The PDP11 Handbook 1979 does not detail user mode implications for MTPS or WAIT. HALT is called out for a trap to 10 in user mode. Prevention of a "restart" in user mode is mentioned on page 182, but nothing explicit about RESET. As FritzM suggested, it appears there are fewer details in the PDP-11 Architecture Handbook (1983) for these instructions than these earlier references above.HALT trapping to 4 appears for later processors in the family differences section, but I did not see much else for this topic. Jerry
Re: PDP11 I/O page memory map
It might be interesting to make a virtual PDP-11 (simulator) that *IS* more virtualization friendly, and find out how much user code depends on the existing behavior... And then write a PDP-11 hypervisor! BUT existing PDP-11's aren't even friendly restarting after a page fault, which is required for lesser virtualization (VM), and would be necessary to simulate memory mapped devices. I remember how each new generation of MC68K processors had ever larger trap stack frames to hold internal processor state...
Re: PDP11 I/O page memory map
> On Mar 2, 2018, at 5:37 AM, Noel Chiappa via cctalk > wrote: > >> From: Jerry Weiss >> Typically execution of the RESET instruction in a user program is >> treated as a NOP > > Yeah, that's not documented in most PDP-11 CPU manuals, either. It's one of > the things that makes the PDP-11 impossible to virtualize; only HALT and SPL > trap, IIRC. M[TF]P[ID] doesn't, I think, and neither does WAIT or RT[IT], > IIRC. Re-affirming Noel's *most* from above: having been through a deep dive on the 11/45 during a restoration the last couple years, I know most of this material *is* explicit in the 11/45 processor handbook, though maybe not in the obvious places. Behavior of HALT, RESET, and SPL in all three modes is documented on page 13, in the Processor Status Word section, for example. HALT and SPL behaviors are also noted on their individual instruction pages, but the RESET behavior, strangely, is not. WAIT is permitted in supervisor and user modes on the 11/45. Current and previous mode bits in the PSW can be set but not cleared when in supervisor and user modes on the 11/45. RTI/RTT/M[FT]P[DI] function uniformly, but given this PSW behavior they can only effectively preserve or lower the processor mode, or access the address space of same or lower modes, assuming the PSW is properly setup and handled by kernel mode code. This is documented on page 24 of the processor handbook, in the Multiprogramming section. I don't recall explicit mention of the MMU reset behavior in the processor handbook, but it may be squirreled away in there somewhere... I think I absorbed that bit of critical info from the KT11-C maintenance manual when I was working through debugging the one in my /45. I am much less familiar with the documentation for later-model PDP-11s. It sounds like a some of this info may have been "sanitized" from the later handbooks? cheers! --FritzM.
Re: PDP11 I/O page memory map
> From: Paul Koning > RTI/RTT are used in the debugger, so they need to work in user mode. > They refuse to raise your privilege level, though. I understand that it has uses, but by specifying the 'failure' mode in User mode (when the contents of the current or previous modes is not User) to be 'ignore', rather than 'trap', that's one more thing that makes the PDP-11 non-virtualizable. (This choice, to ignore, instead of trap, has the same issue in other places where it's done that way, e.g. RESET.) Noel
Re: PDP11 I/O page memory map
> On Mar 2, 2018, at 8:37 AM, Noel Chiappa via cctalk > wrote: > >> From: Jerry Weiss > >> Typically execution of the RESET instruction in a user program is >> treated as a NOP > > Yeah, that's not documented in most PDP-11 CPU manuals, either. It's one of > the things that makes the PDP-11 impossible to virtualize; only HALT and SPL > trap, IIRC. M[TF]P[ID] doesn't, I think, and neither does WAIT or RT[IT], > IIRC. RTI/RTT are used in the debugger, so they need to work in user mode. They refuse to raise your privilege level, though. But an RTI in user mode that returns to user mode is perfectly ok so it is valid. The move from/to previous are also valid, by deliberate design. This works because the previous mode is explicitly encoded in the PSW, and just like the current mode, cannot be raised by user mode RTI. It is why the kernel usually sets current == previous == user when constructing the PSW for a process. What does the Architecture handbook say about WAIT and RESET in non-kernel modes? I don't have mine at hand unfortunately. paul
Re: PDP11 I/O page memory map
> From: Jerry Weiss > Typically execution of the RESET instruction in a user program is > treated as a NOP Yeah, that's not documented in most PDP-11 CPU manuals, either. It's one of the things that makes the PDP-11 impossible to virtualize; only HALT and SPL trap, IIRC. M[TF]P[ID] doesn't, I think, and neither does WAIT or RT[IT], IIRC. Noel
Re: PDP11 I/O page memory map
> On Mar 1, 2018, at 8:54 PM, Noel Chiappa via cctalk > wrote: > >> From: Charles Dickman > >> So if the I/O page is completely (all processor modes) unmapped is >> there any way to recover besides a power cycle? Does the RESET >> instruction disable the MMU? > > Interesting questions! > > The CPU manuals don't say, about the RE$ET; I just tried it on the /23 I > happen to have next to my desktop, and yes, the RESET instruction does clear > bit 0 of SSR0. > > Noel Typically execution of the RESET instruction in a user program is treated as a NOP when the MMU is enabled. What generally occurs in most OS'es is that I/O Page is mapped and unmapped dynamically based on which mode is executing. Interrupts or user program traps cause a context switch to kernel mode. When this occurs page registers with access to the I/O page defined are activated. The interrupt or trap is serviced then the OS returns to running the user mode program. At this point a switch to back to a set of page registers without I/O mapping occurs. There are OS'es that allow regular programs to map the I/O page, These are usually special purpose solutions (RT11XM) or granted only to privileged users (RSX11, TSX+). The effect of RESET to initialize the MMR0 (SSR0) register is documented in the PDP11 Handbook 1979 or the J11 Programmers Reference. I could not find it in the reference immediately below, much to my surprise. Check out Chapter 1 in the KDJ11-A CPU Module User's Guide for an overview of PDP11 memory management. This implementation was (mostly) backward compatible with PDP-11 models having 22bit , 18bit or no memory management. Jerry
Re: PDP11 I/O page memory map
> From: Charles Dickman > So if the I/O page is completely (all processor modes) unmapped is > there any way to recover besides a power cycle? Does the RESET > instruction disable the MMU? Interesting questions! The CPU manuals don't say, about the RE$ET; I just tried it on the /23 I happen to have next to my desktop, and yes, the RESET instruction does clear bit 0 of SSR0. Noel
Re: PDP11 I/O page memory map
On Thu, Mar 1, 2018 at 9:04 AM, Paul Koning via cctalk wrote: > That's true when the MMU is disabled; if so it supplies 1 bits for the upper > bits for page 7, > and zeroes for the other pages. But if the MMU is enabled, all mapping goes > through its mapping > registers, and page 7 is no longer special. By software convention, kernel > data page 7 is > configured to point to the I/O page, but that isn't required. If you wanted > to be be perverse you > could map the I/O page via page 6 and confuse a whole generation of > programmers. So if the I/O page is completely (all processor modes) unmapped is there any way to recover besides a power cycle? Does the RESET instruction disable the MMU? -chuck
Re: PDP11 I/O page memory map
Noel; Thanks for the exact info I was looking for! I knew there was a text listing of the addresses and what devices occupied those addresses. Going thru the manuals one by one was way too tedious. Thanks for explaining the 'bank switching' that is done to accommodate the larger boot roms. Suspected that was going on but didn't really know. I'm curious because I have an MXV11-AC without the boot rom, however it does have another OEM rom there that I could reprogram with the standard bootstrap. This led to the question I posted. Doug On 3/1/2018 7:00 AM, Noel Chiappa via cctalk wrote: > From: Douglas Taylor > Is there a document that describes the bank 7 memory page and what > addresses are reserved for what? Here's one I collated from a large number of DEC manuals: http://ana-3.lcs.mit.edu/~jnc/tech/pdp11/UNIBUS_Registers.txt (Ignore the name, it applies to QBUS machines too.) > bootstrap is reserved for 173000, how many words are allowed there for > this? Well, the space from 773000-773776 (UNIBUS and Q18 - add '17' to the front for Q22) is used for ROMs, and is the most common; 173000 is of course the location QBUS processors can be configured to jump to on power on. 765000-776 in also used for some (e.g. M9301's). > How do the more complicated bootstraps, e.g. microPDP11-53, accommodate > this limitation? Bank switching; e.g. the BDV11, KDF11-B have a 'page control register' at 777520 which says which block of ROM is mapped into the 773000 block. Interestingly, the DEC standard ROMs for the BDV11 and KDF11-B _don't_ copy all the contents down to real memory, and run from there - the code is divided into 'pages', only one of which is mapped in at a time, and it's executed from the ROM. Noel
Re: PDP11 I/O page memory map
> On Mar 1, 2018, at 6:12 AM, allison via cctalk wrote: > > ... and the MMU also > understands that peripherals live in that physical space be it 16/18/22 > bit memory map. That's true when the MMU is disabled; if so it supplies 1 bits for the upper bits for page 7, and zeroes for the other pages. But if the MMU is enabled, all mapping goes through its mapping registers, and page 7 is no longer special. By software convention, kernel data page 7 is configured to point to the I/O page, but that isn't required. If you wanted to be be perverse you could map the I/O page via page 6 and confuse a whole generation of programmers. paul
Re: PDP11 I/O page memory map
> On many of the PDP-11s that page is signified by asserting BBS7 QBUS machines only; the UNIBUS has no equivalent signal. > FYI the microPDP-11/53 is the 11/23+ cpu card Err, no; according to the "MicroPDP11/53 System Supplement Manual" (AZ-GPTAA-MC), pg. 3-1, the CPU card in the /53 is the KDJ11-D. The /23+ uses the KDF11-B CPU card. Noel
Re: PDP11 I/O page memory map
> From: Douglas Taylor > Is there a document that describes the bank 7 memory page and what > addresses are reserved for what? Here's one I collated from a large number of DEC manuals: http://ana-3.lcs.mit.edu/~jnc/tech/pdp11/UNIBUS_Registers.txt (Ignore the name, it applies to QBUS machines too.) > bootstrap is reserved for 173000, how many words are allowed there for > this? Well, the space from 773000-773776 (UNIBUS and Q18 - add '17' to the front for Q22) is used for ROMs, and is the most common; 173000 is of course the location QBUS processors can be configured to jump to on power on. 765000-776 in also used for some (e.g. M9301's). > How do the more complicated bootstraps, e.g. microPDP11-53, accommodate > this limitation? Bank switching; e.g. the BDV11, KDF11-B have a 'page control register' at 777520 which says which block of ROM is mapped into the 773000 block. Interestingly, the DEC standard ROMs for the BDV11 and KDF11-B _don't_ copy all the contents down to real memory, and run from there - the code is divided into 'pages', only one of which is mapped in at a time, and it's executed from the ROM. Noel
Re: PDP11 I/O page memory map
On 02/28/2018 08:15 PM, Douglas Taylor via cctalk wrote: > Is there a document that describes the bank 7 memory page and what > addresses are reserved for what? I think I've seen this before but > can't seem to put my hands on it. > > Another question, bootstrap is reserved for 173000, how many words are > allowed there for this? How do the more complicated bootstraps, e.g. > microPDP11-53, accommodate this limitation? > > Doug > I strongly suggest RTFM the PDP-11 handbooks. Till you do... Page 7 is the upper most memory area and is reserved as EPROM and IO peripherals. On many of the PDP-11s that page is signified by asserting BBS7 ( a partially decode address) and the MMU also understands that peripherals live in that physical space be it 16/18/22 bit memory map. Boot and diagnostic roms are a special case as more often their size was not limited to the area of bank 7 but the available devices of the day. They do however map roms so that they cannot overlap the IO devices. FYI the microPDP-11/53 is the 11/23+ cpu card so you can look that up. Allison
Re: PDP11 I/O page memory map
The various handbooks are useful. Processor, peripherals, and architecture handbooks all give parts of the picture. paul > On Feb 28, 2018, at 8:15 PM, Douglas Taylor via cctalk > wrote: > > Is there a document that describes the bank 7 memory page and what addresses > are reserved for what? I think I've seen this before but can't seem to put > my hands on it. > > Another question, bootstrap is reserved for 173000, how many words are > allowed there for this? How do the more complicated bootstraps, e.g. > microPDP11-53, accommodate this limitation? > > Doug >
PDP11 I/O page memory map
Is there a document that describes the bank 7 memory page and what addresses are reserved for what? I think I've seen this before but can't seem to put my hands on it. Another question, bootstrap is reserved for 173000, how many words are allowed there for this? How do the more complicated bootstraps, e.g. microPDP11-53, accommodate this limitation? Doug
