[PATCH] D82609: [PowerPC][Power10] Implement Vector Multiply High/Divide Extended Builtins in LLVM/Clang
anil9 added inline comments. Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:18 + // CHECK-NEXT: ret <4 x i32> + return vec_dive(vsia, vsib); +} I may be wrong but where are the variables declared ? I do not see the variables delclared above in the file, i mean many of them. Comment at: llvm/test/CodeGen/PowerPC/p10-vector-divide.ll:49 } + +declare <4 x i32> @llvm.ppc.altivec.vdivesw(<4 x i32>, <4 x i32>) nit : you put a comment right at this position in the multiply.ll file, for consistency you could add one here or remove the one there. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82609/new/ https://reviews.llvm.org/D82609 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend
anil9 added inline comments. Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:17 +unsigned int uia, *uiap; +signed int *ia; +signed short *sia; nit: It seems that most pull requests follow an ordering like first signed declaration and then unsigned, declaration, this one follows too , except the above two lines. And should the above declarations of chars, be along with these lines ? Comment at: llvm/test/CodeGen/PowerPC/p10-vsx-builtins.ll:56 + +; CHECK: lxvrdx +; Function Attrs: norecurse nounwind readonly I am not too familiar with the builtins but I never saw a check outside of the two braces in the test cases before, is it not posible to include it inside the test cases ? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82502/new/ https://reviews.llvm.org/D82502 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D80970: [PowerPC][Power10] Implement centrifuge, vector gather every nth bit, vector evaluate Builtins in LLVM/Clang
anil9 added inline comments. Comment at: clang/include/clang/Basic/BuiltinsPPC.def:305 +// P10 Vector Centrifuge +BUILTIN(__builtin_altivec_vcfuged, "V2ULLiV2ULLiV2ULLi", "") nit : // P10 Vector Centrifuge built-in. Comment at: clang/include/clang/Basic/BuiltinsPPC.def:308 + +// P10 Vector Gather Every N-th Bit +BUILTIN(__builtin_altivec_vgnb, "ULLiV1ULLLiIi", "") similar as above. Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:43 + // CHECK-NEXT: ret i64 + return vec_gnb(vui128a, 7); +} Try out some numbers which have different interpretation as signed/unsigned, if that matters that is. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80970/new/ https://reviews.llvm.org/D80970 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
